diff options
-rw-r--r-- | Makefile | 3 | ||||
-rw-r--r-- | bl1/bl1.ld.S | 12 | ||||
-rw-r--r-- | bl1/bl1_fwu.c | 14 | ||||
-rw-r--r-- | bl1/bl1_main.c | 14 | ||||
-rw-r--r-- | bl1/bl1_private.h | 12 | ||||
-rw-r--r-- | docs/plat/arm/fvp/index.rst | 18 | ||||
-rw-r--r-- | drivers/cfi/v2m/v2m_flash.c | 4 | ||||
-rw-r--r-- | include/bl1/bl1.h | 14 | ||||
-rw-r--r-- | include/lib/el3_runtime/aarch32/context.h | 8 | ||||
-rw-r--r-- | include/lib/el3_runtime/aarch64/context.h | 8 | ||||
-rw-r--r-- | lib/psci/psci_common.c | 4 | ||||
-rw-r--r-- | plat/arm/board/fvp/include/platform_def.h | 6 | ||||
-rw-r--r-- | services/spd/trusty/generic-arm64-smcall.c | 23 | ||||
-rw-r--r-- | services/spd/trusty/generic-arm64-smcall.h | 1 | ||||
-rw-r--r-- | services/spd/trusty/trusty.c | 4 | ||||
-rw-r--r-- | services/spd/tspd/tspd_main.c | 4 |
16 files changed, 96 insertions, 53 deletions
@@ -207,9 +207,10 @@ AS = $(CC) -c -x assembler-with-cpp $(TF_CFLAGS_$(ARCH)) CPP = $(CC) -E $(TF_CFLAGS_$(ARCH)) PP = $(CC) -E $(TF_CFLAGS_$(ARCH)) else ifneq ($(findstring clang,$(notdir $(CC))),) +CLANG_CCDIR = $(if $(filter-out ./,$(dir $(CC))),$(dir $(CC)),) TF_CFLAGS_aarch32 = $(target32-directive) $(march32-directive) TF_CFLAGS_aarch64 = -target aarch64-elf $(march64-directive) -LD = ld.lld +LD = $(CLANG_CCDIR)ld.lld ifeq (, $(shell which $(LD))) $(error "No $(LD) in PATH, make sure it is installed or set LD to a different linker") endif diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S index 877af8e015..b20859b5bb 100644 --- a/bl1/bl1.ld.S +++ b/bl1/bl1.ld.S @@ -65,8 +65,13 @@ SECTIONS * No need to pad out the .rodata section to a page boundary. Next is * the .data section, which can mapped in ROM with the same memory * attributes as the .rodata section. + * + * Pad out to 16 bytes though as .data section needs to be 16 byte + * aligned and lld does not align the LMA to the aligment specified + * on the .data section. */ __RODATA_END__ = .; + . = ALIGN(16); } >ROM #else ro . : { @@ -92,6 +97,13 @@ SECTIONS *(.vectors) __RO_END__ = .; + + /* + * Pad out to 16 bytes as .data section needs to be 16 byte aligned and + * lld does not align the LMA to the aligment specified on the .data + * section. + */ + . = ALIGN(16); } >ROM #endif diff --git a/bl1/bl1_fwu.c b/bl1/bl1_fwu.c index 48f08d2ca8..42a3ded5bd 100644 --- a/bl1/bl1_fwu.c +++ b/bl1/bl1_fwu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -55,11 +55,11 @@ static unsigned int sec_exec_image_id = INVALID_IMAGE_ID; /******************************************************************************* * Top level handler for servicing FWU SMCs. ******************************************************************************/ -register_t bl1_fwu_smc_handler(unsigned int smc_fid, - register_t x1, - register_t x2, - register_t x3, - register_t x4, +u_register_t bl1_fwu_smc_handler(unsigned int smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, void *cookie, void *handle, unsigned int flags) @@ -76,7 +76,7 @@ register_t bl1_fwu_smc_handler(unsigned int smc_fid, SMC_RET1(handle, bl1_fwu_image_execute(x1, &handle, flags)); case FWU_SMC_IMAGE_RESUME: - SMC_RET1(handle, bl1_fwu_image_resume(x1, &handle, flags)); + SMC_RET1(handle, bl1_fwu_image_resume((register_t)x1, &handle, flags)); case FWU_SMC_SEC_IMAGE_DONE: SMC_RET1(handle, bl1_fwu_sec_image_done(&handle, flags)); diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index bff8d22f51..e11ead6087 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -226,11 +226,11 @@ void print_debug_loop_message(void) /******************************************************************************* * Top level handler for servicing BL1 SMCs. ******************************************************************************/ -register_t bl1_smc_handler(unsigned int smc_fid, - register_t x1, - register_t x2, - register_t x3, - register_t x4, +u_register_t bl1_smc_handler(unsigned int smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, void *cookie, void *handle, unsigned int flags) @@ -269,12 +269,12 @@ register_t bl1_smc_handler(unsigned int smc_fid, * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI * compliance when invoking bl1_smc_handler. ******************************************************************************/ -register_t bl1_smc_wrapper(uint32_t smc_fid, +u_register_t bl1_smc_wrapper(uint32_t smc_fid, void *cookie, void *handle, unsigned int flags) { - register_t x1, x2, x3, x4; + u_register_t x1, x2, x3, x4; assert(handle != NULL); diff --git a/bl1/bl1_private.h b/bl1/bl1_private.h index 927c7b8a26..2cfeeea28d 100644 --- a/bl1/bl1_private.h +++ b/bl1/bl1_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,11 +19,11 @@ void bl1_arch_next_el_setup(void); void bl1_prepare_next_image(unsigned int image_id); -register_t bl1_fwu_smc_handler(unsigned int smc_fid, - register_t x1, - register_t x2, - register_t x3, - register_t x4, +u_register_t bl1_fwu_smc_handler(unsigned int smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, void *cookie, void *handle, unsigned int flags); diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index 37010e1a50..40e9661177 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -277,15 +277,15 @@ And the FVP binary can be run with the following command: -C cluster0.NUM_CORES=4 \ -C cluster1.NUM_CORES=4 \ -C cache_state_modelled=1 \ - -C cluster0.cpu0.RVBAR=0x04020000 \ - -C cluster0.cpu1.RVBAR=0x04020000 \ - -C cluster0.cpu2.RVBAR=0x04020000 \ - -C cluster0.cpu3.RVBAR=0x04020000 \ - -C cluster1.cpu0.RVBAR=0x04020000 \ - -C cluster1.cpu1.RVBAR=0x04020000 \ - -C cluster1.cpu2.RVBAR=0x04020000 \ - -C cluster1.cpu3.RVBAR=0x04020000 \ - --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000 \ + -C cluster0.cpu0.RVBAR=0x04001000 \ + -C cluster0.cpu1.RVBAR=0x04001000 \ + -C cluster0.cpu2.RVBAR=0x04001000 \ + -C cluster0.cpu3.RVBAR=0x04001000 \ + -C cluster1.cpu0.RVBAR=0x04001000 \ + -C cluster1.cpu1.RVBAR=0x04001000 \ + -C cluster1.cpu2.RVBAR=0x04001000 \ + -C cluster1.cpu3.RVBAR=0x04001000 \ + --data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000 \ --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \ --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000 diff --git a/drivers/cfi/v2m/v2m_flash.c b/drivers/cfi/v2m/v2m_flash.c index aadafbce23..6690189192 100644 --- a/drivers/cfi/v2m/v2m_flash.c +++ b/drivers/cfi/v2m/v2m_flash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,7 +27,7 @@ #define DWS_WORD_LOCK_RETRIES 1000 /* Helper macro to detect end of command */ -#define NOR_CMD_END (NOR_DWS | NOR_DWS << 16l) +#define NOR_CMD_END (NOR_DWS | (NOR_DWS << 16l)) /* Helper macros to access two flash banks in parallel */ #define NOR_2X16(d) ((d << 16) | (d & 0xffff)) diff --git a/include/bl1/bl1.h b/include/bl1/bl1.h index d81f434045..e6447f25bf 100644 --- a/include/bl1/bl1.h +++ b/include/bl1/bl1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -67,16 +67,16 @@ struct entry_point_info; -register_t bl1_smc_wrapper(uint32_t smc_fid, +u_register_t bl1_smc_wrapper(uint32_t smc_fid, void *cookie, void *handle, unsigned int flags); -register_t bl1_smc_handler(unsigned int smc_fid, - register_t x1, - register_t x2, - register_t x3, - register_t x4, +u_register_t bl1_smc_handler(unsigned int smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, void *cookie, void *handle, unsigned int flags); diff --git a/include/lib/el3_runtime/aarch32/context.h b/include/lib/el3_runtime/aarch32/context.h index c5567c974b..5604c8e502 100644 --- a/include/lib/el3_runtime/aarch32/context.h +++ b/include/lib/el3_runtime/aarch32/context.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -37,7 +37,7 @@ #define WORD_SHIFT U(2) #define DEFINE_REG_STRUCT(name, num_regs) \ typedef struct name { \ - uint32_t _regs[num_regs]; \ + uint32_t ctx_regs[num_regs]; \ } __aligned(8) name##_t /* Constants to determine the size of individual context structures */ @@ -47,8 +47,8 @@ DEFINE_REG_STRUCT(regs, CTX_REG_ALL); #undef CTX_REG_ALL -#define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> WORD_SHIFT]) -#define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[offset >> WORD_SHIFT]) \ +#define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[offset >> WORD_SHIFT]) +#define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[offset >> WORD_SHIFT]) \ = val) typedef struct cpu_context { regs_t regs_ctx; diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index 7a1f3a3a8c..4158c023ee 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -230,7 +230,7 @@ #define DWORD_SHIFT U(3) #define DEFINE_REG_STRUCT(name, num_regs) \ typedef struct name { \ - uint64_t _regs[num_regs]; \ + uint64_t ctx_regs[num_regs]; \ } __aligned(16) name##_t /* Constants to determine the size of individual context structures */ @@ -288,8 +288,8 @@ DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL); * Macros to access members of any of the above structures using their * offsets */ -#define read_ctx_reg(ctx, offset) ((ctx)->_regs[(offset) >> DWORD_SHIFT]) -#define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[(offset) >> DWORD_SHIFT]) \ +#define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) +#define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \ = (uint64_t) (val)) /* diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index 5ab15c6ee6..cced2761f5 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -601,7 +601,7 @@ void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, unsigned int level; /* Unlock top down. No unlocking required for level 0. */ - for (level = end_pwrlvl; level >= PSCI_CPU_PWR_LVL + 1U; level--) { + for (level = end_pwrlvl; level >= (PSCI_CPU_PWR_LVL + 1U); level--) { parent_idx = parent_nodes[level - 1U]; psci_lock_release(&psci_non_cpu_pd_nodes[parent_idx]); } diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 602ea6defa..bfe207a29b 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -116,12 +116,18 @@ # define PLAT_ARM_MAX_BL2_SIZE (UL(0x11000) - FVP_BL2_ROMLIB_OPTIMIZATION) #endif +#if RESET_TO_BL31 +/* Size of Trusted SRAM - the first 4KB of shared memory */ +#define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ + ARM_SHARED_RAM_SIZE) +#else /* * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is * calculated using the current BL31 PROGBITS debug size plus the sizes of * BL2 and BL1-RW */ #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) +#endif /* RESET_TO_BL31 */ #ifndef __aarch64__ /* diff --git a/services/spd/trusty/generic-arm64-smcall.c b/services/spd/trusty/generic-arm64-smcall.c index dfc3e71b75..5c3a628496 100644 --- a/services/spd/trusty/generic-arm64-smcall.c +++ b/services/spd/trusty/generic-arm64-smcall.c @@ -12,6 +12,22 @@ #include "generic-arm64-smcall.h" +#ifndef PLAT_ARM_GICD_BASE +#ifdef GICD_BASE +#define PLAT_ARM_GICD_BASE GICD_BASE +#define PLAT_ARM_GICC_BASE GICC_BASE +#ifdef GICR_BASE +#define PLAT_ARM_GICR_BASE GICR_BASE +#endif +#else +#error PLAT_ARM_GICD_BASE or GICD_BASE must be defined +#endif +#endif + +#ifndef PLAT_ARM_GICR_BASE +#define PLAT_ARM_GICR_BASE SMC_UNK +#endif + int trusty_disable_serial_debug; struct dputc_state { @@ -48,12 +64,15 @@ static void trusty_dputc(char ch, int secure) static uint64_t trusty_get_reg_base(uint32_t reg) { switch (reg) { - case 0: + case SMC_GET_GIC_BASE_GICD: return PLAT_ARM_GICD_BASE; - case 1: + case SMC_GET_GIC_BASE_GICC: return PLAT_ARM_GICC_BASE; + case SMC_GET_GIC_BASE_GICR: + return PLAT_ARM_GICR_BASE; + default: NOTICE("%s(0x%x) unknown reg\n", __func__, reg); return SMC_UNK; diff --git a/services/spd/trusty/generic-arm64-smcall.h b/services/spd/trusty/generic-arm64-smcall.h index 06efc722f7..ac0346924d 100644 --- a/services/spd/trusty/generic-arm64-smcall.h +++ b/services/spd/trusty/generic-arm64-smcall.h @@ -23,5 +23,6 @@ */ #define SMC_GET_GIC_BASE_GICD 0 #define SMC_GET_GIC_BASE_GICC 1 +#define SMC_GET_GIC_BASE_GICR 2 #define SMC_FC_GET_REG_BASE SMC_FASTCALL_NR(SMC_ENTITY_PLATFORM_MONITOR, 0x1) #define SMC_FC64_GET_REG_BASE SMC_FASTCALL64_NR(SMC_ENTITY_PLATFORM_MONITOR, 0x1) diff --git a/services/spd/trusty/trusty.c b/services/spd/trusty/trusty.c index d6c092cb7f..092ffa8eb9 100644 --- a/services/spd/trusty/trusty.c +++ b/services/spd/trusty/trusty.c @@ -390,6 +390,10 @@ static const spd_pm_ops_t trusty_pm = { void plat_trusty_set_boot_args(aapcs64_params_t *args); +#if !defined(TSP_SEC_MEM_SIZE) && defined(BL32_MEM_SIZE) +#define TSP_SEC_MEM_SIZE BL32_MEM_SIZE +#endif + #ifdef TSP_SEC_MEM_SIZE #pragma weak plat_trusty_set_boot_args void plat_trusty_set_boot_args(aapcs64_params_t *args) diff --git a/services/spd/tspd/tspd_main.c b/services/spd/tspd/tspd_main.c index f2067244e1..b0cbf625d2 100644 --- a/services/spd/tspd/tspd_main.c +++ b/services/spd/tspd/tspd_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -126,7 +126,7 @@ static uint64_t tspd_sel1_interrupt_handler(uint32_t id, * interrupt handling. */ if (get_yield_smc_active_flag(tsp_ctx->state)) { - tsp_ctx->saved_spsr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, + tsp_ctx->saved_spsr_el3 = (uint32_t)SMC_GET_EL3(&tsp_ctx->cpu_ctx, CTX_SPSR_EL3); tsp_ctx->saved_elr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, CTX_ELR_EL3); |