diff options
25 files changed, 361 insertions, 119 deletions
@@ -207,9 +207,10 @@ AS = $(CC) -c -x assembler-with-cpp $(TF_CFLAGS_$(ARCH)) CPP = $(CC) -E $(TF_CFLAGS_$(ARCH)) PP = $(CC) -E $(TF_CFLAGS_$(ARCH)) else ifneq ($(findstring clang,$(notdir $(CC))),) +CLANG_CCDIR = $(if $(filter-out ./,$(dir $(CC))),$(dir $(CC)),) TF_CFLAGS_aarch32 = $(target32-directive) $(march32-directive) TF_CFLAGS_aarch64 = -target aarch64-elf $(march64-directive) -LD = ld.lld +LD = $(CLANG_CCDIR)ld.lld ifeq (, $(shell which $(LD))) $(error "No $(LD) in PATH, make sure it is installed or set LD to a different linker") endif diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S index 877af8e015..b20859b5bb 100644 --- a/bl1/bl1.ld.S +++ b/bl1/bl1.ld.S @@ -65,8 +65,13 @@ SECTIONS * No need to pad out the .rodata section to a page boundary. Next is * the .data section, which can mapped in ROM with the same memory * attributes as the .rodata section. + * + * Pad out to 16 bytes though as .data section needs to be 16 byte + * aligned and lld does not align the LMA to the aligment specified + * on the .data section. */ __RODATA_END__ = .; + . = ALIGN(16); } >ROM #else ro . : { @@ -92,6 +97,13 @@ SECTIONS *(.vectors) __RO_END__ = .; + + /* + * Pad out to 16 bytes as .data section needs to be 16 byte aligned and + * lld does not align the LMA to the aligment specified on the .data + * section. + */ + . = ALIGN(16); } >ROM #endif diff --git a/bl1/bl1_fwu.c b/bl1/bl1_fwu.c index 48f08d2ca8..42a3ded5bd 100644 --- a/bl1/bl1_fwu.c +++ b/bl1/bl1_fwu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -55,11 +55,11 @@ static unsigned int sec_exec_image_id = INVALID_IMAGE_ID; /******************************************************************************* * Top level handler for servicing FWU SMCs. ******************************************************************************/ -register_t bl1_fwu_smc_handler(unsigned int smc_fid, - register_t x1, - register_t x2, - register_t x3, - register_t x4, +u_register_t bl1_fwu_smc_handler(unsigned int smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, void *cookie, void *handle, unsigned int flags) @@ -76,7 +76,7 @@ register_t bl1_fwu_smc_handler(unsigned int smc_fid, SMC_RET1(handle, bl1_fwu_image_execute(x1, &handle, flags)); case FWU_SMC_IMAGE_RESUME: - SMC_RET1(handle, bl1_fwu_image_resume(x1, &handle, flags)); + SMC_RET1(handle, bl1_fwu_image_resume((register_t)x1, &handle, flags)); case FWU_SMC_SEC_IMAGE_DONE: SMC_RET1(handle, bl1_fwu_sec_image_done(&handle, flags)); diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index bff8d22f51..e11ead6087 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -226,11 +226,11 @@ void print_debug_loop_message(void) /******************************************************************************* * Top level handler for servicing BL1 SMCs. ******************************************************************************/ -register_t bl1_smc_handler(unsigned int smc_fid, - register_t x1, - register_t x2, - register_t x3, - register_t x4, +u_register_t bl1_smc_handler(unsigned int smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, void *cookie, void *handle, unsigned int flags) @@ -269,12 +269,12 @@ register_t bl1_smc_handler(unsigned int smc_fid, * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI * compliance when invoking bl1_smc_handler. ******************************************************************************/ -register_t bl1_smc_wrapper(uint32_t smc_fid, +u_register_t bl1_smc_wrapper(uint32_t smc_fid, void *cookie, void *handle, unsigned int flags) { - register_t x1, x2, x3, x4; + u_register_t x1, x2, x3, x4; assert(handle != NULL); diff --git a/bl1/bl1_private.h b/bl1/bl1_private.h index 927c7b8a26..2cfeeea28d 100644 --- a/bl1/bl1_private.h +++ b/bl1/bl1_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,11 +19,11 @@ void bl1_arch_next_el_setup(void); void bl1_prepare_next_image(unsigned int image_id); -register_t bl1_fwu_smc_handler(unsigned int smc_fid, - register_t x1, - register_t x2, - register_t x3, - register_t x4, +u_register_t bl1_fwu_smc_handler(unsigned int smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, void *cookie, void *handle, unsigned int flags); diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index 37010e1a50..40e9661177 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -277,15 +277,15 @@ And the FVP binary can be run with the following command: -C cluster0.NUM_CORES=4 \ -C cluster1.NUM_CORES=4 \ -C cache_state_modelled=1 \ - -C cluster0.cpu0.RVBAR=0x04020000 \ - -C cluster0.cpu1.RVBAR=0x04020000 \ - -C cluster0.cpu2.RVBAR=0x04020000 \ - -C cluster0.cpu3.RVBAR=0x04020000 \ - -C cluster1.cpu0.RVBAR=0x04020000 \ - -C cluster1.cpu1.RVBAR=0x04020000 \ - -C cluster1.cpu2.RVBAR=0x04020000 \ - -C cluster1.cpu3.RVBAR=0x04020000 \ - --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000 \ + -C cluster0.cpu0.RVBAR=0x04001000 \ + -C cluster0.cpu1.RVBAR=0x04001000 \ + -C cluster0.cpu2.RVBAR=0x04001000 \ + -C cluster0.cpu3.RVBAR=0x04001000 \ + -C cluster1.cpu0.RVBAR=0x04001000 \ + -C cluster1.cpu1.RVBAR=0x04001000 \ + -C cluster1.cpu2.RVBAR=0x04001000 \ + -C cluster1.cpu3.RVBAR=0x04001000 \ + --data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000 \ --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \ --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000 diff --git a/drivers/cfi/v2m/v2m_flash.c b/drivers/cfi/v2m/v2m_flash.c index aadafbce23..6690189192 100644 --- a/drivers/cfi/v2m/v2m_flash.c +++ b/drivers/cfi/v2m/v2m_flash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,7 +27,7 @@ #define DWS_WORD_LOCK_RETRIES 1000 /* Helper macro to detect end of command */ -#define NOR_CMD_END (NOR_DWS | NOR_DWS << 16l) +#define NOR_CMD_END (NOR_DWS | (NOR_DWS << 16l)) /* Helper macros to access two flash banks in parallel */ #define NOR_2X16(d) ((d << 16) | (d & 0xffff)) diff --git a/fdts/corstone700.dts b/fdts/corstone700.dts index 16cf412277..c13d3b23e2 100644 --- a/fdts/corstone700.dts +++ b/fdts/corstone700.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,9 +14,10 @@ #size-cells = <1>; chosen { - bootargs = "console=ttyAMA0 root=/dev/vda2 rw loglevel=9"; - linux,initrd-start = <0x02a00000>; - linux,initrd-end = <0x04000000>; + bootargs = "console=ttyAMA0 \ + root=mtd:physmap-flash.0 \ + ro \ + loglevel=9"; }; cpus { @@ -32,9 +33,9 @@ }; - memory@2000000 { + memory@80000000 { device_type = "memory"; - reg = <0x02000000 0x02000000>; + reg = <0x80000000 0x80000000>; }; gic: interrupt-controller@1c000000 { @@ -68,14 +69,21 @@ clock-output-names = "smclk"; }; + uartclk: uartclk { + /* UART clock - 32MHz */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000000>; + clock-output-names = "uartclk"; + }; serial0: uart@1a510000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x1a510000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 19 4>; - clocks = <&refclk100mhz>, <&smbclk>; - clock-names = "apb_pclk", "smclk"; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; }; serial1: uart@1a520000 { @@ -83,8 +91,8 @@ reg = <0x1a520000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 20 4>; - clocks = <&refclk100mhz>, <&smbclk>; - clock-names = "apb_pclk", "smclk"; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; }; timer { diff --git a/include/bl1/bl1.h b/include/bl1/bl1.h index d81f434045..e6447f25bf 100644 --- a/include/bl1/bl1.h +++ b/include/bl1/bl1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -67,16 +67,16 @@ struct entry_point_info; -register_t bl1_smc_wrapper(uint32_t smc_fid, +u_register_t bl1_smc_wrapper(uint32_t smc_fid, void *cookie, void *handle, unsigned int flags); -register_t bl1_smc_handler(unsigned int smc_fid, - register_t x1, - register_t x2, - register_t x3, - register_t x4, +u_register_t bl1_smc_handler(unsigned int smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, void *cookie, void *handle, unsigned int flags); diff --git a/include/lib/el3_runtime/aarch32/context.h b/include/lib/el3_runtime/aarch32/context.h index c5567c974b..5604c8e502 100644 --- a/include/lib/el3_runtime/aarch32/context.h +++ b/include/lib/el3_runtime/aarch32/context.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -37,7 +37,7 @@ #define WORD_SHIFT U(2) #define DEFINE_REG_STRUCT(name, num_regs) \ typedef struct name { \ - uint32_t _regs[num_regs]; \ + uint32_t ctx_regs[num_regs]; \ } __aligned(8) name##_t /* Constants to determine the size of individual context structures */ @@ -47,8 +47,8 @@ DEFINE_REG_STRUCT(regs, CTX_REG_ALL); #undef CTX_REG_ALL -#define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> WORD_SHIFT]) -#define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[offset >> WORD_SHIFT]) \ +#define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[offset >> WORD_SHIFT]) +#define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[offset >> WORD_SHIFT]) \ = val) typedef struct cpu_context { regs_t regs_ctx; diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index 7a1f3a3a8c..4158c023ee 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -230,7 +230,7 @@ #define DWORD_SHIFT U(3) #define DEFINE_REG_STRUCT(name, num_regs) \ typedef struct name { \ - uint64_t _regs[num_regs]; \ + uint64_t ctx_regs[num_regs]; \ } __aligned(16) name##_t /* Constants to determine the size of individual context structures */ @@ -288,8 +288,8 @@ DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL); * Macros to access members of any of the above structures using their * offsets */ -#define read_ctx_reg(ctx, offset) ((ctx)->_regs[(offset) >> DWORD_SHIFT]) -#define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[(offset) >> DWORD_SHIFT]) \ +#define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) +#define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \ = (uint64_t) (val)) /* diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index 5ab15c6ee6..cced2761f5 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -601,7 +601,7 @@ void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, unsigned int level; /* Unlock top down. No unlocking required for level 0. */ - for (level = end_pwrlvl; level >= PSCI_CPU_PWR_LVL + 1U; level--) { + for (level = end_pwrlvl; level >= (PSCI_CPU_PWR_LVL + 1U); level--) { parent_idx = parent_nodes[level - 1U]; psci_lock_release(&psci_non_cpu_pd_nodes[parent_idx]); } diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk index 1fa26cc2bc..b6925d3b15 100644 --- a/make_helpers/build_macros.mk +++ b/make_helpers/build_macros.mk @@ -67,6 +67,17 @@ $(foreach d,$(0-9),$(eval __numeric := $(subst $(d),,$(__numeric)))) $(if $(__numeric),$(error $(1) must be numeric)) endef +# CREATE_SEQ is a recursive function to create sequence of numbers from 1 to +# $(2) and assign the sequence to $(1) +define CREATE_SEQ +$(if $(word $(2), $($(1))),\ + $(eval $(1) += $(words $($(1))))\ + $(eval $(1) := $(filter-out 0,$($(1)))),\ + $(eval $(1) += $(words $($(1))))\ + $(call CREATE_SEQ,$(1),$(2))\ +) +endef + # IMG_LINKERFILE defines the linker script corresponding to a BL stage # $(1) = BL stage (2, 30, 31, 32, 33) define IMG_LINKERFILE diff --git a/plat/arm/board/corstone700/corstone700_plat.c b/plat/arm/board/corstone700/corstone700_plat.c index cee6fd618c..e2ade70983 100644 --- a/plat/arm/board/corstone700/corstone700_plat.c +++ b/plat/arm/board/corstone700/corstone700_plat.c @@ -1,10 +1,12 @@ /* - * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <common/bl_common.h> + +#include <mhu.h> #include <plat/arm/common/plat_arm.h> #include <plat/common/platform.h> #include <platform_def.h> @@ -26,6 +28,7 @@ const mmap_region_t plat_arm_mmap[] = { */ void __init plat_arm_pwrc_setup(void) { + mhu_secure_init(); } unsigned int plat_get_syscnt_freq2(void) diff --git a/plat/arm/board/corstone700/corstone700_topology.c b/plat/arm/board/corstone700/corstone700_topology.c index d9445e0c56..904f5ab3a5 100644 --- a/plat/arm/board/corstone700/corstone700_topology.c +++ b/plat/arm/board/corstone700/corstone700_topology.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,8 +8,8 @@ #include <plat/common/platform.h> /* The Corstone700 power domain tree descriptor */ -static unsigned char corstone700_power_domain_tree_desc - [PLAT_ARM_CLUSTER_COUNT + 2]; +static unsigned char corstone700_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT + + 2]; /******************************************************************************* * This function dynamically constructs the topology according to * CLUSTER_COUNT and returns it. diff --git a/plat/arm/board/corstone700/drivers/mhu/mhu.c b/plat/arm/board/corstone700/drivers/mhu/mhu.c new file mode 100644 index 0000000000..2231d11734 --- /dev/null +++ b/plat/arm/board/corstone700/drivers/mhu/mhu.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> + +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/delay_timer.h> +#include <lib/bakery_lock.h> +#include <lib/mmio.h> + +#include "mhu.h" +#include <plat_arm.h> +#include <platform_def.h> + +ARM_INSTANTIATE_LOCK; + +#pragma weak plat_arm_pwrc_setup + +/* + * Slot 31 is reserved because the MHU hardware uses this register bit to + * indicate a non-secure access attempt. The total number of available slots is + * therefore 31 [30:0]. + */ +#define MHU_MAX_SLOT_ID 30 + +void mhu_secure_message_start(uintptr_t address, unsigned int slot_id) +{ + unsigned int intr_stat_check; + uint64_t timeout_cnt; + volatile uint8_t expiration; + + assert(slot_id <= MHU_MAX_SLOT_ID); + arm_lock_get(); + + /* + * Make sure any previous command has finished + * and polling timeout not expired + */ + + timeout_cnt = timeout_init_us(MHU_POLL_INTR_STAT_TIMEOUT); + + do { + intr_stat_check = (mmio_read_32(address + CPU_INTR_S_STAT) & + (1 << slot_id)); + + expiration = timeout_elapsed(timeout_cnt); + + } while ((intr_stat_check != 0U) && (expiration == 0U)); + + /* + * Note: No risk of timer overflows while waiting + * for the timeout expiration. + * According to Armv8 TRM: System counter roll-over + * time of not less than 40 years + */ +} + +void mhu_secure_message_send(uintptr_t address, + unsigned int slot_id, + unsigned int message) +{ + unsigned char access_ready; + uint64_t timeout_cnt; + volatile uint8_t expiration; + + assert(slot_id <= MHU_MAX_SLOT_ID); + assert((mmio_read_32(address + CPU_INTR_S_STAT) & + (1 << slot_id)) == 0U); + + MHU_V2_ACCESS_REQUEST(address); + + timeout_cnt = timeout_init_us(MHU_POLL_INTR_STAT_TIMEOUT); + + do { + access_ready = MHU_V2_IS_ACCESS_READY(address); + expiration = timeout_elapsed(timeout_cnt); + + } while ((access_ready == 0U) && (expiration == 0U)); + + /* + * Note: No risk of timer overflows while waiting + * for the timeout expiration. + * According to Armv8 TRM: System counter roll-over + * time of not less than 40 years + */ + + mmio_write_32(address + CPU_INTR_S_SET, message); +} + +void mhu_secure_message_end(uintptr_t address, unsigned int slot_id) +{ + assert(slot_id <= MHU_MAX_SLOT_ID); + /* + * Clear any response we got by writing one in the relevant slot bit to + * the CLEAR register + */ + MHU_V2_CLEAR_REQUEST(address); + + arm_lock_release(); +} + +void __init mhu_secure_init(void) +{ + arm_lock_init(); + + /* + * The STAT register resets to zero. Ensure it is in the expected state, + * as a stale or garbage value would make us think it's a message we've + * already sent. + */ + + assert(mmio_read_32(PLAT_SDK700_MHU0_SEND + CPU_INTR_S_STAT) == 0); +} diff --git a/plat/arm/board/corstone700/drivers/mhu/mhu.h b/plat/arm/board/corstone700/drivers/mhu/mhu.h new file mode 100644 index 0000000000..3808746e9c --- /dev/null +++ b/plat/arm/board/corstone700/drivers/mhu/mhu.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MHU_H +#define MHU_H + +#define MHU_POLL_INTR_STAT_TIMEOUT 50000 /*timeout value in us*/ + +/* CPU MHU secure channel registers */ +#define CPU_INTR_S_STAT 0x00 +#define CPU_INTR_S_SET 0x0C + +/* MHUv2 Control Registers Offsets */ +#define MHU_V2_MSG_CFG_OFFSET 0xF80 +#define MHU_V2_ACCESS_REQ_OFFSET 0xF88 +#define MHU_V2_ACCESS_READY_OFFSET 0xF8C + +#define MHU_V2_ACCESS_REQUEST(addr) \ + mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x1) + +#define MHU_V2_CLEAR_REQUEST(addr) \ + mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x0) + +#define MHU_V2_IS_ACCESS_READY(addr) \ + (mmio_read_32((addr) + MHU_V2_ACCESS_READY_OFFSET) & 0x1) + +void mhu_secure_message_start(uintptr_t address, unsigned int slot_id); +void mhu_secure_message_send(uintptr_t address, + unsigned int slot_id, + unsigned int message); +void mhu_secure_message_end(uintptr_t address, unsigned int slot_id); +void mhu_secure_init(void); + +#endif /* MHU_H */ diff --git a/plat/arm/board/corstone700/include/platform_def.h b/plat/arm/board/corstone700/include/platform_def.h index 8dff3ec3fb..0fb74e442e 100644 --- a/plat/arm/board/corstone700/include/platform_def.h +++ b/plat/arm/board/corstone700/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,20 +9,35 @@ #include <lib/utils_def.h> #include <lib/xlat_tables/xlat_tables_defs.h> + #include <plat/arm/board/common/v2m_def.h> #include <plat/arm/common/arm_spm_def.h> #include <plat/common/common_def.h> +/* PL011 UART related constants */ +#ifdef V2M_IOFPGA_UART0_CLK_IN_HZ +#undef V2M_IOFPGA_UART0_CLK_IN_HZ +#endif + +#ifdef V2M_IOFPGA_UART1_CLK_IN_HZ +#undef V2M_IOFPGA_UART1_CLK_IN_HZ +#endif + +#define V2M_IOFPGA_UART0_CLK_IN_HZ 32000000 +#define V2M_IOFPGA_UART1_CLK_IN_HZ 32000000 + /* Core/Cluster/Thread counts for Corstone700 */ #define CORSTONE700_CLUSTER_COUNT U(1) #define CORSTONE700_MAX_CPUS_PER_CLUSTER U(4) #define CORSTONE700_MAX_PE_PER_CPU U(1) -#define CORSTONE700_CORE_COUNT (CORSTONE700_CLUSTER_COUNT * \ - CORSTONE700_MAX_CPUS_PER_CLUSTER * \ - CORSTONE700_MAX_PE_PER_CPU) -#define PLATFORM_CORE_COUNT CORSTONE700_CORE_COUNT + #define PLAT_ARM_CLUSTER_COUNT CORSTONE700_CLUSTER_COUNT +#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ + CORSTONE700_MAX_CPUS_PER_CLUSTER * \ + CORSTONE700_MAX_PE_PER_CPU) + + /* UART related constants */ #define PLAT_ARM_BOOT_UART_BASE 0x1a510000 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ @@ -85,8 +100,12 @@ ARM_BL_REGIONS) /* GIC related constants */ -#define PLAT_ARM_GICD_BASE 0x1C010000 -#define PLAT_ARM_GICC_BASE 0x1C02F000 +#define PLAT_ARM_GICD_BASE 0x1C010000 +#define PLAT_ARM_GICC_BASE 0x1C02F000 + +/* MHUv2 Secure Channel receiver and sender */ +#define PLAT_SDK700_MHU0_SEND 0x1B800000 +#define PLAT_SDK700_MHU0_RECV 0x1B810000 /* Timer/watchdog related constants */ #define ARM_SYS_CNTCTL_BASE UL(0x1a200000) @@ -101,46 +120,46 @@ * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The * power levels have a 1:1 mapping with the MPIDR affinity levels. */ -#define ARM_PWR_LVL0 MPIDR_AFFLVL0 -#define ARM_PWR_LVL1 MPIDR_AFFLVL1 -#define ARM_PWR_LVL2 MPIDR_AFFLVL2 +#define ARM_PWR_LVL0 MPIDR_AFFLVL0 +#define ARM_PWR_LVL1 MPIDR_AFFLVL1 +#define ARM_PWR_LVL2 MPIDR_AFFLVL2 /* * Macros for local power states in ARM platforms encoded by State-ID field * within the power-state parameter. */ /* Local power state for power domains in Run state. */ -#define ARM_LOCAL_STATE_RUN U(0) +#define ARM_LOCAL_STATE_RUN U(0) /* Local power state for retention. Valid only for CPU power domains */ -#define ARM_LOCAL_STATE_RET U(1) +#define ARM_LOCAL_STATE_RET U(1) /* Local power state for OFF/power-down. Valid for CPU and cluster * power domains */ -#define ARM_LOCAL_STATE_OFF U(2) +#define ARM_LOCAL_STATE_OFF U(2) -#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE -#define PLAT_ARM_NSTIMER_FRAME_ID U(1) +#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE +#define PLAT_ARM_NSTIMER_FRAME_ID U(1) -#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + UL(0x8000000)) +#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + UL(0x8000000)) -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) /* * This macro defines the deepest retention state possible. A higher state * ID will represent an invalid or a power down state. */ -#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_RET_STATE 1 /* * This macro defines the deepest power down states possible. Any state ID * higher than this is invalid. */ -#define PLAT_MAX_OFF_STATE 2 +#define PLAT_MAX_OFF_STATE 2 -#define PLATFORM_STACK_SIZE UL(0x440) +#define PLATFORM_STACK_SIZE UL(0x440) -#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ +#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ ARM_SHARED_RAM_BASE, \ ARM_SHARED_RAM_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) @@ -170,21 +189,21 @@ #define CORSTONE700_DEVICE_BASE (0x1A000000) #define CORSTONE700_DEVICE_SIZE (0x26000000) -#define CORSTONE700_MAP_DEVICE MAP_REGION_FLAT( \ - CORSTONE700_DEVICE_BASE, \ - CORSTONE700_DEVICE_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define ARM_IRQ_SEC_PHY_TIMER 29 - -#define ARM_IRQ_SEC_SGI_0 8 -#define ARM_IRQ_SEC_SGI_1 9 -#define ARM_IRQ_SEC_SGI_2 10 -#define ARM_IRQ_SEC_SGI_3 11 -#define ARM_IRQ_SEC_SGI_4 12 -#define ARM_IRQ_SEC_SGI_5 13 -#define ARM_IRQ_SEC_SGI_6 14 -#define ARM_IRQ_SEC_SGI_7 15 +#define CORSTONE700_MAP_DEVICE MAP_REGION_FLAT( \ + CORSTONE700_DEVICE_BASE,\ + CORSTONE700_DEVICE_SIZE,\ + MT_DEVICE | MT_RW | MT_SECURE) + +#define ARM_IRQ_SEC_PHY_TIMER 29 + +#define ARM_IRQ_SEC_SGI_0 8 +#define ARM_IRQ_SEC_SGI_1 9 +#define ARM_IRQ_SEC_SGI_2 10 +#define ARM_IRQ_SEC_SGI_3 11 +#define ARM_IRQ_SEC_SGI_4 12 +#define ARM_IRQ_SEC_SGI_5 13 +#define ARM_IRQ_SEC_SGI_6 14 +#define ARM_IRQ_SEC_SGI_7 15 /* * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 @@ -192,7 +211,7 @@ * as Group 0 interrupts. */ #define ARM_G1S_IRQ_PROPS(grp) \ - INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ (grp), GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ (grp), GIC_INTR_CFG_EDGE), \ @@ -217,11 +236,11 @@ * as Group 0 interrupts. */ #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ - ARM_G1S_IRQ_PROPS(grp), \ - INTR_PROP_DESC(CORSTONE700_IRQ_TZ_WDOG, \ - GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(CORSTONE700_IRQ_SEC_SYS_TIMER, \ - GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL) \ + ARM_G1S_IRQ_PROPS(grp), \ + INTR_PROP_DESC(CORSTONE700_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \ + (grp), GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(CORSTONE700_IRQ_SEC_SYS_TIMER, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL) #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) diff --git a/plat/arm/board/corstone700/platform.mk b/plat/arm/board/corstone700/platform.mk index bff3589eb6..a4d4f2227c 100644 --- a/plat/arm/board/corstone700/platform.mk +++ b/plat/arm/board/corstone700/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -11,16 +11,19 @@ BL32_SOURCES += plat/arm/common/aarch32/arm_helpers.S \ plat/arm/common/arm_common.c \ lib/xlat_tables/aarch32/xlat_tables.c \ lib/xlat_tables/xlat_tables_common.c \ - ${CORSTONE700_CPU_LIBS} + ${CORSTONE700_CPU_LIBS} \ + plat/arm/board/corstone700/drivers/mhu/mhu.c -PLAT_INCLUDES := -Iplat/arm/board/corstone700/include +PLAT_INCLUDES := -Iplat/arm/board/corstone700/include \ + -Iinclude/plat/arm/common \ + -Iplat/arm/board/corstone700/drivers/mhu NEED_BL32 := yes -CORSTONE700_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ - drivers/arm/gic/v2/gicv2_main.c \ - drivers/arm/gic/v2/gicv2_helpers.c \ - plat/common/plat_gicv2.c \ +CORSTONE700_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + plat/common/plat_gicv2.c \ plat/arm/common/arm_gicv2.c # BL1/BL2 Image not a part of the capsule Image for Corstone700 diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 602ea6defa..bfe207a29b 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -116,12 +116,18 @@ # define PLAT_ARM_MAX_BL2_SIZE (UL(0x11000) - FVP_BL2_ROMLIB_OPTIMIZATION) #endif +#if RESET_TO_BL31 +/* Size of Trusted SRAM - the first 4KB of shared memory */ +#define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ + ARM_SHARED_RAM_SIZE) +#else /* * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is * calculated using the current BL31 PROGBITS debug size plus the sizes of * BL2 and BL1-RW */ #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) +#endif /* RESET_TO_BL31 */ #ifndef __aarch64__ /* diff --git a/plat/arm/board/rdn1edge/platform.mk b/plat/arm/board/rdn1edge/platform.mk index 99bb71d792..135676d43b 100644 --- a/plat/arm/board/rdn1edge/platform.mk +++ b/plat/arm/board/rdn1edge/platform.mk @@ -51,8 +51,9 @@ NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb # Add the NT_FW_CONFIG to FIP and specify the same to certtool $(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config)) -ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),1 2)) - $(error "Chip count for RDN1Edge platform should either 1 or 2, currently \ +$(eval $(call CREATE_SEQ,SEQ,2)) +ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ))) + $(error "Chip count for RDN1Edge platform should be one of $(SEQ), currently \ set to ${CSS_SGI_CHIP_COUNT}.") endif diff --git a/services/spd/trusty/generic-arm64-smcall.c b/services/spd/trusty/generic-arm64-smcall.c index dfc3e71b75..5c3a628496 100644 --- a/services/spd/trusty/generic-arm64-smcall.c +++ b/services/spd/trusty/generic-arm64-smcall.c @@ -12,6 +12,22 @@ #include "generic-arm64-smcall.h" +#ifndef PLAT_ARM_GICD_BASE +#ifdef GICD_BASE +#define PLAT_ARM_GICD_BASE GICD_BASE +#define PLAT_ARM_GICC_BASE GICC_BASE +#ifdef GICR_BASE +#define PLAT_ARM_GICR_BASE GICR_BASE +#endif +#else +#error PLAT_ARM_GICD_BASE or GICD_BASE must be defined +#endif +#endif + +#ifndef PLAT_ARM_GICR_BASE +#define PLAT_ARM_GICR_BASE SMC_UNK +#endif + int trusty_disable_serial_debug; struct dputc_state { @@ -48,12 +64,15 @@ static void trusty_dputc(char ch, int secure) static uint64_t trusty_get_reg_base(uint32_t reg) { switch (reg) { - case 0: + case SMC_GET_GIC_BASE_GICD: return PLAT_ARM_GICD_BASE; - case 1: + case SMC_GET_GIC_BASE_GICC: return PLAT_ARM_GICC_BASE; + case SMC_GET_GIC_BASE_GICR: + return PLAT_ARM_GICR_BASE; + default: NOTICE("%s(0x%x) unknown reg\n", __func__, reg); return SMC_UNK; diff --git a/services/spd/trusty/generic-arm64-smcall.h b/services/spd/trusty/generic-arm64-smcall.h index 06efc722f7..ac0346924d 100644 --- a/services/spd/trusty/generic-arm64-smcall.h +++ b/services/spd/trusty/generic-arm64-smcall.h @@ -23,5 +23,6 @@ */ #define SMC_GET_GIC_BASE_GICD 0 #define SMC_GET_GIC_BASE_GICC 1 +#define SMC_GET_GIC_BASE_GICR 2 #define SMC_FC_GET_REG_BASE SMC_FASTCALL_NR(SMC_ENTITY_PLATFORM_MONITOR, 0x1) #define SMC_FC64_GET_REG_BASE SMC_FASTCALL64_NR(SMC_ENTITY_PLATFORM_MONITOR, 0x1) diff --git a/services/spd/trusty/trusty.c b/services/spd/trusty/trusty.c index d6c092cb7f..092ffa8eb9 100644 --- a/services/spd/trusty/trusty.c +++ b/services/spd/trusty/trusty.c @@ -390,6 +390,10 @@ static const spd_pm_ops_t trusty_pm = { void plat_trusty_set_boot_args(aapcs64_params_t *args); +#if !defined(TSP_SEC_MEM_SIZE) && defined(BL32_MEM_SIZE) +#define TSP_SEC_MEM_SIZE BL32_MEM_SIZE +#endif + #ifdef TSP_SEC_MEM_SIZE #pragma weak plat_trusty_set_boot_args void plat_trusty_set_boot_args(aapcs64_params_t *args) diff --git a/services/spd/tspd/tspd_main.c b/services/spd/tspd/tspd_main.c index f2067244e1..b0cbf625d2 100644 --- a/services/spd/tspd/tspd_main.c +++ b/services/spd/tspd/tspd_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -126,7 +126,7 @@ static uint64_t tspd_sel1_interrupt_handler(uint32_t id, * interrupt handling. */ if (get_yield_smc_active_flag(tsp_ctx->state)) { - tsp_ctx->saved_spsr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, + tsp_ctx->saved_spsr_el3 = (uint32_t)SMC_GET_EL3(&tsp_ctx->cpu_ctx, CTX_SPSR_EL3); tsp_ctx->saved_elr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, CTX_ELR_EL3); |