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-rw-r--r--.editorconfig6
-rw-r--r--.gitignore4
-rw-r--r--Makefile73
-rw-r--r--bl1/bl1.mk6
-rw-r--r--bl2/bl2.mk6
-rw-r--r--bl31/aarch64/ea_delegate.S4
-rw-r--r--bl31/aarch64/runtime_exceptions.S94
-rw-r--r--bl31/bl31.mk10
-rw-r--r--bl32/sp_min/sp_min.mk11
-rw-r--r--docs/about/maintainers.rst43
-rw-r--r--docs/change-log.rst6
-rw-r--r--docs/design/cpu-specific-build-macros.rst17
-rw-r--r--docs/getting_started/build-options.rst15
-rw-r--r--docs/getting_started/porting-guide.rst49
-rw-r--r--docs/global_substitutions.txt1
-rw-r--r--docs/glossary.rst3
-rw-r--r--docs/plat/arm/arm-build-options.rst4
-rw-r--r--docs/plat/arm/fvp/index.rst8
-rw-r--r--docs/plat/index.rst1
-rw-r--r--docs/plat/marvell/armada/build.rst135
-rw-r--r--docs/plat/marvell/armada/misc/mvebu-ccu.rst2
-rw-r--r--docs/plat/marvell/armada/misc/mvebu-io-win.rst2
-rw-r--r--docs/plat/marvell/armada/misc/mvebu-iob.rst2
-rw-r--r--docs/plat/rpi4.rst2
-rw-r--r--docs/plat/rz-g2.rst228
-rw-r--r--docs/plat/stm32mp1.rst2
-rw-r--r--docs/resources/diagrams/plantuml/fip-secure-partitions.puml95
-rw-r--r--drivers/arm/tzc/tzc400.c11
-rw-r--r--drivers/cadence/uart/aarch64/cdns_console.S8
-rw-r--r--drivers/marvell/uart/a3700_console.S32
-rw-r--r--drivers/renesas/common/auth/auth_mod.c (renamed from drivers/renesas/rcar/auth/auth_mod.c)27
-rw-r--r--drivers/renesas/common/avs/avs_driver.c (renamed from drivers/renesas/rcar/avs/avs_driver.c)74
-rw-r--r--drivers/renesas/common/avs/avs_driver.h (renamed from drivers/renesas/rcar/avs/avs_driver.h)0
-rw-r--r--drivers/renesas/common/common.c37
-rw-r--r--drivers/renesas/common/console/rcar_console.S (renamed from drivers/renesas/rcar/console/rcar_console.S)0
-rw-r--r--drivers/renesas/common/console/rcar_printf.c (renamed from drivers/renesas/rcar/console/rcar_printf.c)37
-rw-r--r--drivers/renesas/common/console/rcar_printf.h (renamed from drivers/renesas/rcar/console/rcar_printf.h)0
-rw-r--r--drivers/renesas/common/ddr_regs.h (renamed from drivers/renesas/rcar/ddr/ddr_regs.h)0
-rw-r--r--drivers/renesas/common/delay/micro_delay.c (renamed from drivers/renesas/rcar/delay/micro_delay.c)5
-rw-r--r--drivers/renesas/common/delay/micro_delay.h (renamed from drivers/renesas/rcar/delay/micro_delay.h)0
-rw-r--r--drivers/renesas/common/dma/dma_driver.c (renamed from drivers/renesas/rcar/dma/dma_driver.c)50
-rw-r--r--drivers/renesas/common/emmc/emmc_cmd.c (renamed from drivers/renesas/rcar/emmc/emmc_cmd.c)37
-rw-r--r--drivers/renesas/common/emmc/emmc_config.h20
-rw-r--r--drivers/renesas/common/emmc/emmc_def.h (renamed from drivers/renesas/rcar/emmc/emmc_def.h)0
-rw-r--r--drivers/renesas/common/emmc/emmc_hal.h535
-rw-r--r--drivers/renesas/common/emmc/emmc_init.c (renamed from drivers/renesas/rcar/emmc/emmc_init.c)35
-rw-r--r--drivers/renesas/common/emmc/emmc_interrupt.c (renamed from drivers/renesas/rcar/emmc/emmc_interrupt.c)8
-rw-r--r--drivers/renesas/common/emmc/emmc_mount.c (renamed from drivers/renesas/rcar/emmc/emmc_mount.c)85
-rw-r--r--drivers/renesas/common/emmc/emmc_read.c (renamed from drivers/renesas/rcar/emmc/emmc_read.c)15
-rw-r--r--drivers/renesas/common/emmc/emmc_registers.h228
-rw-r--r--drivers/renesas/common/emmc/emmc_std.h475
-rw-r--r--drivers/renesas/common/emmc/emmc_utility.c (renamed from drivers/renesas/rcar/emmc/emmc_utility.c)12
-rw-r--r--drivers/renesas/common/iic_dvfs/iic_dvfs.c (renamed from drivers/renesas/rcar/iic_dvfs/iic_dvfs.c)259
-rw-r--r--drivers/renesas/common/iic_dvfs/iic_dvfs.h (renamed from drivers/renesas/rcar/iic_dvfs/iic_dvfs.h)14
-rw-r--r--drivers/renesas/common/io/io_common.h (renamed from drivers/renesas/rcar/io/io_common.h)0
-rw-r--r--drivers/renesas/common/io/io_emmcdrv.c (renamed from drivers/renesas/rcar/io/io_emmcdrv.c)38
-rw-r--r--drivers/renesas/common/io/io_emmcdrv.h (renamed from drivers/renesas/rcar/io/io_emmcdrv.h)0
-rw-r--r--drivers/renesas/common/io/io_memdrv.c (renamed from drivers/renesas/rcar/io/io_memdrv.c)19
-rw-r--r--drivers/renesas/common/io/io_memdrv.h (renamed from drivers/renesas/rcar/io/io_memdrv.h)0
-rw-r--r--drivers/renesas/common/io/io_private.h (renamed from drivers/renesas/rcar/io/io_private.h)0
-rw-r--r--drivers/renesas/common/io/io_rcar.c (renamed from drivers/renesas/rcar/io/io_rcar.c)109
-rw-r--r--drivers/renesas/common/io/io_rcar.h (renamed from drivers/renesas/rcar/io/io_rcar.h)0
-rw-r--r--drivers/renesas/common/pfc_regs.h (renamed from drivers/renesas/rcar/pfc/pfc_regs.h)0
-rw-r--r--drivers/renesas/common/pwrc/call_sram.S (renamed from drivers/renesas/rcar/pwrc/call_sram.S)0
-rw-r--r--drivers/renesas/common/pwrc/pwrc.c (renamed from drivers/renesas/rcar/pwrc/pwrc.c)261
-rw-r--r--drivers/renesas/common/pwrc/pwrc.h (renamed from drivers/renesas/rcar/pwrc/pwrc.h)10
-rw-r--r--drivers/renesas/common/qos_reg.h (renamed from drivers/renesas/rcar/qos/qos_reg.h)0
-rw-r--r--drivers/renesas/common/rom/rom_api.c (renamed from drivers/renesas/rcar/rom/rom_api.c)0
-rw-r--r--drivers/renesas/common/rom/rom_api.h (renamed from drivers/renesas/rcar/rom/rom_api.h)0
-rw-r--r--drivers/renesas/common/rpc/rpc_driver.c (renamed from drivers/renesas/rcar/rpc/rpc_driver.c)0
-rw-r--r--drivers/renesas/common/rpc/rpc_registers.h (renamed from drivers/renesas/rcar/rpc/rpc_registers.h)0
-rw-r--r--drivers/renesas/common/scif/scif.S (renamed from drivers/renesas/rcar/scif/scif.S)176
-rw-r--r--drivers/renesas/common/watchdog/swdt.c (renamed from drivers/renesas/rcar/watchdog/swdt.c)4
-rw-r--r--drivers/renesas/rcar/common.c34
-rw-r--r--drivers/renesas/rcar/emmc/emmc_config.h40
-rw-r--r--drivers/renesas/rcar/emmc/emmc_hal.h318
-rw-r--r--drivers/renesas/rcar/emmc/emmc_registers.h260
-rw-r--r--drivers/renesas/rcar/emmc/emmc_std.h474
-rw-r--r--drivers/renesas/rzg/board/board.c64
-rw-r--r--drivers/renesas/rzg/board/board.h30
-rw-r--r--drivers/renesas/rzg/ddr/boot_init_dram.h18
-rw-r--r--drivers/renesas/rzg/ddr/ddr.mk7
-rw-r--r--drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c3700
-rw-r--r--drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_config.c277
-rw-r--r--drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_regdef.h99
-rw-r--r--drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk7
-rw-r--r--drivers/renesas/rzg/ddr/ddr_b/ddr_regdef.h5891
-rw-r--r--drivers/renesas/rzg/ddr/ddr_b/init_dram_tbl_g2m.h472
-rw-r--r--drivers/renesas/rzg/ddr/dram_sub_func.h14
-rw-r--r--drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c1300
-rw-r--r--drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.h12
-rw-r--r--drivers/renesas/rzg/pfc/pfc.mk20
-rw-r--r--drivers/renesas/rzg/pfc/pfc_init.c72
-rw-r--r--drivers/renesas/rzg/qos/G2M/qos_init_g2m_v10.c148
-rw-r--r--drivers/renesas/rzg/qos/G2M/qos_init_g2m_v10.h12
-rw-r--r--drivers/renesas/rzg/qos/G2M/qos_init_g2m_v10_mstat.h232
-rw-r--r--drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11.c218
-rw-r--r--drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11.h12
-rw-r--r--drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11_mstat195.h230
-rw-r--r--drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11_mstat390.h230
-rw-r--r--drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11_qoswt195.h230
-rw-r--r--drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11_qoswt390.h230
-rw-r--r--drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30.c210
-rw-r--r--drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30.h12
-rw-r--r--drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30_mstat195.h230
-rw-r--r--drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30_mstat390.h230
-rw-r--r--drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30_qoswt195.h230
-rw-r--r--drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30_qoswt390.h230
-rw-r--r--drivers/renesas/rzg/qos/qos.mk34
-rw-r--r--drivers/renesas/rzg/qos/qos_common.h67
-rw-r--r--drivers/renesas/rzg/qos/qos_init.c175
-rw-r--r--drivers/renesas/rzg/qos/qos_init.h13
-rw-r--r--drivers/scmi-msg/base.c (renamed from drivers/st/scmi-msg/base.c)4
-rw-r--r--drivers/scmi-msg/base.h (renamed from drivers/st/scmi-msg/base.h)0
-rw-r--r--drivers/scmi-msg/clock.c (renamed from drivers/st/scmi-msg/clock.c)4
-rw-r--r--drivers/scmi-msg/clock.h (renamed from drivers/st/scmi-msg/clock.h)0
-rw-r--r--drivers/scmi-msg/common.h (renamed from drivers/st/scmi-msg/common.h)0
-rw-r--r--drivers/scmi-msg/entry.c (renamed from drivers/st/scmi-msg/entry.c)4
-rw-r--r--drivers/scmi-msg/reset_domain.c (renamed from drivers/st/scmi-msg/reset_domain.c)4
-rw-r--r--drivers/scmi-msg/reset_domain.h (renamed from drivers/st/scmi-msg/reset_domain.h)0
-rw-r--r--drivers/scmi-msg/smt.c (renamed from drivers/st/scmi-msg/smt.c)4
-rw-r--r--drivers/st/fmc/stm32_fmc2_nand.c11
-rw-r--r--fdts/morello-fvp.dts10
-rw-r--r--fdts/n1sdp-single-chip.dts2
-rw-r--r--fdts/stm32mp157c-lxa-mc1.dts107
-rw-r--r--fdts/stm32mp15xx-osd32.dtsi281
-rw-r--r--fdts/tc0.dts74
-rw-r--r--include/arch/aarch32/arch.h11
-rw-r--r--include/arch/aarch32/el3_common_macros.S4
-rw-r--r--include/arch/aarch64/arch.h84
-rw-r--r--include/arch/aarch64/arch_features.h6
-rw-r--r--include/arch/aarch64/arch_helpers.h5
-rw-r--r--include/arch/aarch64/el3_common_macros.S4
-rw-r--r--include/drivers/allwinner/axp.h4
-rw-r--r--include/drivers/arm/tzc400.h9
-rw-r--r--include/drivers/cadence/cdns_uart.h1
-rw-r--r--include/drivers/marvell/uart/a3700_console.h3
-rw-r--r--include/drivers/scmi-msg.h (renamed from include/drivers/st/scmi-msg.h)0
-rw-r--r--include/drivers/scmi.h (renamed from include/drivers/st/scmi.h)0
-rw-r--r--include/drivers/st/stm32mp1_ddr_regs.h4
-rw-r--r--include/lib/cpus/aarch64/cortex_a78.h19
-rw-r--r--include/lib/cpus/aarch64/neoverse_n1.h8
-rw-r--r--include/lib/cpus/aarch64/neoverse_n2.h31
-rw-r--r--include/lib/cpus/aarch64/neoverse_n_common.h18
-rw-r--r--include/lib/cpus/errata_report.h3
-rw-r--r--include/lib/el3_runtime/aarch64/context.h5
-rw-r--r--include/lib/libc/stdlib.h9
-rw-r--r--include/plat/arm/common/fconf_arm_sp_getter.h2
-rw-r--r--include/plat/common/plat_trng.h18
-rw-r--r--include/plat/common/platform.h5
-rw-r--r--include/services/trng_svc.h57
-rw-r--r--lib/aarch64/misc_helpers.S48
-rw-r--r--lib/cpus/aarch32/cpu_helpers.S16
-rw-r--r--lib/cpus/aarch64/cortex_a76.S61
-rw-r--r--lib/cpus/aarch64/cortex_a78.S98
-rw-r--r--lib/cpus/aarch64/neoverse_n1.S82
-rw-r--r--lib/cpus/aarch64/neoverse_n2.S109
-rw-r--r--lib/cpus/aarch64/neoverse_n_common.S26
-rw-r--r--lib/cpus/aarch64/rainier.S90
-rw-r--r--lib/cpus/cpu-ops.mk44
-rw-r--r--lib/debugfs/dev.c6
-rw-r--r--lib/debugfs/devfip.c11
-rw-r--r--lib/el3_runtime/aarch64/context.S7
-rw-r--r--lib/el3_runtime/aarch64/context_mgmt.c31
-rw-r--r--lib/extensions/mtpmu/aarch32/mtpmu.S105
-rw-r--r--lib/extensions/mtpmu/aarch64/mtpmu.S96
-rw-r--r--lib/libc/libc.mk10
-rw-r--r--lib/libc/libc_asm.mk10
-rw-r--r--lib/libc/printf.c5
-rw-r--r--lib/libc/snprintf.c35
-rw-r--r--lib/libc/strtol.c133
-rw-r--r--lib/libc/strtoll.c134
-rw-r--r--lib/libc/strtoul.c112
-rw-r--r--lib/libc/strtoull.c112
-rw-r--r--lib/psci/psci_private.h9
-rw-r--r--lib/psci/psci_setup.c14
-rw-r--r--make_helpers/build_macros.mk15
-rw-r--r--make_helpers/defaults.mk12
-rw-r--r--plat/allwinner/common/allwinner-common.mk38
-rw-r--r--plat/allwinner/common/include/platform_def.h3
-rw-r--r--plat/allwinner/common/include/sunxi_private.h25
-rw-r--r--plat/allwinner/common/sunxi_bl31_setup.c7
-rw-r--r--plat/allwinner/common/sunxi_common.c19
-rw-r--r--plat/allwinner/common/sunxi_cpu_ops.c37
-rw-r--r--plat/allwinner/common/sunxi_native_pm.c81
-rw-r--r--plat/allwinner/common/sunxi_pm.c278
-rw-r--r--plat/allwinner/common/sunxi_scpi_pm.c223
-rw-r--r--plat/allwinner/common/sunxi_security.c19
-rw-r--r--plat/allwinner/sun50i_a64/include/sunxi_ccu.h14
-rw-r--r--plat/allwinner/sun50i_a64/include/sunxi_mmap.h1
-rw-r--r--plat/allwinner/sun50i_a64/include/sunxi_spc.h16
-rw-r--r--plat/allwinner/sun50i_a64/sunxi_power.c21
-rw-r--r--plat/allwinner/sun50i_h6/include/sunxi_ccu.h14
-rw-r--r--plat/allwinner/sun50i_h6/include/sunxi_mmap.h3
-rw-r--r--plat/allwinner/sun50i_h6/include/sunxi_spc.h16
-rw-r--r--plat/allwinner/sun50i_h6/platform.mk2
-rw-r--r--plat/allwinner/sun50i_h6/sunxi_power.c74
-rw-r--r--plat/amlogic/axg/include/platform_def.h4
-rw-r--r--plat/arm/board/arm_fpga/platform.mk2
-rw-r--r--plat/arm/board/common/board_common.mk1
-rw-r--r--plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts12
-rw-r--r--plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts12
-rw-r--r--plat/arm/board/fvp/fdts/optee_sp_manifest.dts (renamed from fdts/optee_sp_manifest.dts)16
-rw-r--r--plat/arm/board/fvp/fvp_common.c23
-rw-r--r--plat/arm/board/fvp/fvp_def.h11
-rw-r--r--plat/arm/board/fvp/fvp_gicv3.c40
-rw-r--r--plat/arm/board/fvp/platform.mk11
-rw-r--r--plat/arm/board/juno/juno_decl.h2
-rw-r--r--plat/arm/board/juno/juno_stack_protector.c18
-rw-r--r--plat/arm/board/juno/juno_trng.c82
-rw-r--r--plat/arm/board/juno/platform.mk4
-rw-r--r--plat/arm/board/morello/morello_bl31_setup.c26
-rw-r--r--plat/arm/board/morello/morello_def.h6
-rw-r--r--plat/arm/board/morello/platform.mk2
-rw-r--r--plat/arm/board/n1sdp/platform.mk2
-rw-r--r--plat/arm/board/rde1edge/include/platform_def.h2
-rw-r--r--plat/arm/board/rde1edge/platform.mk2
-rw-r--r--plat/arm/board/rdn1edge/include/platform_def.h2
-rw-r--r--plat/arm/board/rdn1edge/platform.mk2
-rw-r--r--plat/arm/board/rdn1edge/rdn1edge_plat.c2
-rw-r--r--plat/arm/board/rdn2/fdts/rdn2_fw_config.dts (renamed from plat/arm/board/rddaniel/fdts/rddaniel_fw_config.dts)0
-rw-r--r--plat/arm/board/rdn2/fdts/rdn2_nt_fw_config.dts (renamed from plat/arm/board/rddaniel/fdts/rddaniel_nt_fw_config.dts)2
-rw-r--r--plat/arm/board/rdn2/fdts/rdn2_tb_fw_config.dts (renamed from plat/arm/board/rddaniel/fdts/rddaniel_tb_fw_config.dts)0
-rw-r--r--plat/arm/board/rdn2/include/platform_def.h65
-rw-r--r--plat/arm/board/rdn2/platform.mk60
-rw-r--r--plat/arm/board/rdn2/rdn2_err.c (renamed from plat/arm/board/rddaniel/rddaniel_err.c)2
-rw-r--r--plat/arm/board/rdn2/rdn2_plat.c31
-rw-r--r--plat/arm/board/rdn2/rdn2_security.c25
-rw-r--r--plat/arm/board/rdn2/rdn2_topology.c62
-rw-r--r--plat/arm/board/rdn2/rdn2_trusted_boot.c (renamed from plat/arm/board/rddaniel/rddaniel_trusted_boot.c)0
-rw-r--r--plat/arm/board/rdv1/fdts/rdv1_fw_config.dts (renamed from plat/arm/board/rddanielxlr/fdts/rddanielxlr_fw_config.dts)0
-rw-r--r--plat/arm/board/rdv1/fdts/rdv1_nt_fw_config.dts (renamed from plat/arm/board/rddanielxlr/fdts/rddanielxlr_nt_fw_config.dts)2
-rw-r--r--plat/arm/board/rdv1/fdts/rdv1_tb_fw_config.dts (renamed from plat/arm/board/rddanielxlr/fdts/rddanielxlr_tb_fw_config.dts)0
-rw-r--r--plat/arm/board/rdv1/include/platform_def.h (renamed from plat/arm/board/rddaniel/include/platform_def.h)2
-rw-r--r--plat/arm/board/rdv1/platform.mk (renamed from plat/arm/board/rddaniel/platform.mk)33
-rw-r--r--plat/arm/board/rdv1/rdv1_err.c17
-rw-r--r--plat/arm/board/rdv1/rdv1_plat.c (renamed from plat/arm/board/rddaniel/rddaniel_plat.c)0
-rw-r--r--plat/arm/board/rdv1/rdv1_security.c (renamed from plat/arm/board/rddaniel/rddaniel_security.c)0
-rw-r--r--plat/arm/board/rdv1/rdv1_topology.c (renamed from plat/arm/board/rddaniel/rddaniel_topology.c)4
-rw-r--r--plat/arm/board/rdv1/rdv1_trusted_boot.c (renamed from plat/arm/board/rddanielxlr/rddanielxlr_trusted_boot.c)0
-rw-r--r--plat/arm/board/rdv1mc/fdts/rdv1mc_fw_config.dts27
-rw-r--r--plat/arm/board/rdv1mc/fdts/rdv1mc_nt_fw_config.dts22
-rw-r--r--plat/arm/board/rdv1mc/fdts/rdv1mc_tb_fw_config.dts28
-rw-r--r--plat/arm/board/rdv1mc/include/platform_def.h (renamed from plat/arm/board/rddanielxlr/include/platform_def.h)2
-rw-r--r--plat/arm/board/rdv1mc/platform.mk (renamed from plat/arm/board/rddanielxlr/platform.mk)30
-rw-r--r--plat/arm/board/rdv1mc/rdv1mc_err.c (renamed from plat/arm/board/rddanielxlr/rddanielxlr_err.c)2
-rw-r--r--plat/arm/board/rdv1mc/rdv1mc_plat.c (renamed from plat/arm/board/rddanielxlr/rddanielxlr_plat.c)24
-rw-r--r--plat/arm/board/rdv1mc/rdv1mc_security.c (renamed from plat/arm/board/rddanielxlr/rddanielxlr_security.c)0
-rw-r--r--plat/arm/board/rdv1mc/rdv1mc_topology.c (renamed from plat/arm/board/rddanielxlr/rddanielxlr_topology.c)4
-rw-r--r--plat/arm/board/rdv1mc/rdv1mc_trusted_boot.c26
-rw-r--r--plat/arm/board/sgi575/include/platform_def.h2
-rw-r--r--plat/arm/board/sgi575/platform.mk2
-rw-r--r--plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts41
-rw-r--r--plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts104
-rw-r--r--plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts7
-rw-r--r--plat/arm/board/tc0/include/platform_def.h6
-rw-r--r--plat/arm/board/tc0/platform.mk11
-rw-r--r--plat/arm/board/tc0/tc0_plat.c4
-rw-r--r--plat/arm/board/tc0/tc0_topology.c3
-rw-r--r--plat/arm/css/common/css_pm.c3
-rw-r--r--plat/arm/css/sgi/include/sgi_base_platform_def.h3
-rw-r--r--plat/arm/css/sgi/include/sgi_soc_css_def_v2.h194
-rw-r--r--plat/arm/css/sgi/include/sgi_soc_platform_def.h15
-rw-r--r--plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h13
-rw-r--r--plat/arm/css/sgi/include/sgi_variant.h7
-rw-r--r--plat/arm/css/sgi/sgi-common.mk3
-rw-r--r--plat/arm/css/sgi/sgi_bl31_setup.c16
-rw-r--r--plat/arm/css/sgi/sgi_plat_v2.c85
-rw-r--r--plat/arm/css/sgi/sgi_ras.c18
-rw-r--r--plat/marvell/armada/a3k/common/a3700_common.mk175
-rw-r--r--plat/marvell/armada/a3k/common/cm3_system_reset.c62
-rw-r--r--plat/marvell/armada/a3k/common/dram_win.c56
-rw-r--r--plat/marvell/armada/a3k/common/include/a3700_plat_def.h18
-rw-r--r--plat/marvell/armada/a3k/common/include/a3700_pm.h4
-rw-r--r--plat/marvell/armada/a3k/common/include/platform_def.h6
-rw-r--r--plat/marvell/armada/a3k/common/plat_cci.c35
-rw-r--r--plat/marvell/armada/a3k/common/plat_pm.c10
-rw-r--r--plat/marvell/armada/a8k/common/a8k_common.mk15
-rw-r--r--plat/marvell/armada/a8k/common/ble/ble.mk2
-rw-r--r--plat/marvell/armada/common/marvell_common.mk7
-rw-r--r--plat/marvell/version.mk2
-rw-r--r--plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c125
-rw-r--r--plat/mediatek/common/drivers/uart/uart.c (renamed from plat/mediatek/mt8183/drivers/uart/uart.c)11
-rw-r--r--plat/mediatek/mt8183/bl31_plat_setup.c3
-rw-r--r--plat/mediatek/mt8183/drivers/timer/mt_timer.c29
-rw-r--r--plat/mediatek/mt8183/drivers/timer/mt_timer.h20
-rw-r--r--plat/mediatek/mt8183/drivers/uart/uart.h2
-rw-r--r--plat/mediatek/mt8183/platform.mk4
-rw-r--r--plat/mediatek/mt8192/bl31_plat_setup.c15
-rw-r--r--plat/mediatek/mt8192/drivers/dcm/mtk_dcm.c63
-rw-r--r--plat/mediatek/mt8192/drivers/dcm/mtk_dcm.h14
-rw-r--r--plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.c562
-rw-r--r--plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.h68
-rw-r--r--plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c122
-rw-r--r--plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.h102
-rw-r--r--plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm.c123
-rw-r--r--plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm_cpc.c269
-rw-r--r--plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm_cpc.h106
-rw-r--r--plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.c148
-rw-r--r--plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.h12
-rw-r--r--plat/mediatek/mt8192/drivers/pmic/pmic.c13
-rw-r--r--plat/mediatek/mt8192/drivers/pmic/pmic.h15
-rw-r--r--plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h76
-rw-r--r--plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_common.h48
-rw-r--r--plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_main.c84
-rw-r--r--plat/mediatek/mt8192/drivers/rtc/rtc.c148
-rw-r--r--plat/mediatek/mt8192/drivers/rtc/rtc.h197
-rw-r--r--plat/mediatek/mt8192/drivers/spmc/mtspmc.c177
-rw-r--r--plat/mediatek/mt8192/drivers/spmc/mtspmc.h31
-rw-r--r--plat/mediatek/mt8192/drivers/spmc/mtspmc_private.h184
-rw-r--r--plat/mediatek/mt8192/drivers/timer/mt_timer.c8
-rw-r--r--plat/mediatek/mt8192/drivers/timer/mt_timer.h5
-rw-r--r--plat/mediatek/mt8192/drivers/uart/uart.h100
-rw-r--r--plat/mediatek/mt8192/include/mcucfg.h257
-rw-r--r--plat/mediatek/mt8192/include/plat_mt_cirq.h124
-rw-r--r--plat/mediatek/mt8192/include/plat_mtk_lpm.h48
-rw-r--r--plat/mediatek/mt8192/include/plat_pm.h38
-rw-r--r--plat/mediatek/mt8192/include/plat_sip_calls.h15
-rw-r--r--plat/mediatek/mt8192/include/platform_def.h12
-rw-r--r--plat/mediatek/mt8192/plat_mt_cirq.c718
-rw-r--r--plat/mediatek/mt8192/plat_pm.c373
-rw-r--r--plat/mediatek/mt8192/plat_sip_calls.c27
-rw-r--r--plat/mediatek/mt8192/plat_topology.c2
-rw-r--r--plat/mediatek/mt8192/platform.mk28
-rw-r--r--plat/nxp/common/plat_make_helper/plat_build_macros.mk11
-rw-r--r--plat/qemu/common/aarch64/plat_helpers.S3
-rw-r--r--plat/qemu/common/qemu_common.c9
-rw-r--r--plat/qemu/common/qemu_spm.c65
-rw-r--r--plat/qemu/common/qemu_stack_protector.c16
-rw-r--r--plat/qemu/qemu/include/platform_def.h8
-rw-r--r--plat/qemu/qemu_sbsa/include/platform_def.h49
-rw-r--r--plat/qemu/qemu_sbsa/platform.mk6
-rw-r--r--plat/qemu/qemu_sbsa/sbsa_pm.c237
-rw-r--r--plat/qemu/qemu_sbsa/sbsa_private.h17
-rw-r--r--plat/qemu/qemu_sbsa/sbsa_topology.c63
-rw-r--r--plat/qti/common/src/spmi_arb.c4
-rw-r--r--plat/renesas/common/aarch64/plat_helpers.S (renamed from plat/renesas/rcar/aarch64/plat_helpers.S)0
-rw-r--r--plat/renesas/common/aarch64/platform_common.c (renamed from plat/renesas/rcar/aarch64/platform_common.c)0
-rw-r--r--plat/renesas/common/bl2_cpg_init.c (renamed from plat/renesas/rcar/bl2_cpg_init.c)22
-rw-r--r--plat/renesas/common/bl2_interrupt_error.c (renamed from plat/renesas/rcar/bl2_interrupt_error.c)0
-rw-r--r--plat/renesas/common/bl2_plat_mem_params_desc.c (renamed from plat/renesas/rcar/bl2_plat_mem_params_desc.c)0
-rw-r--r--plat/renesas/common/bl2_secure_setting.c362
-rw-r--r--plat/renesas/common/bl31_plat_setup.c (renamed from plat/renesas/rcar/bl31_plat_setup.c)27
-rw-r--r--plat/renesas/common/common.mk132
-rw-r--r--plat/renesas/common/include/plat.ld.S (renamed from plat/renesas/rcar/include/plat.ld.S)0
-rw-r--r--plat/renesas/common/include/plat_macros.S (renamed from plat/renesas/rcar/include/plat_macros.S)0
-rw-r--r--plat/renesas/common/include/platform_def.h (renamed from plat/renesas/rcar/include/platform_def.h)42
-rw-r--r--plat/renesas/common/include/rcar_def.h (renamed from plat/renesas/rcar/include/rcar_def.h)208
-rw-r--r--plat/renesas/common/include/rcar_private.h (renamed from plat/renesas/rcar/include/rcar_private.h)19
-rw-r--r--plat/renesas/common/include/rcar_version.h (renamed from plat/renesas/rcar/include/rcar_version.h)0
-rw-r--r--plat/renesas/common/include/registers/axi_registers.h (renamed from plat/renesas/rcar/include/registers/axi_registers.h)0
-rw-r--r--plat/renesas/common/include/registers/cpg_registers.h (renamed from plat/renesas/rcar/include/registers/cpg_registers.h)0
-rw-r--r--plat/renesas/common/include/registers/lifec_registers.h144
-rw-r--r--plat/renesas/common/plat_image_load.c (renamed from plat/renesas/rcar/plat_image_load.c)0
-rw-r--r--plat/renesas/common/plat_pm.c (renamed from plat/renesas/rcar/plat_pm.c)25
-rw-r--r--plat/renesas/common/plat_storage.c (renamed from plat/renesas/rcar/plat_storage.c)24
-rw-r--r--plat/renesas/common/plat_topology.c (renamed from plat/renesas/rcar/plat_topology.c)0
-rw-r--r--plat/renesas/common/rcar_common.c (renamed from plat/renesas/rcar/rcar_common.c)0
-rw-r--r--plat/renesas/rcar/bl2_secure_setting.c352
-rw-r--r--plat/renesas/rcar/include/registers/lifec_registers.h144
-rw-r--r--plat/renesas/rcar/platform.mk149
-rw-r--r--plat/renesas/rzg/bl2_plat_setup.c909
-rw-r--r--plat/renesas/rzg/platform.mk222
-rw-r--r--plat/rockchip/common/rockchip_stack_protector.c24
-rw-r--r--plat/rockchip/px30/platform.mk4
-rw-r--r--plat/rockchip/rk3328/platform.mk4
-rw-r--r--plat/rockchip/rk3368/platform.mk4
-rw-r--r--plat/rockchip/rk3399/platform.mk4
-rw-r--r--plat/st/stm32mp1/services/stm32mp1_svc_setup.c2
-rw-r--r--plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk10
-rw-r--r--plat/st/stm32mp1/stm32mp1_helper.S2
-rw-r--r--plat/st/stm32mp1/stm32mp1_scmi.c4
-rw-r--r--plat/ti/k3/board/generic/board.mk7
-rw-r--r--plat/ti/k3/board/lite/board.mk24
-rw-r--r--plat/ti/k3/board/lite/include/board_def.h34
-rw-r--r--plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c14
-rw-r--r--plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h15
-rw-r--r--plat/ti/k3/common/drivers/ti_sci/ti_sci.c1
-rw-r--r--plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h3
-rw-r--r--plat/ti/k3/common/k3_bl31_setup.c34
-rw-r--r--plat/ti/k3/common/plat_common.mk5
-rw-r--r--plat/ti/k3/include/platform_def.h18
-rw-r--r--plat/xilinx/common/pm_service/pm_ipi.c4
-rw-r--r--plat/xilinx/versal/bl31_versal_setup.c8
-rw-r--r--plat/xilinx/versal/plat_psci.c12
-rw-r--r--plat/xilinx/versal/plat_versal.c6
-rw-r--r--plat/xilinx/versal/pm_service/pm_api_sys.c112
-rw-r--r--plat/xilinx/versal/pm_service/pm_api_sys.h7
-rw-r--r--plat/xilinx/versal/pm_service/pm_client.c9
-rw-r--r--plat/xilinx/versal/pm_service/pm_defs.h27
-rw-r--r--plat/xilinx/versal/pm_service/pm_svc_main.c33
-rw-r--r--plat/xilinx/zynqmp/bl31_zynqmp_setup.c29
-rw-r--r--plat/xilinx/zynqmp/include/zynqmp_def.h16
-rw-r--r--plat/xilinx/zynqmp/plat_zynqmp.c6
-rw-r--r--plat/xilinx/zynqmp/platform.mk9
-rw-r--r--plat/xilinx/zynqmp/pm_service/pm_api_clock.c45
-rw-r--r--plat/xilinx/zynqmp/pm_service/pm_api_clock.h4
-rw-r--r--plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c46
-rw-r--r--plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c367
-rw-r--r--plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h15
-rw-r--r--plat/xilinx/zynqmp/pm_service/pm_api_sys.c232
-rw-r--r--plat/xilinx/zynqmp/pm_service/pm_api_sys.h22
-rw-r--r--plat/xilinx/zynqmp/pm_service/pm_defs.h50
-rw-r--r--plat/xilinx/zynqmp/pm_service/pm_svc_main.c119
-rw-r--r--plat/xilinx/zynqmp/pm_service/pm_svc_main.h5
-rw-r--r--plat/xilinx/zynqmp/sip_svc_setup.c15
-rw-r--r--services/std_svc/spm_mm/spm_mm_setup.c4
-rw-r--r--services/std_svc/std_svc_setup.c12
-rw-r--r--services/std_svc/trng/trng_entropy_pool.c151
-rw-r--r--services/std_svc/trng/trng_entropy_pool.h16
-rw-r--r--services/std_svc/trng/trng_main.c143
-rw-r--r--tools/cert_create/Makefile2
-rw-r--r--tools/cert_create/src/ext.c37
-rw-r--r--tools/cert_create/src/main.c57
-rw-r--r--tools/encrypt_fw/Makefile2
-rw-r--r--tools/renesas/rzg_layout_create/makefile118
-rw-r--r--tools/renesas/rzg_layout_create/sa0.c30
-rw-r--r--tools/renesas/rzg_layout_create/sa0.ld.S28
-rw-r--r--tools/renesas/rzg_layout_create/sa6.c236
-rw-r--r--tools/renesas/rzg_layout_create/sa6.ld.S114
420 files changed, 29904 insertions, 4604 deletions
diff --git a/.editorconfig b/.editorconfig
index f523ca19da..12f786de5a 100644
--- a/.editorconfig
+++ b/.editorconfig
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -38,10 +38,10 @@ indent_style = tab
insert_final_newline = true
# [LCS] Chapter 2: Breaking long lines and strings
-# "The limit on the length of lines is 80 columns"
+# "The limit on the length of lines is 100 columns"
# This is a "soft" requirement for Arm-TF, and should not be the sole
# reason for changes.
-max_line_length = 80
+max_line_length = 100
# [LCS] Chapter 1: Indentation
# "Tabs are 8 characters"
diff --git a/.gitignore b/.gitignore
index 64b389b12a..79c510405a 100644
--- a/.gitignore
+++ b/.gitignore
@@ -15,6 +15,10 @@ tools/renesas/rcar_layout_create/*.bin
tools/renesas/rcar_layout_create/*.srec
tools/renesas/rcar_layout_create/*.map
tools/renesas/rcar_layout_create/*.elf
+tools/renesas/rzg_layout_create/*.bin
+tools/renesas/rzg_layout_create/*.srec
+tools/renesas/rzg_layout_create/*.map
+tools/renesas/rzg_layout_create/*.elf
tools/fiptool/fiptool
tools/fiptool/fiptool.exe
tools/cert_create/src/*.o
diff --git a/Makefile b/Makefile
index 5c9186ece3..f899dacd26 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -185,13 +185,14 @@ target32-directive = -target arm-none-eabi
else
target32-directive = -target armv8a-none-eabi
-# Set the compiler's target architecture profile based on ARM_ARCH_MINOR option
+# Set the compiler's target architecture profile based on
+# ARM_ARCH_MAJOR ARM_ARCH_MINOR options
ifeq (${ARM_ARCH_MINOR},0)
-march32-directive = -march=armv8-a
-march64-directive = -march=armv8-a
+march32-directive = -march=armv${ARM_ARCH_MAJOR}-a
+march64-directive = -march=armv${ARM_ARCH_MAJOR}-a
else
-march32-directive = -march=armv8.${ARM_ARCH_MINOR}-a
-march64-directive = -march=armv8.${ARM_ARCH_MINOR}-a
+march32-directive = -march=armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a
+march64-directive = -march=armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a
endif
endif
@@ -203,23 +204,46 @@ mem_tag_arch_support = yes
endif
endif
-# Enabled required option for memory stack tagging. Currently, these options are
-# enabled only for clang and armclang compiler.
+# Get architecture feature modifiers
+arch-features = ${ARM_ARCH_FEATURE}
+
+# Enable required options for memory stack tagging.
+# Currently, these options are enabled only for clang and armclang compiler.
ifeq (${SUPPORT_STACK_MEMTAG},yes)
ifdef mem_tag_arch_support
+# Check for armclang and clang compilers
ifneq ( ,$(filter $(notdir $(CC)),armclang clang))
-march64-directive = -march=armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a+memtag
+# Add "memtag" architecture feature modifier if not specified
+ifeq ( ,$(findstring memtag,$(arch-features)))
+arch-features := $(arch-features)+memtag
+endif # memtag
ifeq ($(notdir $(CC)),armclang)
TF_CFLAGS += -mmemtag-stack
else ifeq ($(notdir $(CC)),clang)
TF_CFLAGS += -fsanitize=memtag
-endif
-endif
+endif # armclang
+endif # armclang clang
else
$(error "Error: stack memory tagging is not supported for architecture \
${ARCH},armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a")
+endif # mem_tag_arch_support
+endif # SUPPORT_STACK_MEMTAG
+
+# Set the compiler's architecture feature modifiers
+ifneq ($(arch-features), none)
+# Strip "none+" from arch-features
+arch-features := $(subst none+,,$(arch-features))
+ifeq ($(ARCH), aarch32)
+march32-directive := $(march32-directive)+$(arch-features)
+else
+march64-directive := $(march64-directive)+$(arch-features)
endif
-endif
+# Print features
+$(info Arm Architecture Features specified: $(subst +, ,$(arch-features)))
+endif # arch-features
+
+# Determine if FEAT_RNG is supported
+ENABLE_FEAT_RNG = $(if $(findstring rng,${arch-features}),1,0)
ifneq ($(findstring armclang,$(notdir $(CC))),)
TF_CFLAGS_aarch32 = -target arm-arm-none-eabi $(march32-directive)
@@ -867,6 +891,7 @@ $(eval $(call assert_booleans,\
CTX_INCLUDE_EL2_REGS \
CTX_INCLUDE_NEVE_REGS \
DEBUG \
+ DISABLE_MTPMU \
DYN_DISABLE_AUTH \
EL3_EXCEPTION_HANDLING \
ENABLE_AMU \
@@ -918,6 +943,7 @@ $(eval $(call assert_booleans,\
RAS_TRAP_LOWER_EL_ERR_ACCESS \
COT_DESC_IN_DTB \
USE_SP804_TIMER \
+ ENABLE_FEAT_RNG \
)))
$(eval $(call assert_numerics,\
@@ -956,6 +982,7 @@ $(eval $(call add_defines,\
CTX_INCLUDE_EL2_REGS \
CTX_INCLUDE_NEVE_REGS \
DECRYPTION_SUPPORT_${DECRYPTION_SUPPORT} \
+ DISABLE_MTPMU \
ENABLE_AMU \
ENABLE_ASSERTIONS \
ENABLE_BTI \
@@ -991,6 +1018,7 @@ $(eval $(call add_defines,\
SPM_MM \
SPMD_SPM_AT_SEL2 \
TRUSTED_BOARD_BOOT \
+ TRNG_SUPPORT \
USE_COHERENT_MEM \
USE_DEBUGFS \
ARM_IO_IN_DTB \
@@ -1007,6 +1035,7 @@ $(eval $(call add_defines,\
RAS_TRAP_LOWER_EL_ERR_ACCESS \
COT_DESC_IN_DTB \
USE_SP804_TIMER \
+ ENABLE_FEAT_RNG \
)))
ifeq (${SANITIZE_UB},trap)
@@ -1222,8 +1251,7 @@ checkpatch: locate-checkpatch
certtool: ${CRTTOOL}
-.PHONY: ${CRTTOOL}
-${CRTTOOL}:
+${CRTTOOL}: FORCE
${Q}${MAKE} PLAT=${PLAT} USE_TBBR_DEFS=${USE_TBBR_DEFS} COT=${COT} OPENSSL_DIR=${OPENSSL_DIR} CRTTOOL=${CRTTOOL} --no-print-directory -C ${CRTTOOLPATH}
@${ECHO_BLANK_LINE}
@echo "Built $@ successfully"
@@ -1239,6 +1267,7 @@ certificates: ${CRT_DEPS} ${CRTTOOL}
endif
${BUILD_PLAT}/${FIP_NAME}: ${FIP_DEPS} ${FIPTOOL}
+ $(eval ${CHECK_FIP_CMD})
${Q}${FIPTOOL} create ${FIP_ARGS} $@
${Q}${FIPTOOL} info $@
@${ECHO_BLANK_LINE}
@@ -1255,6 +1284,7 @@ fwu_certificates: ${FWU_CRT_DEPS} ${CRTTOOL}
endif
${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP_DEPS} ${FIPTOOL}
+ $(eval ${CHECK_FWU_FIP_CMD})
${Q}${FIPTOOL} create ${FWU_FIP_ARGS} $@
${Q}${FIPTOOL} info $@
@${ECHO_BLANK_LINE}
@@ -1265,8 +1295,7 @@ fiptool: ${FIPTOOL}
fip: ${BUILD_PLAT}/${FIP_NAME}
fwu_fip: ${BUILD_PLAT}/${FWU_FIP_NAME}
-.PHONY: ${FIPTOOL}
-${FIPTOOL}:
+${FIPTOOL}: FORCE
@${ECHO_BLANK_LINE}
@echo "Building $@"
ifdef UNIX_MK
@@ -1279,12 +1308,10 @@ endif
@${ECHO_BLANK_LINE}
sptool: ${SPTOOL}
-.PHONY: ${SPTOOL}
-${SPTOOL}:
+${SPTOOL}: FORCE
${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" SPTOOL=${SPTOOL} --no-print-directory -C ${SPTOOLPATH}
-.PHONY: libraries
-romlib.bin: libraries
+romlib.bin: libraries FORCE
${Q}${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} ENABLE_BTI=${ENABLE_BTI} ARM_ARCH_MINOR=${ARM_ARCH_MINOR} INCLUDES='${INCLUDES}' DEFINES='${DEFINES}' --no-print-directory -C ${ROMLIBPATH} all
# Call print_memory_map tool
@@ -1297,8 +1324,7 @@ doc:
enctool: ${ENCTOOL}
-.PHONY: ${ENCTOOL}
-${ENCTOOL}:
+${ENCTOOL}: FORCE
${Q}${MAKE} PLAT=${PLAT} BUILD_INFO=0 OPENSSL_DIR=${OPENSSL_DIR} ENCTOOL=${ENCTOOL} --no-print-directory -C ${ENCTOOLPATH}
@${ECHO_BLANK_LINE}
@echo "Built $@ successfully"
@@ -1352,3 +1378,6 @@ help:
@echo ""
@echo "example: build all targets for the FVP platform:"
@echo " CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp all"
+
+.PHONY: FORCE
+FORCE:;
diff --git a/bl1/bl1.mk b/bl1/bl1.mk
index b839990751..d11b4ab0ed 100644
--- a/bl1/bl1.mk
+++ b/bl1/bl1.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -16,6 +16,10 @@ BL1_SOURCES += bl1/bl1_main.c \
plat/common/${ARCH}/platform_up_stack.S \
${MBEDTLS_SOURCES}
+ifeq (${DISABLE_MTPMU},1)
+BL1_SOURCES += lib/extensions/mtpmu/${ARCH}/mtpmu.S
+endif
+
ifeq (${ARCH},aarch64)
BL1_SOURCES += lib/cpus/aarch64/dsu_helpers.S \
lib/el3_runtime/aarch64/context.S
diff --git a/bl2/bl2.mk b/bl2/bl2.mk
index 6dc0f18253..735e7e04fb 100644
--- a/bl2/bl2.mk
+++ b/bl2/bl2.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -25,6 +25,10 @@ BL2_SOURCES += bl2/${ARCH}/bl2_el3_entrypoint.S \
lib/cpus/${ARCH}/cpu_helpers.S \
lib/cpus/errata_report.c
+ifeq (${DISABLE_MTPMU},1)
+BL2_SOURCES += lib/extensions/mtpmu/${ARCH}/mtpmu.S
+endif
+
ifeq (${ARCH},aarch64)
BL2_SOURCES += lib/cpus/aarch64/dsu_helpers.S
endif
diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S
index 1d28d5e0fb..f9c789f540 100644
--- a/bl31/aarch64/ea_delegate.S
+++ b/bl31/aarch64/ea_delegate.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,6 +15,7 @@
#include <context.h>
.globl handle_lower_el_ea_esb
+ .globl handle_lower_el_async_ea
.globl enter_lower_el_sync_ea
.globl enter_lower_el_async_ea
@@ -133,6 +134,7 @@ func enter_lower_el_async_ea
*/
str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
+handle_lower_el_async_ea:
/*
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
* If Secure Cycle Counter is not disabled in MDCR_EL3 when
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index bfe13f3120..51eb2bd475 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -45,8 +45,9 @@
* instruction. When an error is thus synchronized, the handling is
* delegated to platform EA handler.
*
- * Without RAS_EXTENSION, this macro just saves x30, and unmasks
- * Asynchronous External Aborts.
+ * Without RAS_EXTENSION, this macro synchronizes pending errors using
+ * a DSB, unmasks Asynchronous External Aborts and saves X30 before
+ * setting the flag CTX_IS_IN_EL3.
*/
.macro check_and_unmask_ea
#if RAS_EXTENSION
@@ -79,13 +80,89 @@
bl restore_gp_pmcr_pauth_regs
1:
#else
+ /*
+ * For SoCs which do not implement RAS, use DSB as a barrier to
+ * synchronize pending external aborts.
+ */
+ dsb sy
+
/* Unmask the SError interrupt */
msr daifclr, #DAIF_ABT_BIT
+ /* Use ISB for the above unmask operation to take effect immediately */
+ isb
+
+ /*
+ * Refer Note 1. No need to restore X30 as both handle_sync_exception
+ * and handle_interrupt_exception macro which follow this macro modify
+ * X30 anyway.
+ */
str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
+ mov x30, #1
+ str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
+ dmb sy
#endif
.endm
+#if !RAS_EXTENSION
+ /*
+ * Note 1: The explicit DSB at the entry of various exception vectors
+ * for handling exceptions from lower ELs can inadvertently trigger an
+ * SError exception in EL3 due to pending asynchronous aborts in lower
+ * ELs. This will end up being handled by serror_sp_elx which will
+ * ultimately panic and die.
+ * The way to workaround is to update a flag to indicate if the exception
+ * truly came from EL3. This flag is allocated in the cpu_context
+ * structure and located at offset "CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3"
+ * This is not a bullet proof solution to the problem at hand because
+ * we assume the instructions following "isb" that help to update the
+ * flag execute without causing further exceptions.
+ */
+
+ /* ---------------------------------------------------------------------
+ * This macro handles Asynchronous External Aborts.
+ * ---------------------------------------------------------------------
+ */
+ .macro handle_async_ea
+ /*
+ * Use a barrier to synchronize pending external aborts.
+ */
+ dsb sy
+
+ /* Unmask the SError interrupt */
+ msr daifclr, #DAIF_ABT_BIT
+
+ /* Use ISB for the above unmask operation to take effect immediately */
+ isb
+
+ /* Refer Note 1 */
+ str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
+ mov x30, #1
+ str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
+ dmb sy
+
+ b handle_lower_el_async_ea
+ .endm
+
+ /*
+ * This macro checks if the exception was taken due to SError in EL3 or
+ * because of pending asynchronous external aborts from lower EL that got
+ * triggered due to explicit synchronization in EL3. Refer Note 1.
+ */
+ .macro check_if_serror_from_EL3
+ /* Assumes SP_EL3 on entry */
+ str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
+ ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
+ cbnz x30, exp_from_EL3
+
+ /* Handle asynchronous external abort from lower EL */
+ b handle_lower_el_async_ea
+
+exp_from_EL3:
+ /* Jump to plat_handle_el3_ea which does not return */
+ .endm
+#endif
+
/* ---------------------------------------------------------------------
* This macro handles Synchronous exceptions.
* Only SMC exceptions are supported.
@@ -272,6 +349,9 @@ vector_entry fiq_sp_elx
end_vector_entry fiq_sp_elx
vector_entry serror_sp_elx
+#if !RAS_EXTENSION
+ check_if_serror_from_EL3
+#endif
no_ret plat_handle_el3_ea
end_vector_entry serror_sp_elx
@@ -305,8 +385,12 @@ end_vector_entry fiq_aarch64
vector_entry serror_aarch64
apply_at_speculative_wa
+#if RAS_EXTENSION
msr daifclr, #DAIF_ABT_BIT
b enter_lower_el_async_ea
+#else
+ handle_async_ea
+#endif
end_vector_entry serror_aarch64
/* ---------------------------------------------------------------------
@@ -339,8 +423,12 @@ end_vector_entry fiq_aarch32
vector_entry serror_aarch32
apply_at_speculative_wa
+#if RAS_EXTENSION
msr daifclr, #DAIF_ABT_BIT
b enter_lower_el_async_ea
+#else
+ handle_async_ea
+#endif
end_vector_entry serror_aarch32
#ifdef MONITOR_TRAPS
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index cd6549bff9..2088533acd 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -40,6 +40,9 @@ BL31_SOURCES += bl31/bl31_main.c \
${SPMD_SOURCES} \
${SPM_SOURCES}
+ifeq (${DISABLE_MTPMU},1)
+BL31_SOURCES += lib/extensions/mtpmu/aarch64/mtpmu.S
+endif
ifeq (${ENABLE_PMF}, 1)
BL31_SOURCES += lib/pmf/pmf_main.c
@@ -65,6 +68,11 @@ BL31_SOURCES += services/std_svc/sdei/sdei_dispatch.S \
services/std_svc/sdei/sdei_state.c
endif
+ifeq (${TRNG_SUPPORT},1)
+BL31_SOURCES += services/std_svc/trng/trng_main.c \
+ services/std_svc/trng/trng_entropy_pool.c
+endif
+
ifeq (${ENABLE_SPE_FOR_LOWER_ELS},1)
BL31_SOURCES += lib/extensions/spe/spe.c
endif
diff --git a/bl32/sp_min/sp_min.mk b/bl32/sp_min/sp_min.mk
index 6233299d7d..8b5eddd664 100644
--- a/bl32/sp_min/sp_min.mk
+++ b/bl32/sp_min/sp_min.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -19,6 +19,10 @@ BL32_SOURCES += bl32/sp_min/sp_min_main.c \
services/std_svc/std_svc_setup.c \
${PSCI_LIB_SOURCES}
+ifeq (${DISABLE_MTPMU},1)
+BL32_SOURCES += lib/extensions/mtpmu/aarch32/mtpmu.S
+endif
+
ifeq (${ENABLE_PMF}, 1)
BL32_SOURCES += lib/pmf/pmf_main.c
endif
@@ -33,6 +37,11 @@ BL32_SOURCES += bl32/sp_min/wa_cve_2017_5715_bpiall.S \
bl32/sp_min/wa_cve_2017_5715_icache_inv.S
endif
+ifeq (${TRNG_SUPPORT},1)
+BL32_SOURCES += services/std_svc/trng/trng_main.c \
+ services/std_svc/trng/trng_entropy_pool.c
+endif
+
BL32_LINKERFILE := bl32/sp_min/sp_min.ld.S
# Include the platform-specific SP_MIN Makefile
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index ab2d3f9f8a..14a3b45e39 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -295,6 +295,15 @@ Measured Boot
:F: include/drivers/measured_boot
:F: plat/arm/board/fvp/fvp_measured_boot.c
+System Control and Management Interface (SCMI) Server
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:M: Etienne Carriere <etienne.carriere@st.com>
+:G: `etienne-lms`_
+:M: Peng Fan <peng.fan@nxp.com>
+:G: `MrVan`_
+:F: drivers/scmi-msg
+:F: include/drivers/scmi\*
+
Platform Ports
~~~~~~~~~~~~~~
@@ -482,10 +491,27 @@ Renesas rcar-gen3 platform port
:M: Marek Vasut <marek.vasut@gmail.com>
:G: `marex`_
:F: docs/plat/rcar-gen3.rst
+:F: plat/renesas/common
:F: plat/renesas/rcar
+:F: drivers/renesas/common
:F: drivers/renesas/rcar
:F: tools/renesas/rcar_layout_create
+Renesas RZ/G2 platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:M: Biju Das <biju.das.jz@bp.renesas.com>
+:G: `bijucdas`_
+:M: Marek Vasut <marek.vasut@gmail.com>
+:G: `marex`_
+:M: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+:G: `prabhakarlad`_
+:F: docs/plat/rz-g2.rst
+:F: plat/renesas/common
+:F: plat/renesas/rzg
+:F: drivers/renesas/common
+:F: drivers/renesas/rzg
+:F: tools/renesas/rzg_layout_create
+
RockChip platform port
^^^^^^^^^^^^^^^^^^^^^^
:M: Tony Xie <tony.xie@rock-chips.com>
@@ -516,8 +542,8 @@ Synquacer platform port
Texas Instruments platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Andrew F. Davis <afd@ti.com>
-:G: `glneo`_
+:M: Nishanth Menon <nm@ti.com>
+:G: `nmenon`_
:F: docs/plat/ti-k3.rst
:F: plat/ti/
@@ -529,8 +555,10 @@ UniPhier platform port
Xilinx platform port
^^^^^^^^^^^^^^^^^^^^
-:M: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
-:G: `sivadur`_
+:M: Michal Simek <michal.simek@xilinx.com>
+:G: `michalsimek`_
+:M: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
+:G: `venkatesh`_
:F: docs/plat/xilinx-zynqmp.rst
:F: plat/xilinx/
@@ -599,6 +627,7 @@ Build system
.. _AlexeiFedorov: https://github.com/AlexeiFedorov
.. _Andre-ARM: https://github.com/Andre-ARM
.. _Anson-Huang: https://github.com/Anson-Huang
+.. _bijucdas: https://github.com/bijucdas
.. _bryanodonoghue: https://github.com/bryanodonoghue
.. _b49020: https://github.com/b49020
.. _carlocaione: https://github.com/carlocaione
@@ -614,23 +643,26 @@ Build system
.. _ldts: https://github.com/ldts
.. _marex: https://github.com/marex
.. _masahir0y: https://github.com/masahir0y
+.. _michalsimek: https://github.com/michalsimek
.. _mmind: https://github.com/mmind
+.. _MrVan: https://github.com/MrVan
.. _mtk09422: https://github.com/mtk09422
.. _niej: https://github.com/niej
.. _npoushin: https://github.com/npoushin
+.. _prabhakarlad: https://github.com/prabhakarlad
.. _qoriq-open-source: https://github.com/qoriq-open-source
.. _remi-triplefault: https://github.com/repk
.. _rockchip-linux: https://github.com/rockchip-linux
.. _sandrine-bailleux-arm: https://github.com/sandrine-bailleux-arm
.. _sgorecha: https://github.com/sgorecha
.. _shawnguo2: https://github.com/shawnguo2
-.. _sivadur: https://github.com/sivadur
.. _smaeul: https://github.com/smaeul
.. _soby-mathew: https://github.com/soby-mathew
.. _thloh85-intel: https://github.com/thloh85-intel
.. _thomas-arm: https://github.com/thomas-arm
.. _TonyXie06: https://github.com/TonyXie06
.. _vwadekar: https://github.com/vwadekar
+.. _venkatesh: https://github.com/vabbarap
.. _Yann-lms: https://github.com/Yann-lms
.. _manish-pandey-arm: https://github.com/manish-pandey-arm
.. _mardyk01: https://github.com/mardyk01
@@ -648,5 +680,6 @@ Build system
.. _john-powell-arm: https://github.com/john-powell-arm
.. _raghuncstate: https://github.com/raghuncstate
.. _CJKay: https://github.com/cjkay
+.. _nmenon: https://github.com/nmenon
.. _Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/
diff --git a/docs/change-log.rst b/docs/change-log.rst
index 3b8f8365cb..ec88df921a 100644
--- a/docs/change-log.rst
+++ b/docs/change-log.rst
@@ -689,10 +689,10 @@ New Features
- arm/common: Allow boards to specify second DRAM Base address
and to define PLAT_ARM_TZC_FILTERS
- - arm/cornstone700: Add support for mhuv2 and stack protector
+ - arm/corstone700: Add support for mhuv2 and stack protector
- arm/fvp: Add support for fconf in BL31 and SP_MIN. Populate power
- domain desciptor dynamically by leveraging fconf APIs.
+ domain descriptor dynamically by leveraging fconf APIs.
- arm/fvp: Add Cactus/Ivy Secure Partition information and use two
instances of Cactus at S-EL1
- arm/fvp: Add support to run BL32 in TDRAM and BL31 in secure DRAM
@@ -967,7 +967,7 @@ Changed
cpu clock, Move versal_def.h and versal_private to include directory
- Tools
- - sptool: Updated sptool to accomodate building secure partition packages.
+ - sptool: Updated sptool to accommodate building secure partition packages.
Resolved Issues
^^^^^^^^^^^^^^^
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index c0fda78dd7..7c142d132c 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -249,6 +249,9 @@ For Cortex-A76, the following errata build flags are defined :
- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
+- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76
+ CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU.
+
For Cortex-A77, the following errata build flags are defined :
- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77
@@ -262,6 +265,13 @@ For Cortex-A78, the following errata build flags are defined :
- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
+- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78
+ CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
+
+- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78
+ CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same
+ issue but there is no workaround for that revision.
+
For Neoverse N1, the following errata build flags are defined :
- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
@@ -300,6 +310,10 @@ For Neoverse N1, the following errata build flags are defined :
- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1
CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
+- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1
+ CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for
+ revisions r0p0, r1p0, and r2p0 there is no workaround.
+
DSU Errata Workarounds
----------------------
@@ -363,10 +377,11 @@ architecture that can be enabled by the platform as desired.
Cortex-A57 based platform must make its own decision on whether to use
the optimization. This flag is disabled by default.
-- ``NEOVERSE_N1_EXTERNAL_LLC``: This flag indicates that an external last
+- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last
level cache(LLC) is present in the system, and that the DataSource field
on the master CHI interface indicates when data is returned from the LLC.
This is used to control how the LL_CACHE* PMU events count.
+ Default value is 0 (Disabled).
--------------
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 8adf4ad8ba..c520e0c22e 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -26,6 +26,12 @@ Common build options
``aarch64`` or ``aarch32`` as values. By default, it is defined to
``aarch64``.
+- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies
+ one or more feature modifiers. This option has the form ``[no]feature+...``
+ and defaults to ``none``. It translates into compiler option
+ ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the
+ list of supported feature modifiers.
+
- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
*Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
@@ -185,6 +191,11 @@ Common build options
of the binary image. If set to 1, then only the ELF image is built.
0 is the default.
+- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented
+ (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms
+ that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU,
+ check the latest Arm ARM.
+
- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
Board Boot authentication at runtime. This option is meant to be enabled only
for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
@@ -392,7 +403,7 @@ Common build options
library is not supported.
- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the
- bottom, higher addresses at the top. This buid flag can be set to '1' to
+ bottom, higher addresses at the top. This build flag can be set to '1' to
invert this behavior. Lower addresses will be printed at the top and higher
addresses at the bottom.
@@ -559,7 +570,7 @@ Common build options
- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS
sections of BL31 (.bss, stacks, page tables, and coherent memory) to be
allocated in RAM discontiguous from the loaded firmware image. When set, the
- platform is expected to provide definitons for ``BL31_NOBITS_BASE`` and
+ platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and
``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS
sections are placed in RAM immediately following the loaded firmware image.
diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst
index d063ec7e62..be3f0bb0ff 100644
--- a/docs/getting_started/porting-guide.rst
+++ b/docs/getting_started/porting-guide.rst
@@ -2009,6 +2009,53 @@ interrupt and the interrupt ID are passed as parameters.
The default implementation only prints out a warning message.
+.. _porting_guide_trng_requirements:
+
+TRNG porting requirements
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The |TRNG| backend requires the platform to provide the following values
+and mandatory functions.
+
+Values
+......
+
+value: uuid_t plat_trng_uuid [mandatory]
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+This value must be defined to the UUID of the TRNG backend that is specific to
+the hardware after ``plat_trng_setup`` function is called. This value must
+conform to the SMCCC calling convention; The most significant 32 bits of the
+UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in
+w0 indicates failure to get a TRNG source.
+
+Functions
+.........
+
+Function: void plat_entropy_setup(void) [mandatory]
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+::
+
+ Argument: none
+ Return: none
+
+This function is expected to do platform-specific initialization of any TRNG
+hardware. This may include generating a UUID from a hardware-specific seed.
+
+Function: bool plat_get_entropy(uint64_t \*out) [mandatory]
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+::
+
+ Argument: uint64_t *
+ Return: bool
+ Out : when the return value is true, the entropy has been written into the
+ storage pointed to
+
+This function writes entropy into storage provided by the caller. If no entropy
+is available, it must return false and the storage must not be written.
+
Power State Coordination Interface (in BL31)
--------------------------------------------
@@ -2941,7 +2988,7 @@ amount of open resources per driver.
--------------
-*Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.*
.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
diff --git a/docs/global_substitutions.txt b/docs/global_substitutions.txt
index d33155b9ac..24ac8300e6 100644
--- a/docs/global_substitutions.txt
+++ b/docs/global_substitutions.txt
@@ -56,6 +56,7 @@
.. |TF-M| replace:: :term:`TF-M`
.. |TLB| replace:: :term:`TLB`
.. |TLK| replace:: :term:`TLK`
+.. |TRNG| replace:: :term:`TRNG`
.. |TSP| replace:: :term:`TSP`
.. |TZC| replace:: :term:`TZC`
.. |UBSAN| replace:: :term:`UBSAN`
diff --git a/docs/glossary.rst b/docs/glossary.rst
index 08add3a702..54820e4b62 100644
--- a/docs/glossary.rst
+++ b/docs/glossary.rst
@@ -193,6 +193,9 @@ You can find additional definitions in the `Arm Glossary`_.
TLK
Trusted Little Kernel. A Trusted OS from NVIDIA.
+ TRNG
+ True Randon Number Generator (hardware based)
+
TSP
Test Secure Payload
diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst
index 2e50068f66..a1d2313575 100644
--- a/docs/plat/arm/arm-build-options.rst
+++ b/docs/plat/arm/arm-build-options.rst
@@ -94,6 +94,10 @@ Arm Platform Build Options
- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the
SPMC Core manifest. Valid when ``SPD=spmd`` is selected.
+- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in tb_fw_config
+ device tree. This flag is defined only when ``ARM_SPMC_MANIFEST_DTS`` manifest
+ file name contains pattern optee_sp.
+
For a better understanding of these options, the Arm development platform memory
map is explained in the :ref:`Firmware Design`.
diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst
index 3a13268fa3..235b7b6879 100644
--- a/docs/plat/arm/fvp/index.rst
+++ b/docs/plat/arm/fvp/index.rst
@@ -49,7 +49,8 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores
- ``FVP_RD_E1_edge`` (Version 11.9 build 41)
- ``FVP_RD_N1_edge`` (Version 11.10 build 36)
- ``FVP_RD_N1_edge_dual`` (Version 11.10 build 36)
-- ``FVP_RD_Daniel`` (Version 11.10 build 36)
+- ``FVP_RD_Daniel`` (Version 11.13 build 10)
+- ``FVP_RD_N2`` (Version 11.13 build 10)
- ``FVP_TC0`` (Version 0.0 build 6114)
- ``Foundation_Platform``
@@ -141,6 +142,11 @@ Arm FVP Platform Specific Build Options
HW_CONFIG blob instead of the DTS file. This option is useful to override
the default HW_CONFIG selected by the build system.
+- ``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of
+ inactive/fused CPU cores as read-only. The default value of this option
+ is ``0``, which means the redistributor pages of all CPU cores are marked
+ as read and write.
+
Booting Firmware Update images
------------------------------
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index fb60e56392..3cbb552466 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -32,6 +32,7 @@ Platform Ports
rpi3
rpi4
rcar-gen3
+ rz-g2
rockchip
socionext-uniphier
synquacer
diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst
index 54182cb082..e55ce3c09f 100644
--- a/docs/plat/marvell/armada/build.rst
+++ b/docs/plat/marvell/armada/build.rst
@@ -51,6 +51,18 @@ Install ARM 32-bit cross compiler, which is required for building WTMI image for
There are several build options:
+- PLAT
+
+ Supported Marvell platforms are:
+
+ - a3700 - A3720 DB, EspressoBin and Turris MOX
+ - a70x0
+ - a70x0_amc - AMC board
+ - a80x0
+ - a80x0_mcbin - MacchiatoBin
+ - a80x0_puzzle - IEI Puzzle-M801
+ - t9130 - CN913x
+
- DEBUG
Default is without debug information (=0). in order to enable it use ``DEBUG=1``.
@@ -86,6 +98,20 @@ There are several build options:
There is no reason to enable this feature if OP-TEE OS built with CFG_WITH_PAGER=n.
Only set LLC_SRAM=1 if OP-TEE OS is built with CFG_WITH_PAGER=y.
+- CM3_SYSTEM_RESET
+
+ For Armada37x0 only, when ``CM3_SYSTEM_RESET=1``, the Cortex-M3 secure coprocessor will
+ be used for system reset.
+ TF-A will send command 0x0009 with a magic value via the rWTM mailbox interface to the
+ Cortex-M3 secure coprocessor.
+ The firmware running in the coprocessor must either implement this functionality or
+ ignore the 0x0009 command (which is true for the firmware from A3700-utils-marvell
+ repository). If this option is enabled but the firmware does not support this command,
+ an error message will be printed prior trying to reboot via the usual way.
+
+ This option is needed on Turris MOX as a workaround to a HW bug which causes reset to
+ sometime hang the board.
+
- MARVELL_SECURE_BOOT
Build trusted(=1)/non trusted(=0) image, default is non trusted.
@@ -109,6 +135,9 @@ There are several build options:
For the mv_ddr source location, check the section "Tools and external components installation"
+ If MV_DDR_PATH source code is a git snapshot then provide path to the full git
+ repository (including .git subdir) because mv_ddr build process calls git commands.
+
- CP_NUM
Total amount of CPs (South Bridge) connected to AP. When the parameter is omitted,
@@ -122,15 +151,15 @@ There are several build options:
For Armada37x0 only, the DDR topology map index/name, default is 0.
Supported Options:
- - 0 - DDR3 1CS: DB-88F3720-DDR3-Modular (512MB); EspressoBIN (512MB)
- - 1 - DDR4 1CS: DB-88F3720-DDR4-Modular (512MB)
- - 2 - DDR3 2CS: EspressoBIN V3-V5 (1GB 2CS)
- - 3 - DDR4 2CS: DB-88F3720-DDR4-Modular (4GB)
- - 4 - DDR3 1CS: DB-88F3720-DDR3-Modular (1GB); EspressoBIN V3-V5 (1GB 1CS)
- - 5 - DDR4 1CS: EspressoBin V7 (1GB)
- - 6 - DDR4 2CS: EspressoBin V7 (2GB)
- - 7 - DDR3 2CS: EspressoBin V3-V5 (2GB)
- - CUST - CUSTOMER: Customer board, DDR3 1CS 512MB
+ - 0 - DDR3 1CS 512MB (DB-88F3720-DDR3-Modular, EspressoBin V3-V5)
+ - 1 - DDR4 1CS 512MB (DB-88F3720-DDR4-Modular)
+ - 2 - DDR3 2CS 1GB (EspressoBin V3-V5)
+ - 3 - DDR4 2CS 4GB (DB-88F3720-DDR4-Modular)
+ - 4 - DDR3 1CS 1GB (DB-88F3720-DDR3-Modular, EspressoBin V3-V5)
+ - 5 - DDR4 1CS 1GB (EspressoBin V7, EspressoBin-Ultra)
+ - 6 - DDR4 2CS 2GB (EspressoBin V7)
+ - 7 - DDR3 2CS 2GB (EspressoBin V3-V5)
+ - CUST - CUSTOMER BOARD (Customer board settings)
- CLOCKSPRESET
@@ -142,6 +171,13 @@ There are several build options:
- CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz
- CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz
+ Look at Armada37x0 chip package marking on board to identify correct CPU frequency.
+ The last line on package marking (next line after the 88F37x0 line) should contain:
+
+ - C080 or I080 - chip with 800 MHz CPU - use ``CLOCKSPRESET=CPU_800_DDR_800``
+ - C100 or I100 - chip with 1000 MHz CPU - use ``CLOCKSPRESET=CPU_1000_DDR_800``
+ - C120 - chip with 1200 MHz CPU - use ``CLOCKSPRESET=CPU_1200_DDR_750``
+
- BOOTDEV
For Armada37x0 only, the flash boot device, default is ``SPINOR``.
@@ -157,6 +193,10 @@ There are several build options:
- SATA - SATA device boot
+ Image needs to be stored at disk LBA 0 or at disk partition with
+ MBR type 0x4d (ASCII 'M' as in Marvell) or at disk partition with
+ GPT name ``MARVELL BOOT PARTITION``.
+
- PARTNUM
For Armada37x0 only, the boot partition number, default is 0.
@@ -168,22 +208,43 @@ There are several build options:
- WTMI_IMG
- For Armada37x0 only, the path of the WTMI image can point to an image which
+ For Armada37x0 only, the path of the binary can point to an image which
does nothing, an image which supports EFUSE or a customized CM3 firmware
- binary. The default image is wtmi.bin that built from sources in WTP
+ binary. The default image is ``fuse.bin`` that built from sources in WTP
folder, which is the next option. If the default image is OK, then this
option should be skipped.
+ Please note that this is not a full WTMI image, just a main loop without
+ hardware initialization code. Final WTMI image is built from this WTMI_IMG
+ binary and sys-init code from the WTP directory which sets DDR and CPU
+ clocks according to DDR_TOPOLOGY and CLOCKSPRESET options.
+
- WTP
For Armada37x0 only, use this parameter to point to wtptools source code
directory, which can be found as a3700_utils.zip in the release. Usage
example: ``WTP=/path/to/a3700_utils``
+ If WTP source code is a git snapshot then provide path to the full git
+ repository (including .git subdir) because WTP build process calls git commands.
+
- CRYPTOPP_PATH
- For Armada37x0 only, use this parameter tp point to Crypto++ source code
- directory, which is required for building WTP image tool.
+ For Armada37x0 only, use this parameter to point to Crypto++ source code
+ directory. If this option is specified then Crypto++ source code in
+ CRYPTOPP_PATH directory will be automatically compiled. Crypto++ library
+ is required for building WTP image tool. Either CRYPTOPP_PATH or
+ CRYPTOPP_LIBDIR with CRYPTOPP_INCDIR needs to be specified for Armada37x0.
+
+- CRYPTOPP_LIBDIR
+
+ For Armada37x0 only, use this parameter to point to the directory with
+ compiled Crypto++ library. By default it points to the CRYPTOPP_PATH.
+
+- CRYPTOPP_INCDIR
+
+ For Armada37x0 only, use this parameter to point to the directory with
+ header files of Crypto++ library. By default it points to the CRYPTOPP_PATH.
For example, in order to build the image in debug mode with log level up to 'notice' level run
@@ -203,21 +264,33 @@ line is as following
MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 \
MV_DDR_PATH=/path/to/mv-ddr-marvell/ WTP=/path/to/A3700-utils-marvell/ \
CRYPTOPP_PATH=/path/to/cryptopp/ BL33=/path/to/u-boot.bin \
- all fip mrvl_bootimage mrvl_flash
+ all fip mrvl_bootimage mrvl_flash mrvl_uart
To build just TF-A without WTMI image (useful for A3720 Turris MOX board), run following command:
.. code:: shell
- > make USE_COHERENT_MEM=0 PLAT=a3700 BL33=/path/to/u-boot.bin CROSS_COMPILE=aarch64-linux-gnu- mrvl_bootimage
+ > make USE_COHERENT_MEM=0 PLAT=a3700 CM3_SYSTEM_RESET=1 BL33=/path/to/u-boot.bin \
+ CROSS_COMPILE=aarch64-linux-gnu- mrvl_bootimage
+
+Here is full example how to build production release of Marvell firmware image (concatenated
+binary of Marvell secure firmware, TF-A and U-Boot) for EspressoBin board (PLAT=a3700) with
+1GHz CPU (CLOCKSPRESET=CPU_1000_DDR_800) and 1GB DDR4 RAM (DDR_TOPOLOGY=5):
+
+.. code:: shell
+
+ > git clone https://review.trustedfirmware.org/TF-A/trusted-firmware-a
+ > git clone https://gitlab.denx.de/u-boot/u-boot.git
+ > git clone https://github.com/weidai11/cryptopp.git
+ > git clone https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git -b master
+ > git clone https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git -b master
+ > make -C u-boot CROSS_COMPILE=aarch64-linux-gnu- mvebu_espressobin-88f3720_defconfig u-boot.bin
+ > make -C trusted-firmware-a CROSS_COMPILE=aarch64-linux-gnu- CROSS_CM3=arm-linux-gnueabi- \
+ USE_COHERENT_MEM=0 PLAT=a3700 CLOCKSPRESET=CPU_1000_DDR_800 DDR_TOPOLOGY=5 \
+ MV_DDR_PATH=$PWD/mv-ddr-marvell/ WTP=$PWD/A3700-utils-marvell/ CRYPTOPP_PATH=$PWD/cryptopp/ \
+ BL33=$PWD/u-boot/u-boot.bin mrvl_flash
-Supported MARVELL_PLATFORM are:
- - a3700 (for both A3720 DB and EspressoBin)
- - a70x0
- - a70x0_amc (for AMC board)
- - a80x0
- - a80x0_mcbin (for MacchiatoBin)
- - t9130 (OcteonTX2 CN913x)
+Produced Marvell firmware flash image: ``trusted-firmware-a/build/a3700/release/flash-image.bin``
Special Build Flags
--------------------
@@ -241,20 +314,22 @@ Build output
------------
Marvell's TF-A compilation generates 8 files:
- - ble.bin - BLe image
+ - ble.bin - BLe image (not available for Armada37x0)
- bl1.bin - BL1 image
- bl2.bin - BL2 image
- bl31.bin - BL31 image
- fip.bin - FIP image (contains BL2, BL31 & BL33 (U-Boot) images)
- boot-image.bin - TF-A image (contains BL1 and FIP images)
- - flash-image.bin - Image which contains boot-image.bin and SPL image.
- Should be placed on the boot flash/device.
+ - flash-image.bin - Flashable Marvell firmware image. For Armada37x0 it
+ contains TIM, WTMI and boot-image.bin images. For other platforms it contains
+ BLe and boot-image.bin images. Should be placed on the boot flash/device.
- uart-images.tgz.bin - GZIPed TAR archive which contains Armada37x0 images
for booting via UART. Could be loaded via Marvell's WtpDownload tool from
A3700-utils-marvell repository.
-Additional make target ``mrvl_bootimage`` produce ``boot-image.bin`` file and target
-``mrvl_flash`` produce final ``flash-image.bin`` and ``uart-images.tgz.bin`` files.
+Additional make target ``mrvl_bootimage`` produce ``boot-image.bin`` file. Target
+``mrvl_flash`` produce final ``flash-image.bin`` file and target ``mrvl_uart``
+produce ``uart-images.tgz.bin`` file.
Tools and external components installation
@@ -281,12 +356,12 @@ Armada37x0 Builds require installation of 3 components
> export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi
(2) DDR initialization library sources (mv_ddr) available at the following repository
- (use the "mv-ddr-devel" branch):
+ (use the "master" branch):
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
(3) Armada3700 tools available at the following repository
- (use the "A3700_utils-armada-18.12-fixed" branch):
+ (use the "master" branch):
https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git
@@ -298,6 +373,6 @@ Armada70x0 and Armada80x0 Builds require installation of an additional component
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
(1) DDR initialization library sources (mv_ddr) available at the following repository
- (use the "mv-ddr-devel" branch):
+ (use the "master" branch):
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
diff --git a/docs/plat/marvell/armada/misc/mvebu-ccu.rst b/docs/plat/marvell/armada/misc/mvebu-ccu.rst
index 5bac11fafc..12118e9d99 100644
--- a/docs/plat/marvell/armada/misc/mvebu-ccu.rst
+++ b/docs/plat/marvell/armada/misc/mvebu-ccu.rst
@@ -1,7 +1,7 @@
Marvell CCU address decoding bindings
=====================================
-CCU configration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs.
+CCU configuration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs.
The CCU node includes a description of the address decoding configuration.
diff --git a/docs/plat/marvell/armada/misc/mvebu-io-win.rst b/docs/plat/marvell/armada/misc/mvebu-io-win.rst
index 52845ca029..7498291997 100644
--- a/docs/plat/marvell/armada/misc/mvebu-io-win.rst
+++ b/docs/plat/marvell/armada/misc/mvebu-io-win.rst
@@ -1,7 +1,7 @@
Marvell IO WIN address decoding bindings
========================================
-IO Window configration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
+IO Window configuration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
The IO WIN includes a description of the address decoding configuration.
diff --git a/docs/plat/marvell/armada/misc/mvebu-iob.rst b/docs/plat/marvell/armada/misc/mvebu-iob.rst
index d02a7e84c9..aa41822f4f 100644
--- a/docs/plat/marvell/armada/misc/mvebu-iob.rst
+++ b/docs/plat/marvell/armada/misc/mvebu-iob.rst
@@ -1,7 +1,7 @@
Marvell IOB address decoding bindings
=====================================
-IO bridge configration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
+IO bridge configuration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
The IOB includes a description of the address decoding configuration.
diff --git a/docs/plat/rpi4.rst b/docs/plat/rpi4.rst
index beb0227c2e..6e83fd7303 100644
--- a/docs/plat/rpi4.rst
+++ b/docs/plat/rpi4.rst
@@ -60,7 +60,7 @@ As with the previous models, the GPU and its firmware are the first entity to
run after the SoC gets its power. The on-chip Boot ROM loads the next stage
(bootcode.bin) from flash (EEPROM), which is again GPU code.
This part knows how to access the MMC controller and how to parse a FAT
-filesystem, so it will load further compononents and configuration files
+filesystem, so it will load further components and configuration files
from the first FAT partition on the SD card.
To accommodate this existing way of configuring and setting up the board,
diff --git a/docs/plat/rz-g2.rst b/docs/plat/rz-g2.rst
new file mode 100644
index 0000000000..e7ae620400
--- /dev/null
+++ b/docs/plat/rz-g2.rst
@@ -0,0 +1,228 @@
+Renesas RZ/G
+============
+
+The "RZ/G" Family of high-end 64-bit Arm®-based microprocessors (MPUs)
+enables the solutions required for the smart society of the future.
+Through a variety of Arm Cortex®-A53 and A57-based devices, engineers can
+easily implement high-resolution human machine interfaces (HMI), embedded
+vision, embedded artificial intelligence (e-AI) and real-time control and
+industrial ethernet connectivity.
+
+The scalable RZ/G hardware platform and flexible software platform
+cover the full product range, from the premium class to the entry
+level. Plug-ins are available for multiple open-source software tools.
+
+
+Renesas RZ/G2 reference platforms:
+----------------------------------
+
++--------------+----------------------------------------------------------------------------------+
+| Board | Details |
++==============+===============+==================================================================+
+| hihope-rzg2h | "96 boards" compatible board from Hoperun equipped with Renesas RZ/G2H SoC |
+| +----------------------------------------------------------------------------------+
+| | http://hihope.org/product/musashi |
++--------------+----------------------------------------------------------------------------------+
+| hihope-rzg2m | "96 boards" compatible board from Hoperun equipped with Renesas RZ/G2M SoC |
+| +----------------------------------------------------------------------------------+
+| | http://hihope.org/product/musashi |
++--------------+----------------------------------------------------------------------------------+
+| hihope-rzg2n | "96 boards" compatible board from Hoperun equipped with Renesas RZ/G2N SoC |
+| +----------------------------------------------------------------------------------+
+| | http://hihope.org/product/musashi |
++--------------+----------------------------------------------------------------------------------+
+| ek874 | "96 boards" compatible board from Silicon Linux equipped with Renesas RZ/G2E SoC |
+| +----------------------------------------------------------------------------------+
+| | https://www.si-linux.co.jp/index.php?CAT%2FCAT874 |
++--------------+----------------------------------------------------------------------------------+
+
+`boards info <https://www.renesas.com/us/en/products/rzg-linux-platform/rzg-marcketplace/board-solutions.html#rzg2>`__
+
+The current TF-A port has been tested on the HiHope RZ/G2M
+SoC_id r8a774a1 revision ES1.3.
+
+
+::
+
+ ARM CA57 (ARMv8) 1.5 GHz dual core, with NEON/VFPv4, L1$ I/D 48K/32K, L2$ 1MB
+ ARM CA53 (ARMv8) 1.2 GHz quad core, with NEON/VFPv4, L1$ I/D 32K/32K, L2$ 512K
+ Memory controller for LPDDR4-3200 4GB in 2 channels(32-bit bus mode)
+ Two- and three-dimensional graphics engines,
+ Video processing units,
+ Display Output,
+ Video Input,
+ SD card host interface,
+ USB3.0 and USB2.0 interfaces,
+ CAN interfaces,
+ Ethernet AVB,
+ Wi-Fi + BT,
+ PCI Express Interfaces,
+ Memories
+ INTERNAL 384KB SYSTEM RAM
+ DDR 4 GB LPDDR4
+ QSPI FLASH 64MB
+ EMMC 32 GB EMMC (HS400 240 MBYTES/S)
+ MICROSD-CARD SLOT (SDR104 100 MBYTES/S)
+
+Overview
+--------
+On RZ/G2 SoCs the BOOTROM starts the cpu at EL3; for this port BL2
+will therefore be entered at this exception level (the Renesas' ATF
+reference tree [1] resets into EL1 before entering BL2 - see its
+bl2.ld.S)
+
+BL2 initializes DDR before determining the boot reason (cold or warm).
+
+Once BL2 boots, it determines the boot reason, writes it to shared
+memory (BOOT_KIND_BASE) together with the BL31 parameters
+(PARAMS_BASE) and jumps to BL31.
+
+To all effects, BL31 is as if it is being entered in reset mode since
+it still needs to initialize the rest of the cores; this is the reason
+behind using direct shared memory access to BOOT_KIND_BASE _and_
+PARAMS_BASE instead of using registers to get to those locations (see
+el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
+case).
+
+[1] https://github.com/renesas-rz/meta-rzg2/tree/BSP-1.0.5/recipes-bsp/arm-trusted-firmware/files
+
+
+How to build
+------------
+
+The TF-A build options depend on the target board so you will have to
+refer to those specific instructions. What follows is customized to
+the HiHope RZ/G2M development kit used in this port.
+
+Build Tested:
+~~~~~~~~~~~~~
+
+.. code:: bash
+
+ make bl2 bl31 rzg LOG_LEVEL=40 PLAT=rzg LSI=G2M RCAR_DRAM_SPLIT=2\
+ RCAR_LOSSY_ENABLE=1 SPD="none" MBEDTLS_DIR=$mbedtls
+
+System Tested:
+~~~~~~~~~~~~~~
+* mbed_tls:
+ git@github.com:ARMmbed/mbedtls.git [devel]
+
+| commit 72ca39737f974db44723760623d1b29980c00a88
+| Merge: ef94c4fcf dd9ec1c57
+| Author: Janos Follath <janos.follath@arm.com>
+| Date: Wed Oct 7 09:21:01 2020 +0100
+
+* u-boot:
+ The port has beent tested using mainline uboot with HiHope RZ/G2M board
+ specific patches.
+
+| commit 46ce9e777c1314ccb78906992b94001194eaa87b
+| Author: Heiko Schocher <hs@denx.de>
+| Date: Tue Nov 3 15:22:36 2020 +0100
+
+* linux:
+ The port has beent tested using mainline kernel.
+
+| commit f8394f232b1eab649ce2df5c5f15b0e528c92091
+| Author: Linus Torvalds <torvalds@linux-foundation.org>
+| Date: Sun Nov 8 16:10:16 2020 -0800
+| Linux 5.10-rc3
+
+TF-A Build Procedure
+~~~~~~~~~~~~~~~~~~~~
+
+- Fetch all the above 3 repositories.
+
+- Prepare the AARCH64 toolchain.
+
+- Build u-boot using hihope_rzg2_defconfig.
+
+ Result: u-boot-elf.srec
+
+.. code:: bash
+
+ make CROSS_COMPILE=aarch64-linux-gnu-
+ hihope_rzg2_defconfig
+
+ make CROSS_COMPILE=aarch64-linux-gnu-
+
+- Build TF-A
+
+ Result: bootparam_sa0.srec, cert_header_sa6.srec, bl2.srec, bl31.srec
+
+.. code:: bash
+
+ make bl2 bl31 rzg LOG_LEVEL=40 PLAT=rzg LSI=G2M RCAR_DRAM_SPLIT=2\
+ RCAR_LOSSY_ENABLE=1 SPD="none" MBEDTLS_DIR=$mbedtls
+
+
+Install Procedure
+~~~~~~~~~~~~~~~~~
+
+- Boot the board in Mini-monitor mode and enable access to the
+ QSPI flash.
+
+
+- Use the flash_writer utility[2] to flash all the SREC files.
+
+[2] https://github.com/renesas-rz/rzg2_flash_writer
+
+
+Boot trace
+----------
+::
+
+ INFO: ARM GICv2 driver initialized
+ NOTICE: BL2: RZ/G2 Initial Program Loader(CA57) Rev.2.0.6
+ NOTICE: BL2: PRR is RZ/G2M Ver.1.3
+ NOTICE: BL2: Board is HiHope RZ/G2M Rev.4.0
+ NOTICE: BL2: Boot device is QSPI Flash(40MHz)
+ NOTICE: BL2: LCM state is unknown
+ NOTICE: BL2: DDR3200(rev.0.40)
+ NOTICE: BL2: [COLD_BOOT]
+ NOTICE: BL2: DRAM Split is 2ch
+ NOTICE: BL2: QoS is default setting(rev.0.19)
+ NOTICE: BL2: DRAM refresh interval 1.95 usec
+ NOTICE: BL2: Periodic Write DQ Training
+ NOTICE: BL2: CH0: 400000000 - 47fffffff, 2 GiB
+ NOTICE: BL2: CH2: 600000000 - 67fffffff, 2 GiB
+ NOTICE: BL2: Lossy Decomp areas
+ NOTICE: Entry 0: DCMPAREACRAx:0x80000540 DCMPAREACRBx:0x570
+ NOTICE: Entry 1: DCMPAREACRAx:0x40000000 DCMPAREACRBx:0x0
+ NOTICE: Entry 2: DCMPAREACRAx:0x20000000 DCMPAREACRBx:0x0
+ NOTICE: BL2: FDT at 0xe631db30
+ NOTICE: BL2: v2.3(release):v2.4-rc0-2-g1433701e5
+ NOTICE: BL2: Built : 13:45:26, Nov 7 2020
+ NOTICE: BL2: Normal boot
+ INFO: BL2: Doing platform setup
+ INFO: BL2: Loading image id 3
+ NOTICE: BL2: dst=0xe631d200 src=0x8180000 len=512(0x200)
+ NOTICE: BL2: dst=0x43f00000 src=0x8180400 len=6144(0x1800)
+ WARNING: r-car ignoring the BL31 size from certificate,using RCAR_TRUSTED_SRAM_SIZE instead
+ INFO: Loading image id=3 at address 0x44000000
+ NOTICE: rcar_file_len: len: 0x0003e000
+ NOTICE: BL2: dst=0x44000000 src=0x81c0000 len=253952(0x3e000)
+ INFO: Image id=3 loaded: 0x44000000 - 0x4403e000
+ INFO: BL2: Loading image id 5
+ INFO: Loading image id=5 at address 0x50000000
+ NOTICE: rcar_file_len: len: 0x00100000
+ NOTICE: BL2: dst=0x50000000 src=0x8300000 len=1048576(0x100000)
+ INFO: Image id=5 loaded: 0x50000000 - 0x50100000
+ NOTICE: BL2: Booting BL31
+ INFO: Entry point address = 0x44000000
+ INFO: SPSR = 0x3cd
+
+
+ U-Boot 2021.01-rc1-00244-gac37e14fbd (Nov 04 2020 - 20:03:34 +0000)
+
+ CPU: Renesas Electronics R8A774A1 rev 1.3
+ Model: HopeRun HiHope RZ/G2M with sub board
+ DRAM: 3.9 GiB
+ MMC: mmc@ee100000: 0, mmc@ee160000: 1
+ Loading Environment from MMC... OK
+ In: serial@e6e88000
+ Out: serial@e6e88000
+ Err: serial@e6e88000
+ Net: eth0: ethernet@e6800000
+ Hit any key to stop autoboot: 0
+ =>
diff --git a/docs/plat/stm32mp1.rst b/docs/plat/stm32mp1.rst
index f597460db2..0ef2923476 100644
--- a/docs/plat/stm32mp1.rst
+++ b/docs/plat/stm32mp1.rst
@@ -95,6 +95,7 @@ Build Instructions
------------------
Boot media(s) supported by BL2 must be specified in the build command.
Available storage medias are:
+
- ``STM32MP_SDMMC``
- ``STM32MP_EMMC``
- ``STM32MP_RAW_NAND``
@@ -112,6 +113,7 @@ To build with SP_min and support for all bootable devices:
make DEVICE_TREE=stm32mp157c-ev1 all
To build TF-A with OP-TEE support for all bootable devices:
+
.. code:: bash
make CROSS_COMPILE=arm-linux-gnueabihf- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 AARCH32_SP=optee STM32MP_SDMMC=1 STM32MP_EMMC=1 STM32MP_RAW_NAND=1 STM32MP_SPI_NAND=1 STM32MP_SPI_NOR=1 DTB_FILE_NAME=stm32mp157c-ev1.dtb
diff --git a/docs/resources/diagrams/plantuml/fip-secure-partitions.puml b/docs/resources/diagrams/plantuml/fip-secure-partitions.puml
index 40621dbed8..9457e326aa 100644
--- a/docs/resources/diagrams/plantuml/fip-secure-partitions.puml
+++ b/docs/resources/diagrams/plantuml/fip-secure-partitions.puml
@@ -13,6 +13,7 @@ folder SP_vendor_1 {
===
UUID = xxx
load_address = 0xaaa
+ owner = "Sip"
...
]
}
@@ -24,9 +25,26 @@ folder SP_vendor_2 {
===
UUID = yyy
load_address = 0xbbb
+ owner = "Plat"
]
}
+artifact tb_fw_config.dts [
+ tb_fw_config.dts
+ ----
+ secure-partitions
+ ===
+ spkg_1 UUID
+ spkg_1 load_address
+ ---
+ spkg_2 UUID
+ spkg_2 load_address
+ ---
+ ...
+ ===
+ ...<rest of the nodes>
+]
+
artifact config.json [
SP_LAYOUT.json
===
@@ -41,31 +59,22 @@ artifact config.json [
control sp_mk_generator
-artifact fconf_node [
- fconf_sp.dts
- ===
- spkg_1 UUID
- spkg_1 load_address
- ---
- spkg_2 UUID
- spkg_2 load_address
-]
-
artifact sp_gen [
sp_gen.mk
===
FDT_SOURCE = ...
SPTOOL_ARGS = ...
- FIP_ARG = ...
+ FIP_ARGS = ...
+ CRT_ARGS = ...
]
control dtc
control sptool
-artifact FW_CONFIG
+artifact tb_fw_config.dtb
artifact spkg_1 [
- spkg_1.bin
+ sp1.pkg
===
<i>header</i>
---
@@ -75,27 +84,56 @@ artifact spkg_1 [
]
artifact spkg_2 [
- spkg_2.bin
+ sp2.pkg
+ ===
+ <i>header</i>
+ ---
+ manifest
+ ---
+ binary
+]
+
+artifact signed_tb_fw_config.dtb [
+ tb_fw_config.dtb (signed)
+]
+
+artifact signed_spkg_1 [
+ sp1.pkg (signed)
+ ===
+ <i>header</i>
+ ---
+ manifest
+ ---
+ binary
+ ---
+ <i>signature</I>
+]
+
+artifact signed_spkg_2 [
+ sp2.pkg (signed)
===
<i>header</i>
---
manifest
---
binary
+ ---
+ <i>signature</I>
]
+control crttool
control fiptool
artifact fip [
fip.bin
===
- FW_CONFIG.dtb
+ tb_fw_config.dtb (signed)
---
...
---
- SPKG1
+ sp1.pkg (signed & SiP owned)
---
- SPKG2
+ sp2.pkg (signed & Platform owned)
---
...
]
@@ -103,20 +141,27 @@ artifact fip [
config.json .up.> SP_vendor_1
config.json .up.> SP_vendor_2
config.json --> sp_mk_generator
-sp_mk_generator --> fconf_node
sp_mk_generator --> sp_gen
-
+sp_gen --> fiptool
+sp_gen --> cert_create
sp_gen --> sptool
+
sptool --> spkg_1
sptool --> spkg_2
-fconf_node -down-> dtc
-dtc --> FW_CONFIG
+spkg_1 --> cert_create
+spkg_2 --> cert_create
+cert_create --> signed_spkg_1
+cert_create --> signed_spkg_2
-sp_gen --> fiptool
-FW_CONFIG --> fiptool
-spkg_1 -down-> fiptool
-spkg_2 -down-> fiptool
+tb_fw_config.dts --> dtc
+dtc --> tb_fw_config.dtb
+tb_fw_config.dtb --> cert_create
+cert_create --> signed_tb_fw_config.dtb
+
+signed_tb_fw_config.dtb --> fiptool
+signed_spkg_1 -down-> fiptool
+signed_spkg_2 -down-> fiptool
fiptool -down-> fip
@enduml
diff --git a/drivers/arm/tzc/tzc400.c b/drivers/arm/tzc/tzc400.c
index 95a5e7f77f..9798ed4e5f 100644
--- a/drivers/arm/tzc/tzc400.c
+++ b/drivers/arm/tzc/tzc400.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -162,7 +162,9 @@ void tzc400_configure_region0(unsigned int sec_attr,
/*
* `tzc400_configure_region` is used to program regions into the TrustZone
* controller. A region can be associated with more than one filter. The
- * associated filters are passed in as a bitmap (bit0 = filter0).
+ * associated filters are passed in as a bitmap (bit0 = filter0), except that
+ * the value TZC_400_REGION_ATTR_FILTER_BIT_ALL selects all filters, based on
+ * the value of tzc400.num_filters.
* NOTE:
* Region 0 is special; it is preferable to use tzc400_configure_region0
* for this region (see comment for that function).
@@ -176,6 +178,11 @@ void tzc400_configure_region(unsigned int filters,
{
assert(tzc400.base != 0U);
+ /* Adjust filter mask by real filter number */
+ if (filters == TZC_400_REGION_ATTR_FILTER_BIT_ALL) {
+ filters = (1U << tzc400.num_filters) - 1U;
+ }
+
/* Do range checks on filters and regions. */
assert(((filters >> tzc400.num_filters) == 0U) &&
(region < tzc400.num_regions));
diff --git a/drivers/cadence/uart/aarch64/cdns_console.S b/drivers/cadence/uart/aarch64/cdns_console.S
index d1995e3e68..4c1a80efc6 100644
--- a/drivers/cadence/uart/aarch64/cdns_console.S
+++ b/drivers/cadence/uart/aarch64/cdns_console.S
@@ -105,15 +105,15 @@ func console_cdns_core_putc
cmp w0, #0xA
b.ne 2f
1:
- /* Check if the transmit FIFO is full */
+ /* Check if the transmit FIFO is empty */
ldr w2, [x1, #R_UART_SR]
- tbnz w2, #UART_SR_INTR_TFUL_BIT, 1b
+ tbz w2, #UART_SR_INTR_TEMPTY_BIT, 1b
mov w2, #0xD
str w2, [x1, #R_UART_TX]
2:
- /* Check if the transmit FIFO is full */
+ /* Check if the transmit FIFO is empty */
ldr w2, [x1, #R_UART_SR]
- tbnz w2, #UART_SR_INTR_TFUL_BIT, 2b
+ tbz w2, #UART_SR_INTR_TEMPTY_BIT, 2b
str w0, [x1, #R_UART_TX]
ret
endfunc console_cdns_core_putc
diff --git a/drivers/marvell/uart/a3700_console.S b/drivers/marvell/uart/a3700_console.S
index d184a2d244..b377321898 100644
--- a/drivers/marvell/uart/a3700_console.S
+++ b/drivers/marvell/uart/a3700_console.S
@@ -60,25 +60,25 @@ func console_a3700_core_init
str w3, [x0, #UART_POSSR_REG]
/*
- * Wait for the TX FIFO to be empty. If wait for 20ms, the TX FIFO is
+ * Wait for the TX (THR and TSR) to be empty. If wait for 3ms, the TX FIFO is
* still not empty, TX FIFO will reset by all means.
*/
- mov w1, #20 /* max time out 20ms */
+ mov w1, #30 /* max time out 30 * 100 us */
2:
- /* Check whether TX FIFO is empty */
+ /* Check whether TX (THR and TSR) is empty */
ldr w3, [x0, #UART_STATUS_REG]
- and w3, w3, #UARTLSR_TXFIFOEMPTY
+ and w3, w3, #UARTLSR_TXEMPTY
cmp w3, #0
b.ne 4f
/* Delay */
- mov w2, #30000
+ mov w2, #60000 /* 60000 cycles of below 3 instructions on 1200 MHz CPU ~~ 100 us */
3:
sub w2, w2, #1
cmp w2, #0
b.ne 3b
- /* Check whether 10ms is waited */
+ /* Check whether wait timeout expired */
sub w1, w1, #1
cmp w1, #0
b.ne 2b
@@ -196,14 +196,23 @@ endfunc console_a3700_putc
* int console_a3700_core_getc(void)
* Function to get a character from the console.
* It returns the character grabbed on success
- * or -1 on error.
+ * or -1 if no character is available.
* In : w0 - console base address
- * Out : return -1 on error else return character.
+ * Out : w0 - character if available, else -1
* Clobber list : x0, x1
* ---------------------------------------------
*/
func console_a3700_core_getc
- mov w0, #-1
+ /* Check if there is a pending character */
+ ldr w1, [x0, #UART_STATUS_REG]
+ and w1, w1, #UARTLSR_RXRDY
+ cmp w1, #UARTLSR_RXRDY
+ b.ne getc_no_char
+ ldr w0, [x0, #UART_RX_REG]
+ and w0, w0, #0xff
+ ret
+getc_no_char:
+ mov w0, #ERROR_NO_PENDING_CHAR
ret
endfunc console_a3700_core_getc
@@ -232,6 +241,11 @@ endfunc console_a3700_getc
* ---------------------------------------------
*/
func console_a3700_core_flush
+ /* Wait for the TX (THR and TSR) to be empty */
+1: ldr w1, [x0, #UART_STATUS_REG]
+ and w1, w1, #UARTLSR_TXEMPTY
+ cmp w1, #UARTLSR_TXEMPTY
+ b.ne 1b
ret
endfunc console_a3700_core_flush
diff --git a/drivers/renesas/rcar/auth/auth_mod.c b/drivers/renesas/common/auth/auth_mod.c
index ece3462f45..4aa86e2a4a 100644
--- a/drivers/renesas/rcar/auth/auth_mod.c
+++ b/drivers/renesas/common/auth/auth_mod.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights
* reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -7,29 +7,28 @@
#include <stddef.h>
-#include <platform_def.h>
-
#include <arch_helpers.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <plat/common/platform.h>
+#include <platform_def.h>
#include "rom_api.h"
typedef int32_t(*secure_boot_api_f) (uint32_t a, uint32_t b, void *c);
extern int32_t rcar_get_certificate(const int32_t name, uint32_t *cert_addr);
-#define RCAR_IMAGE_ID_MAX (10)
-#define RCAR_CERT_MAGIC_NUM (0xE291F358U)
+#define RCAR_IMAGE_ID_MAX (10)
+#define RCAR_CERT_MAGIC_NUM (0xE291F358U)
#define RCAR_BOOT_KEY_CERT (0xE6300C00U)
#define RCAR_BOOT_KEY_CERT_NEW (0xE6300F00U)
-#define RST_BASE (0xE6160000U)
-#define RST_MODEMR (RST_BASE + 0x0060U)
-#define MFISOFTMDR (0xE6260600U)
-#define MODEMR_MD5_MASK (0x00000020U)
-#define MODEMR_MD5_SHIFT (5U)
-#define SOFTMD_BOOTMODE_MASK (0x00000001U)
-#define SOFTMD_NORMALBOOT (0x1U)
+#define RST_BASE (0xE6160000U)
+#define RST_MODEMR (RST_BASE + 0x0060U)
+#define MFISOFTMDR (0xE6260600U)
+#define MODEMR_MD5_MASK (0x00000020U)
+#define MODEMR_MD5_SHIFT (5U)
+#define SOFTMD_BOOTMODE_MASK (0x00000001U)
+#define SOFTMD_NORMALBOOT (0x1U)
static secure_boot_api_f secure_boot_api;
@@ -125,9 +124,9 @@ verify_image:
#if RCAR_BL2_DCACHE == 1
/* enable */
write_sctlr_el3(read_sctlr_el3() | SCTLR_C_BIT);
-#endif
+#endif /* RCAR_BL2_DCACHE */
-#endif
+#endif /* IMAGE_BL2 */
return ret;
}
diff --git a/drivers/renesas/rcar/avs/avs_driver.c b/drivers/renesas/common/avs/avs_driver.c
index 647869ede4..2c939cd59a 100644
--- a/drivers/renesas/rcar/avs/avs_driver.c
+++ b/drivers/renesas/common/avs/avs_driver.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,8 +8,8 @@
#include <lib/mmio.h>
#include <lib/utils_def.h>
-#include "cpg_registers.h"
#include "avs_driver.h"
+#include "cpg_registers.h"
#include "rcar_def.h"
#include "rcar_private.h"
@@ -22,12 +22,12 @@
#endif /* PMIC_ROHM_BD9571 */
/* Base address of Adaptive Voltage Scaling module registers*/
-#define AVS_BASE (0xE60A0000U)
+#define AVS_BASE (0xE60A0000U)
/* Adaptive Dynamic Voltage ADJust Parameter2 registers */
-#define ADVADJP2 (AVS_BASE + 0x013CU)
+#define ADVADJP2 (AVS_BASE + 0x013CU)
/* Mask VOLCOND bit in ADVADJP2 registers */
-#define ADVADJP2_VOLCOND_MASK (0x000001FFU) /* VOLCOND[8:0] */
+#define ADVADJP2_VOLCOND_MASK (0x000001FFU) /* VOLCOND[8:0] */
#if PMIC_ROHM_BD9571
/* I2C for DVFS bit in CPG registers for module standby and software reset*/
@@ -38,19 +38,19 @@
#if PMIC_ROHM_BD9571
/* Base address of IICDVFS registers*/
-#define IIC_DVFS_BASE (0xE60B0000U)
+#define IIC_DVFS_BASE (0xE60B0000U)
/* IIC bus data register */
-#define IIC_ICDR (IIC_DVFS_BASE + 0x0000U)
+#define IIC_ICDR (IIC_DVFS_BASE + 0x0000U)
/* IIC bus control register */
-#define IIC_ICCR (IIC_DVFS_BASE + 0x0004U)
+#define IIC_ICCR (IIC_DVFS_BASE + 0x0004U)
/* IIC bus status register */
-#define IIC_ICSR (IIC_DVFS_BASE + 0x0008U)
+#define IIC_ICSR (IIC_DVFS_BASE + 0x0008U)
/* IIC interrupt control register */
-#define IIC_ICIC (IIC_DVFS_BASE + 0x000CU)
+#define IIC_ICIC (IIC_DVFS_BASE + 0x000CU)
/* IIC clock control register low */
-#define IIC_ICCL (IIC_DVFS_BASE + 0x0010U)
+#define IIC_ICCL (IIC_DVFS_BASE + 0x0010U)
/* IIC clock control register high */
-#define IIC_ICCH (IIC_DVFS_BASE + 0x0014U)
+#define IIC_ICCH (IIC_DVFS_BASE + 0x0014U)
/* Bit in ICSR register */
#define ICSR_BUSY (0x10U)
@@ -76,20 +76,23 @@
#define ICCR_STOP_RECV (0xC0U)
/* Low-level period of SCL */
-#define ICCL_FREQ_8p33M (0x07U) /* for CP Phy 8.3333MHz */
-#define ICCL_FREQ_10M (0x09U) /* for CP Phy 10MHz */
-#define ICCL_FREQ_12p5M (0x0BU) /* for CP Phy 12.5MHz */
-#define ICCL_FREQ_16p66M (0x0EU) /* for CP Phy 16.6666MHz */
+#define ICCL_FREQ_8p33M (0x07U) /* for CP Phy 8.3333MHz */
+#define ICCL_FREQ_10M (0x09U) /* for CP Phy 10MHz */
+#define ICCL_FREQ_12p5M (0x0BU) /* for CP Phy 12.5MHz */
+#define ICCL_FREQ_16p66M (0x0EU) /* for CP Phy 16.6666MHz */
/* High-level period of SCL */
-#define ICCH_FREQ_8p33M (0x01U) /* for CP Phy 8.3333MHz */
-#define ICCH_FREQ_10M (0x02U) /* for CP Phy 10MHz */
-#define ICCH_FREQ_12p5M (0x03U) /* for CP Phy 12.5MHz */
-#define ICCH_FREQ_16p66M (0x05U) /* for CP Phy 16.6666MHz */
+#define ICCH_FREQ_8p33M (0x01U) /* for CP Phy 8.3333MHz */
+#define ICCH_FREQ_10M (0x02U) /* for CP Phy 10MHz */
+#define ICCH_FREQ_12p5M (0x03U) /* for CP Phy 12.5MHz */
+#define ICCH_FREQ_16p66M (0x05U) /* for CP Phy 16.6666MHz */
/* PMIC */
-#define PMIC_W_SLAVE_ADDRESS (0x60U) /* ROHM BD9571 slave address + (W) */
-#define PMIC_R_SLAVE_ADDRESS (0x61U) /* ROHM BD9571 slave address + (R) */
-#define PMIC_DVFS_SETVID (0x54U) /* ROHM BD9571 DVFS SetVID register */
+/* ROHM BD9571 slave address + (W) */
+#define PMIC_W_SLAVE_ADDRESS (0x60U)
+/* ROHM BD9571 slave address + (R) */
+#define PMIC_R_SLAVE_ADDRESS (0x61U)
+/* ROHM BD9571 DVFS SetVID register */
+#define PMIC_DVFS_SETVID (0x54U)
#endif /* PMIC_ROHM_BD9571 */
/* Individual information */
@@ -102,7 +105,7 @@ typedef struct {
} initial_voltage_t;
static const initial_voltage_t init_vol_tbl[] = {
- /* AVS code, RHOM BD9571 DVFS SetVID register */
+ /* AVS code, ROHM BD9571 DVFS SetVID register */
{0x00U, 0x53U}, /* AVS0, 0.83V */
{0x01U, 0x52U}, /* AVS1, 0.82V */
{0x02U, 0x51U}, /* AVS2, 0.81V */
@@ -188,7 +191,7 @@ void rcar_avs_init(void)
/* Disable I2C module and All internal registers initialized. */
mmio_write_8(IIC_ICCR, 0x00U);
while ((mmio_read_8(IIC_ICCR) & ICCR_ENABLE) != 0U) {
- /* Disable I2C module and All internal registers initialized. */
+ /* Disable I2C module and all internal registers initialized. */
mmio_write_8(IIC_ICCR, 0x00U);
}
@@ -283,8 +286,8 @@ void rcar_avs_setting(void)
/* Dose efuse_avs exceed the number of */
/* the tables? */
if (efuse_avs >= EFUSE_AVS_NUM) {
- ERROR("AVS number of eFuse is out "
- "of a range. number=%u\n",
+ ERROR("%s%s=%u\n", "AVS number of ",
+ "eFuse is out of range. number",
efuse_avs);
/* Infinite loop */
panic();
@@ -417,7 +420,8 @@ void rcar_avs_end(void)
{
uint8_t addr = PMIC_DVFS_SETVID;
uint8_t value = avs_read_pmic_reg(addr);
- NOTICE("Read PMIC register. address=0x%x value=0x%x \n",
+
+ NOTICE("Read PMIC register. address=0x%x value=0x%x\n",
addr, value);
}
#endif
@@ -446,8 +450,8 @@ static avs_error_t avs_check_error(void)
avs_error_t ret;
if ((mmio_read_8(IIC_ICSR) & ICSR_AL) == ICSR_AL) {
- NOTICE("Loss of arbitration is detected. "
- "AVS status=%d Retry=%u\n", avs_status, avs_retry);
+ NOTICE("%s AVS status=%d Retry=%u\n",
+ "Loss of arbitration is detected.", avs_status, avs_retry);
/* Check of retry number of times */
if (avs_retry >= AVS_RETRY_NUM) {
ERROR("AVS setting failed in retry. max=%u\n",
@@ -458,8 +462,8 @@ static avs_error_t avs_check_error(void)
/* Set the error detected to error status. */
ret = avs_error_al;
} else if ((mmio_read_8(IIC_ICSR) & ICSR_TACK) == ICSR_TACK) {
- NOTICE("Non-acknowledge is detected. "
- "AVS status=%d Retry=%u\n", avs_status, avs_retry);
+ NOTICE("%s AVS status=%d Retry=%u\n",
+ "Non-acknowledge is detected.", avs_status, avs_retry);
/* Check of retry number of times */
if (avs_retry >= AVS_RETRY_NUM) {
ERROR("AVS setting failed in retry. max=%u\n",
@@ -526,8 +530,10 @@ static uint8_t avs_read_pmic_reg(uint8_t addr)
/* Set frequency of 400kHz */
avs_set_iic_clock();
- /* Set ICIC.WAITE=1, ICIC.DTEE=1 to enable data transmission */
- /* interrupt and wait interrupt. */
+ /*
+ * Set ICIC.WAITE=1, ICIC.DTEE=1 to enable data transmission
+ * interrupt and wait interrupt.
+ */
mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) | ICIC_WAITE | ICIC_DTEE);
/* Write H'94 in ICCR to issue start condition */
diff --git a/drivers/renesas/rcar/avs/avs_driver.h b/drivers/renesas/common/avs/avs_driver.h
index aa773b6041..aa773b6041 100644
--- a/drivers/renesas/rcar/avs/avs_driver.h
+++ b/drivers/renesas/common/avs/avs_driver.h
diff --git a/drivers/renesas/common/common.c b/drivers/renesas/common/common.c
new file mode 100644
index 0000000000..9b7c1eb16c
--- /dev/null
+++ b/drivers/renesas/common/common.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+
+#include "rcar_private.h"
+
+#if IMAGE_BL31
+void __attribute__ ((section(".system_ram"))) cpg_write(uintptr_t regadr, uint32_t regval)
+#else
+void cpg_write(uintptr_t regadr, uint32_t regval)
+#endif
+{
+ uint32_t value = regval;
+
+ mmio_write_32((uintptr_t) RCAR_CPGWPR, ~value);
+ mmio_write_32(regadr, value);
+}
+
+#if IMAGE_BL31
+void __attribute__ ((section(".system_ram"))) mstpcr_write(uint32_t mstpcr, uint32_t mstpsr,
+ uint32_t target_bit)
+#else
+void mstpcr_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t target_bit)
+#endif
+{
+ uint32_t reg;
+
+ reg = mmio_read_32(mstpcr);
+ reg &= ~target_bit;
+ cpg_write(mstpcr, reg);
+ while ((mmio_read_32(mstpsr) & target_bit) != 0U) {
+ }
+}
diff --git a/drivers/renesas/rcar/console/rcar_console.S b/drivers/renesas/common/console/rcar_console.S
index 29baa67a4a..29baa67a4a 100644
--- a/drivers/renesas/rcar/console/rcar_console.S
+++ b/drivers/renesas/common/console/rcar_console.S
diff --git a/drivers/renesas/rcar/console/rcar_printf.c b/drivers/renesas/common/console/rcar_printf.c
index e75b9f4541..ad074fe059 100644
--- a/drivers/renesas/rcar/console/rcar_printf.c
+++ b/drivers/renesas/common/console/rcar_printf.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,11 +19,22 @@
#define INDEX_TIMER_COUNT (4U)
+#define RCAR_LOG_HEAD (('T' << 0) | ('L' << 8) | ('O' << 16) | ('G' << 24))
+
+/*
+ * The log is initialized and used before BL31 xlat tables are initialized,
+ * therefore the log memory is a device memory at that point. Make sure the
+ * memory is correclty aligned and accessed only with up-to 32bit, aligned,
+ * writes.
+ */
+CASSERT((RCAR_BL31_LOG_BASE & 0x7) == 0, assert_bl31_log_base_unaligned);
+CASSERT((RCAR_BL31_LOG_MAX & 0x7) == 0, assert_bl31_log_max_unaligned);
+
extern RCAR_INSTANTIATE_LOCK typedef struct log_head {
- uint8_t head[4];
+ uint32_t head;
uint32_t index;
uint32_t size;
- uint8_t res[4];
+ uint32_t res;
} loghead_t;
typedef struct log_map {
@@ -66,15 +77,12 @@ int32_t rcar_set_log_data(int32_t c)
int32_t rcar_log_init(void)
{
-
- static const uint8_t const_header[] = "TLOG";
- logmap_t *t_log;
+ logmap_t *t_log = (logmap_t *)RCAR_BL31_LOG_BASE;
+ uint32_t *log_data = (uint32_t *)t_log->log_data;
int16_t init_flag = 0;
+ int i;
- t_log = (logmap_t *) RCAR_BL31_LOG_BASE;
- if (memcmp
- ((const void *)t_log->header.head, (const void *)const_header,
- sizeof(t_log->header.head)) != 0) {
+ if (t_log->header.head != RCAR_LOG_HEAD) {
/*
* Log header is not "TLOG", then log area initialize
*/
@@ -87,11 +95,10 @@ int32_t rcar_log_init(void)
init_flag = 1;
}
if (init_flag == 1) {
- (void)memset((void *)t_log->log_data, 0,
- (size_t) RCAR_BL31_LOG_MAX);
- (void)memcpy((void *)t_log->header.head,
- (const void *)const_header,
- sizeof(t_log->header.head));
+ for (i = 0; i < RCAR_BL31_LOG_MAX; i += 4)
+ *log_data++ = 0;
+
+ t_log->header.head = RCAR_LOG_HEAD;
t_log->header.index = 0U;
t_log->header.size = 0U;
}
diff --git a/drivers/renesas/rcar/console/rcar_printf.h b/drivers/renesas/common/console/rcar_printf.h
index 5da70e6365..5da70e6365 100644
--- a/drivers/renesas/rcar/console/rcar_printf.h
+++ b/drivers/renesas/common/console/rcar_printf.h
diff --git a/drivers/renesas/rcar/ddr/ddr_regs.h b/drivers/renesas/common/ddr_regs.h
index ba26c69c8b..ba26c69c8b 100644
--- a/drivers/renesas/rcar/ddr/ddr_regs.h
+++ b/drivers/renesas/common/ddr_regs.h
diff --git a/drivers/renesas/rcar/delay/micro_delay.c b/drivers/renesas/common/delay/micro_delay.c
index aced5891a8..a5e2a69285 100644
--- a/drivers/renesas/rcar/delay/micro_delay.c
+++ b/drivers/renesas/common/delay/micro_delay.c
@@ -1,18 +1,19 @@
/*
- * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <arch_helpers.h>
+
#include "micro_delay.h"
#define RCAR_CONV_MICROSEC 1000000U
void
#if IMAGE_BL31
- __attribute__ ((section (".system_ram")))
+ __attribute__ ((section(".system_ram")))
#endif
rcar_micro_delay(uint64_t micro_sec)
{
diff --git a/drivers/renesas/rcar/delay/micro_delay.h b/drivers/renesas/common/delay/micro_delay.h
index 37b71f80a6..37b71f80a6 100644
--- a/drivers/renesas/rcar/delay/micro_delay.h
+++ b/drivers/renesas/common/delay/micro_delay.h
diff --git a/drivers/renesas/rcar/dma/dma_driver.c b/drivers/renesas/common/dma/dma_driver.c
index e0be46e6f9..44ee985923 100644
--- a/drivers/renesas/rcar/dma/dma_driver.c
+++ b/drivers/renesas/common/dma/dma_driver.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,15 +11,15 @@
#include <common/debug.h>
#include <lib/mmio.h>
-#include "rcar_def.h"
#include "cpg_registers.h"
+#include "rcar_def.h"
#include "rcar_private.h"
/* DMA CHANNEL setting (0/16/32) */
#if RCAR_LSI == RCAR_V3M
-#define DMA_CH 16
+#define DMA_CH 16
#else
-#define DMA_CH 0
+#define DMA_CH 0
#endif
#if (DMA_CH == 0)
@@ -39,7 +39,7 @@
/* DMA operation */
#define DMA_DMAOR (DMA_BASE + 0x0060U)
/* DMA secure control */
-#define DMA_DMASEC (DMA_BASE + 0x0030U)
+#define DMA_DMASEC (DMA_BASE + 0x0030U)
/* DMA channel clear */
#define DMA_DMACHCLR (DMA_BASE + 0x0080U)
/* DMA source address */
@@ -53,21 +53,21 @@
/* DMA fixed destination address */
#define DMA_DMAFIXDAR (DMA_BASE + 0x8014U)
-#define DMA_USE_CHANNEL (0x00000001U)
-#define DMAOR_INITIAL (0x0301U)
-#define DMACHCLR_CH_ALL (0x0000FFFFU)
-#define DMAFIXDAR_32BIT_SHIFT (32U)
-#define DMAFIXDAR_DAR_MASK (0x000000FFU)
-#define DMADAR_BOUNDARY_ADDR (0x100000000ULL)
-#define DMATCR_CNT_SHIFT (6U)
-#define DMATCR_MAX (0x00FFFFFFU)
-#define DMACHCR_TRN_MODE (0x00105409U)
-#define DMACHCR_DE_BIT (0x00000001U)
-#define DMACHCR_TE_BIT (0x00000002U)
-#define DMACHCR_CHE_BIT (0x80000000U)
-
-#define DMA_SIZE_UNIT FLASH_TRANS_SIZE_UNIT
-#define DMA_FRACTION_MASK (0xFFU)
+#define DMA_USE_CHANNEL (0x00000001U)
+#define DMAOR_INITIAL (0x0301U)
+#define DMACHCLR_CH_ALL (0x0000FFFFU)
+#define DMAFIXDAR_32BIT_SHIFT (32U)
+#define DMAFIXDAR_DAR_MASK (0x000000FFU)
+#define DMADAR_BOUNDARY_ADDR (0x100000000ULL)
+#define DMATCR_CNT_SHIFT (6U)
+#define DMATCR_MAX (0x00FFFFFFU)
+#define DMACHCR_TRN_MODE (0x00105409U)
+#define DMACHCR_DE_BIT (0x00000001U)
+#define DMACHCR_TE_BIT (0x00000002U)
+#define DMACHCR_CHE_BIT (0x80000000U)
+
+#define DMA_SIZE_UNIT FLASH_TRANS_SIZE_UNIT
+#define DMA_FRACTION_MASK (0xFFU)
#define DMA_DST_LIMIT (0x10000000000ULL)
/* transfer length limit */
@@ -129,16 +129,16 @@ void rcar_dma_exec(uintptr_t dst, uint32_t src, uint32_t len)
}
if (src & DMA_FRACTION_MASK) {
- ERROR("BL2: DMA - source address invalid (0x%x), "
- "length (0x%x)\n", src, dma_len);
+ ERROR("BL2: DMA - src address invalid (0x%x), len=(0x%x)\n",
+ src, dma_len);
panic();
}
if ((dst & UINT32_MAX) + dma_len > DMADAR_BOUNDARY_ADDR ||
- (dst + dma_len > DMA_DST_LIMIT) ||
+ (dst + dma_len > DMA_DST_LIMIT) ||
(dst & DMA_FRACTION_MASK)) {
- ERROR("BL2: DMA - destination address invalid (0x%lx), "
- "length (0x%x)\n", dst, dma_len);
+ ERROR("BL2: DMA - dest address invalid (0x%lx), len=(0x%x)\n",
+ dst, dma_len);
panic();
}
diff --git a/drivers/renesas/rcar/emmc/emmc_cmd.c b/drivers/renesas/common/emmc/emmc_cmd.c
index a2e25e3394..d255bffc9f 100644
--- a/drivers/renesas/rcar/emmc/emmc_cmd.c
+++ b/drivers/renesas/common/emmc/emmc_cmd.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,10 +7,10 @@
#include <common/debug.h>
#include "emmc_config.h"
+#include "emmc_def.h"
#include "emmc_hal.h"
-#include "emmc_std.h"
#include "emmc_registers.h"
-#include "emmc_def.h"
+#include "emmc_std.h"
#include "micro_delay.h"
static void emmc_little_to_big(uint8_t *p, uint32_t value)
@@ -22,6 +22,7 @@ static void emmc_little_to_big(uint8_t *p, uint32_t value)
p[1] = (uint8_t) (value >> 16);
p[2] = (uint8_t) (value >> 8);
p[3] = (uint8_t) value;
+
}
static void emmc_softreset(void)
@@ -64,7 +65,6 @@ reset:
SETR_32(SD_INFO2, SD_INFO2_CLEAR);
SETR_32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */
SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */
-
}
static void emmc_read_response(uint32_t *response)
@@ -96,8 +96,7 @@ static EMMC_ERROR_CODE emmc_response_check(uint32_t *response,
{
HAL_MEMCARD_RESPONSE_TYPE response_type =
- (HAL_MEMCARD_RESPONSE_TYPE) (mmc_drv_obj.cmd_info.
- cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK);
+ ((HAL_MEMCARD_RESPONSE_TYPE)mmc_drv_obj.cmd_info.cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK);
if (response == NULL)
return EMMC_ERR_PARAM;
@@ -117,7 +116,7 @@ static EMMC_ERROR_CODE emmc_response_check(uint32_t *response,
}
return EMMC_ERR_CARD_STATUS_BIT;
}
- return EMMC_SUCCESS;;
+ return EMMC_SUCCESS;
}
if (response_type == HAL_MEMCARD_RESPONSE_R4) {
@@ -223,11 +222,11 @@ EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response)
state = ESTATE_BEGIN;
response_type =
- (HAL_MEMCARD_RESPONSE_TYPE) (mmc_drv_obj.cmd_info.
- cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK);
+ ((HAL_MEMCARD_RESPONSE_TYPE)mmc_drv_obj.cmd_info.cmd &
+ HAL_MEMCARD_RESPONSE_TYPE_MASK);
cmd_type =
- (HAL_MEMCARD_COMMAND_TYPE) (mmc_drv_obj.cmd_info.
- cmd & HAL_MEMCARD_COMMAND_TYPE_MASK);
+ ((HAL_MEMCARD_COMMAND_TYPE) mmc_drv_obj.cmd_info.cmd &
+ HAL_MEMCARD_COMMAND_TYPE_MASK);
/* state machine */
while ((mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END)) {
@@ -427,8 +426,9 @@ EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response)
case ESTATE_ACCESS_END:
/* clear flag */
- if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) {
- SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+ if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) {
+ /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+ SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR);
SETR_32(SD_STOP, 0x00000000U);
mmc_drv_obj.during_dma_transfer = FALSE;
}
@@ -448,8 +448,9 @@ EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response)
case ESTATE_TRANSFER_ERROR:
/* The error occurred in the Data transfer. */
- if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) {
- SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+ if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) {
+ /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+ SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR);
SETR_32(SD_STOP, 0x00000000U);
mmc_drv_obj.during_dma_transfer = FALSE;
}
@@ -468,8 +469,8 @@ EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response)
default:
state = ESTATE_END;
break;
- } /* switch (state) */
- } /* while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) */
+ } /* switch (state) */
+ } /* while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) */
/* force terminate */
if (mmc_drv_obj.force_terminate == TRUE) {
@@ -481,7 +482,7 @@ EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response)
ERROR("BL2: emmc exec_cmd:EMMC_ERR_FORCE_TERMINATE\n");
emmc_softreset();
- return EMMC_ERR_FORCE_TERMINATE; /* error information has already been written. */
+ return EMMC_ERR_FORCE_TERMINATE; /* error information has already been written. */
}
/* success */
diff --git a/drivers/renesas/common/emmc/emmc_config.h b/drivers/renesas/common/emmc/emmc_config.h
new file mode 100644
index 0000000000..16b6b8aa9a
--- /dev/null
+++ b/drivers/renesas/common/emmc/emmc_config.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef EMMC_CONFIG_H
+#define EMMC_CONFIG_H
+
+/* RCA */
+#define EMMC_RCA 1UL
+/* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */
+#define EMMC_RW_DATA_TIMEOUT 0x40UL
+/* how many times to try after fail. Don't change. */
+#define EMMC_RETRY_COUNT 0
+#define EMMC_CMD_MAX 60UL /* Don't change. */
+
+#define LOADIMAGE_FLAGS_DMA_ENABLE 0x00000001UL
+
+#endif /* EMMC_CONFIG_H */
diff --git a/drivers/renesas/rcar/emmc/emmc_def.h b/drivers/renesas/common/emmc/emmc_def.h
index 178c795b98..178c795b98 100644
--- a/drivers/renesas/rcar/emmc/emmc_def.h
+++ b/drivers/renesas/common/emmc/emmc_def.h
diff --git a/drivers/renesas/common/emmc/emmc_hal.h b/drivers/renesas/common/emmc/emmc_hal.h
new file mode 100644
index 0000000000..0a8551719f
--- /dev/null
+++ b/drivers/renesas/common/emmc/emmc_hal.h
@@ -0,0 +1,535 @@
+/*
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef EMMC_HAL_H
+#define EMMC_HAL_H
+
+/* memory card error/status types */
+#define HAL_MEMCARD_OUT_OF_RANGE 0x80000000L
+#define HAL_MEMCARD_ADDRESS_ERROR 0x40000000L
+#define HAL_MEMCARD_BLOCK_LEN_ERROR 0x20000000L
+#define HAL_MEMCARD_ERASE_SEQ_ERROR 0x10000000L
+#define HAL_MEMCARD_ERASE_PARAM 0x08000000L
+#define HAL_MEMCARD_WP_VIOLATION 0x04000000L
+#define HAL_MEMCARD_CARD_IS_LOCKED 0x02000000L
+#define HAL_MEMCARD_LOCK_UNLOCK_FAILED 0x01000000L
+#define HAL_MEMCARD_COM_CRC_ERROR 0x00800000L
+#define HAL_MEMCARD_ILEGAL_COMMAND 0x00400000L
+#define HAL_MEMCARD_CARD_ECC_FAILED 0x00200000L
+#define HAL_MEMCARD_CC_ERROR 0x00100000L
+#define HAL_MEMCARD_ERROR 0x00080000L
+#define HAL_MEMCARD_UNDERRUN 0x00040000L
+#define HAL_MEMCARD_OVERRUN 0x00020000L
+#define HAL_MEMCARD_CIDCSD_OVERWRITE 0x00010000L
+#define HAL_MEMCARD_WP_ERASE_SKIP 0x00008000L
+#define HAL_MEMCARD_CARD_ECC_DISABLED 0x00004000L
+#define HAL_MEMCARD_ERASE_RESET 0x00002000L
+#define HAL_MEMCARD_CARD_STATE 0x00001E00L
+#define HAL_MEMCARD_CARD_READY_FOR_DATA 0x00000100L
+#define HAL_MEMCARD_APP_CMD 0x00000020L
+#define HAL_MEMCARD_SWITCH_ERROR 0x00000080L
+#define HAL_MEMCARD_AKE_SEQ_ERROR 0x00000008L
+#define HAL_MEMCARD_NO_ERRORS 0x00000000L
+
+/* Memory card response types */
+#define HAL_MEMCARD_COMMAND_INDEX_MASK 0x0003f
+
+/* Type of the return value. */
+typedef enum {
+ HAL_MEMCARD_FAIL = 0U,
+ HAL_MEMCARD_OK = 1U,
+ HAL_MEMCARD_DMA_ALLOC_FAIL = 2U, /* DMA channel allocation failed */
+ HAL_MEMCARD_DMA_TRANSFER_FAIL = 3U, /* DMA transfer failed */
+ HAL_MEMCARD_CARD_STATUS_ERROR = 4U, /* card status non-masked error */
+ HAL_MEMCARD_CMD_TIMEOUT = 5U, /* Command timeout occurred */
+ HAL_MEMCARD_DATA_TIMEOUT = 6U, /* Data timeout occurred */
+ HAL_MEMCARD_CMD_CRC_ERROR = 7U, /* Command CRC error occurred */
+ HAL_MEMCARD_DATA_CRC_ERROR = 8U /* Data CRC error occurred */
+} HAL_MEMCARD_RETURN;
+
+/* memory access operation */
+typedef enum {
+ HAL_MEMCARD_READ = 0U, /* read */
+ HAL_MEMCARD_WRITE = 1U /* write */
+} HAL_MEMCARD_OPERATION;
+
+/* Type of data width on memorycard bus */
+typedef enum {
+ HAL_MEMCARD_DATA_WIDTH_1_BIT = 0U,
+ HAL_MEMCARD_DATA_WIDTH_4_BIT = 1U,
+ HAL_MEMCARD_DATA_WIDTH_8_BIT = 2U
+} HAL_MEMCARD_DATA_WIDTH; /* data (bus) width types */
+
+/* Presence of the memory card */
+typedef enum {
+ HAL_MEMCARD_CARD_IS_IN = 0U,
+ HAL_MEMCARD_CARD_IS_OUT = 1U
+} HAL_MEMCARD_PRESENCE_STATUS; /* presence status of the memory card */
+
+/* mode of data transfer */
+typedef enum {
+ HAL_MEMCARD_DMA = 0U,
+ HAL_MEMCARD_NOT_DMA = 1U
+} HAL_MEMCARD_DATA_TRANSFER_MODE;
+
+/* Memory card response types. */
+typedef enum hal_memcard_response_type {
+ HAL_MEMCARD_RESPONSE_NONE = 0x00000U,
+ HAL_MEMCARD_RESPONSE_R1 = 0x00100U,
+ HAL_MEMCARD_RESPONSE_R1b = 0x00200U,
+ HAL_MEMCARD_RESPONSE_R2 = 0x00300U,
+ HAL_MEMCARD_RESPONSE_R3 = 0x00400U,
+ HAL_MEMCARD_RESPONSE_R4 = 0x00500U,
+ HAL_MEMCARD_RESPONSE_R5 = 0x00600U,
+ HAL_MEMCARD_RESPONSE_R6 = 0x00700U,
+ HAL_MEMCARD_RESPONSE_R7 = 0x00800U,
+ HAL_MEMCARD_RESPONSE_TYPE_MASK = 0x00f00U
+} HAL_MEMCARD_RESPONSE_TYPE;
+
+/* Memory card command types. */
+typedef enum hal_memcard_command_type {
+ HAL_MEMCARD_COMMAND_TYPE_BC = 0x00000U,
+ HAL_MEMCARD_COMMAND_TYPE_BCR = 0x01000U,
+ HAL_MEMCARD_COMMAND_TYPE_AC = 0x02000U,
+ HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE = 0x03000U,
+ HAL_MEMCARD_COMMAND_TYPE_ADTC_READ = 0x04000U,
+ HAL_MEMCARD_COMMAND_TYPE_MASK = 0x07000U
+} HAL_MEMCARD_COMMAND_TYPE;
+
+/* Type of memory card */
+typedef enum hal_memcard_command_card_type {
+ HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON = 0x00000U,
+ HAL_MEMCARD_COMMAND_CARD_TYPE_MMC = 0x08000U,
+ HAL_MEMCARD_COMMAND_CARD_TYPE_SD = 0x10000U,
+ HAL_MEMCARD_COMMAND_CARD_TYPE_MASK = 0x18000U
+} HAL_MEMCARD_COMMAND_CARD_TYPE;
+
+/* Memory card application command. */
+typedef enum hal_memcard_command_app_norm {
+ HAL_MEMCARD_COMMAND_NORMAL = 0x00000U,
+ HAL_MEMCARD_COMMAND_APP = 0x20000U,
+ HAL_MEMCARD_COMMAND_APP_NORM_MASK = 0x20000U
+} HAL_MEMCARD_COMMAND_APP_NORM;
+
+/* Memory card command codes. */
+typedef enum {
+/* class 0 and class 1 */
+ /* CMD0 */
+ CMD0_GO_IDLE_STATE =
+ 0U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BC |
+ (uint32_t) HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD1 */
+ CMD1_SEND_OP_COND =
+ 1U | (uint32_t)HAL_MEMCARD_RESPONSE_R3 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD2 */
+ CMD2_ALL_SEND_CID_MMC =
+ 2U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ CMD2_ALL_SEND_CID_SD =
+ 2U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD3 */
+ CMD3_SET_RELATIVE_ADDR =
+ 3U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ CMD3_SEND_RELATIVE_ADDR =
+ 3U | (uint32_t)HAL_MEMCARD_RESPONSE_R6 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD4 */
+ CMD4_SET_DSR =
+ 4U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD5 */
+ CMD5_SLEEP_AWAKE =
+ 5U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD6 */
+ CMD6_SWITCH =
+ 6U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ CMD6_SWITCH_FUNC =
+ 6U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ ACMD6_SET_BUS_WIDTH =
+ 6U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+ /* CMD7 */
+ CMD7_SELECT_CARD =
+ 7U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD7(from Disconnected State to Programming State) */
+ CMD7_SELECT_CARD_PROG =
+ 7U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ CMD7_DESELECT_CARD =
+ 7U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD8 */
+ CMD8_SEND_EXT_CSD =
+ 8U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ CMD8_SEND_IF_COND =
+ 8U | (uint32_t)HAL_MEMCARD_RESPONSE_R7 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD9 */
+ CMD9_SEND_CSD =
+ 9U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD10 */
+ CMD10_SEND_CID =
+ 10U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD11 */
+ CMD11_READ_DAT_UNTIL_STOP =
+ 11U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD12 */
+ CMD12_STOP_TRANSMISSION =
+ 12U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD12(R1b : write case) */
+ CMD12_STOP_TRANSMISSION_WRITE =
+ 12U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD13 */
+ CMD13_SEND_STATUS =
+ 13U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ ACMD13_SD_STATUS =
+ 13U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+ /* CMD14 */
+ CMD14_BUSTEST_R =
+ 14U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD15 */
+ CMD15_GO_INACTIVE_STATE =
+ 15U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+
+/* class 2 */
+ /* CMD16 */
+ CMD16_SET_BLOCKLEN =
+ 16U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD17 */
+ CMD17_READ_SINGLE_BLOCK =
+ 17U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD18 */
+ CMD18_READ_MULTIPLE_BLOCK =
+ 18U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD19 */
+ CMD19_BUS_TEST_W =
+ 19U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+
+/* class 3 */
+ /* CMD20 */
+ CMD20_WRITE_DAT_UNTIL_STOP =
+ 20U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD21 */
+ CMD21 = 21U,
+ /* CMD22 */
+ CMD22 = 22U,
+ ACMD22_SEND_NUM_WR_BLOCKS =
+ 22U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+
+/* class 4 */
+ /* CMD23 */
+ CMD23_SET_BLOCK_COUNT =
+ 23U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ ACMD23_SET_WR_BLK_ERASE_COUNT =
+ 23U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+ /* CMD24 */
+ CMD24_WRITE_BLOCK =
+ 24U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD25 */
+ CMD25_WRITE_MULTIPLE_BLOCK =
+ 25U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD26 */
+ CMD26_PROGRAM_CID =
+ 26U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD27 */
+ CMD27_PROGRAM_CSD =
+ 27U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+
+/* class 6 */
+ /* CMD28 */
+ CMD28_SET_WRITE_PROT =
+ 28U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD29 */
+ CMD29_CLR_WRITE_PROT =
+ 29U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD30 */
+ CMD30_SEND_WRITE_PROT =
+ 30U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD31 */
+ CMD30_SEND_WRITE_PROT_TYPE =
+ 31U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+
+/* class 5 */
+ /* CMD32 */
+ CMD32_ERASE_WR_BLK_START =
+ 32U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD33 */
+ CMD33_ERASE_WR_BLK_END =
+ 33U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD34 */
+ CMD34 = 34U,
+ /* CMD35 */
+ CMD35_ERASE_GROUP_START =
+ 35U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD36 */
+ CMD36_ERASE_GROUP_END =
+ 36U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD37 */
+ CMD37 = 37U,
+ /* CMD38 */
+ CMD38_ERASE =
+ 38U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+
+/* class 9 */
+ /* CMD39 */
+ CMD39_FASTIO =
+ 39U | (uint32_t)HAL_MEMCARD_RESPONSE_R4 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD40 */
+ CMD40_GO_IRQSTATE =
+ 40U | (uint32_t)HAL_MEMCARD_RESPONSE_R5 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD41 */
+ CMD41 = 41,
+ ACMD41_SD_SEND_OP_COND =
+ 41U | (uint32_t)HAL_MEMCARD_RESPONSE_R3 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+
+/* class 7 */
+ /* CMD42 */
+ CMD42_LOCK_UNLOCK =
+ 42U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ ACMD42_SET_CLR_CARD_DETECT =
+ 42U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+ CMD43 = 43U, /* CMD43 */
+ CMD44 = 44U, /* CMD44 */
+ CMD45 = 45U, /* CMD45 */
+ CMD46 = 46U, /* CMD46 */
+ CMD47 = 47U, /* CMD47 */
+ CMD48 = 48U, /* CMD48 */
+ CMD49 = 49U, /* CMD49 */
+ CMD50 = 50U, /* CMD50 */
+ CMD51 = 51U, /* CMD51 */
+ ACMD51_SEND_SCR =
+ 51U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+ CMD52 = 52U, /* CMD52 */
+ CMD53 = 53U, /* CMD53 */
+ CMD54 = 54U, /* CMD54 */
+
+/* class 8 */
+ /* CMD55 */
+ CMD55_APP_CMD =
+ 55U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD56 */
+ CMD56_GEN_CMD =
+ 56U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ CMD57 = 57U, /* CMD57 */
+ CMD58 = 58U, /* CMD58 */
+ CMD59 = 59U, /* CMD59 */
+ CMD60 = 60U, /* CMD60 */
+ CMD61 = 61U, /* CMD61 */
+ CMD62 = 62U, /* CMD62 */
+ CMD63 = 63U /* CMD63 */
+} HAL_MEMCARD_COMMAND;
+
+/*
+ * Configuration structure from HAL layer.
+ *
+ * If some field is not available it should be filled with 0xFF.
+ * The API version is 32-bit unsigned integer telling the version of the API.
+ * The integer is divided to four sections which each can be treated as a 8-bit
+ * unsigned number:
+ * Bits 31-24 make the most significant part of the version number. This number
+ * starts from 1 i.e. the second version of the API will be 0x02xxxxxx. This
+ * number changes only, if the API itself changes so much that it is not
+ * compatible anymore with older releases.
+ * Bits 23-16 API minor version number. For example API version 2.1 would be
+ * 0x0201xxxx.
+ * Bits 15-8 are the number of the year when release is done. The 0 is year
+ * 2000, 1 is year 2001 and so on
+ * Bits 7- are the week number when release is done. First full week of the
+ * year is 1
+ *
+ * Example: let's assume that release 2.1 is done on week 10 year 2008
+ * the version will get the value 0x0201080A
+ */
+typedef struct {
+ /*
+ * Version of the chipset API implementation
+ *
+ * bits [31:24] API specification major version number.<br>
+ * bits [23:16] API specification minor version number.<br>
+ * bits [15:8] API implementation year. (2000 = 0, 2001 = 1, ...)
+ * bits [7:0] API implementation week.
+ * Example: API spec version 4.0, implementation w46 2008 => 0x0400082E
+ */
+ uint32_t api_version;
+
+ /* maximum block count which can be transferred at once */
+ uint32_t max_block_count;
+
+ /* maximum clock frequence in Hz supported by HW */
+ uint32_t max_clock_freq;
+
+ /* maximum data bus width supported by HW */
+ uint16_t max_data_width;
+
+ /* Is high-speed mode supported by HW (yes=1, no=0) */
+ uint8_t hs_mode_supported;
+
+ /* Is memory card removable (yes=1, no=0) */
+ uint8_t card_removable;
+
+} HAL_MEMCARD_HW_CONF;
+
+/* Configuration structure to HAL layer. */
+typedef struct {
+ /* how many times to try after fail, for instance sending command */
+ uint32_t retries_after_fail;
+} HAL_MEMCARD_INIT_CONF;
+
+#endif /* EMMC_HAL_H */
diff --git a/drivers/renesas/rcar/emmc/emmc_init.c b/drivers/renesas/common/emmc/emmc_init.c
index b27e165862..354aa3c82a 100644
--- a/drivers/renesas/rcar/emmc/emmc_init.c
+++ b/drivers/renesas/common/emmc/emmc_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -32,12 +32,12 @@ EMMC_ERROR_CODE rcar_emmc_memcard_power(uint8_t mode)
return EMMC_SUCCESS;
}
-static __inline void emmc_set_retry_count(uint32_t retry)
+static inline void emmc_set_retry_count(uint32_t retry)
{
mmc_drv_obj.retries_after_fail = retry;
}
-static __inline void emmc_set_data_timeout(uint32_t data_timeout)
+static inline void emmc_set_data_timeout(uint32_t data_timeout)
{
mmc_drv_obj.data_timeout = data_timeout;
}
@@ -73,7 +73,8 @@ static EMMC_ERROR_CODE emmc_dev_finalize(void)
EMMC_ERROR_CODE result;
uint32_t dataL;
- /* MMC power off
+ /*
+ * MMC power off
* the power supply of eMMC device is always turning on.
* RST_n : Hi --> Low level.
*/
@@ -115,27 +116,25 @@ static EMMC_ERROR_CODE emmc_dev_init(void)
SETR_32(HOST_MODE, 0x00000000U); /* SD_BUF access width = 64-bit */
SETR_32(SD_OPTION, 0x0000C0EEU); /* Bus width = 1bit, timeout=MAX */
- SETR_32(SD_CLK_CTRL, 0x00000000U); /* Automatic Control=Disable, Clock Output=Disable */
+ SETR_32(SD_CLK_CTRL, 0x00000000U); /* Disable Automatic Control & Clock Output */
return EMMC_SUCCESS;
}
static EMMC_ERROR_CODE emmc_reset_controller(void)
{
- EMMC_ERROR_CODE retult;
+ EMMC_ERROR_CODE result;
/* initialize mmc driver */
emmc_drv_init();
/* initialize H/W */
- retult = emmc_dev_init();
- if (EMMC_SUCCESS != retult) {
- return retult;
+ result = emmc_dev_init();
+ if (result == EMMC_SUCCESS) {
+ mmc_drv_obj.initialize = TRUE;
}
- mmc_drv_obj.initialize = TRUE;
-
- return retult;
+ return result;
}
@@ -152,14 +151,12 @@ EMMC_ERROR_CODE emmc_terminate(void)
EMMC_ERROR_CODE rcar_emmc_init(void)
{
- EMMC_ERROR_CODE retult;
+ EMMC_ERROR_CODE result;
- retult = emmc_reset_controller();
- if (EMMC_SUCCESS != retult) {
- return retult;
+ result = emmc_reset_controller();
+ if (result == EMMC_SUCCESS) {
+ emmc_driver_config();
}
- emmc_driver_config();
-
- return EMMC_SUCCESS;
+ return result;
}
diff --git a/drivers/renesas/rcar/emmc/emmc_interrupt.c b/drivers/renesas/common/emmc/emmc_interrupt.c
index 2557280cf6..092fdfb728 100644
--- a/drivers/renesas/rcar/emmc/emmc_interrupt.c
+++ b/drivers/renesas/common/emmc/emmc_interrupt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights
* reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -118,7 +118,7 @@ uint32_t emmc_interrupt(void)
SETR_32(DM_CM_INFO2, 0x00000000U);
/* interrupt clear */
SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BWE));
- /* DM_CM_INFO2: DMA-ch0 error occured */
+ /* DM_CM_INFO2: DMA-ch0 error occurred */
if ((BIT16 & mmc_drv_obj.dm_event2) != 0) {
mmc_drv_obj.dma_error_flag = TRUE;
} else {
@@ -128,13 +128,13 @@ uint32_t emmc_interrupt(void)
/* wait next interrupt */
mmc_drv_obj.state_machine_blocking = FALSE;
}
- /* DM_CM_INFO1: DMA-ch1 transfer complete or error occured */
+ /* DM_CM_INFO1: DMA-ch1 transfer complete or error occurred */
else if ((end_bit & mmc_drv_obj.dm_event1) != 0U) {
SETR_32(DM_CM_INFO1, 0x00000000U);
SETR_32(DM_CM_INFO2, 0x00000000U);
/* interrupt clear */
SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BRE));
- /* DM_CM_INFO2: DMA-ch1 error occured */
+ /* DM_CM_INFO2: DMA-ch1 error occurred */
if ((BIT17 & mmc_drv_obj.dm_event2) != 0) {
mmc_drv_obj.dma_error_flag = TRUE;
} else {
diff --git a/drivers/renesas/rcar/emmc/emmc_mount.c b/drivers/renesas/common/emmc/emmc_mount.c
index df8203ea82..e04afd4cf0 100644
--- a/drivers/renesas/rcar/emmc/emmc_mount.c
+++ b/drivers/renesas/common/emmc/emmc_mount.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,10 +8,10 @@
#include <lib/mmio.h>
#include "emmc_config.h"
+#include "emmc_def.h"
#include "emmc_hal.h"
-#include "emmc_std.h"
#include "emmc_registers.h"
-#include "emmc_def.h"
+#include "emmc_std.h"
#include "micro_delay.h"
#include "rcar_def.h"
@@ -53,7 +53,7 @@ static EMMC_ERROR_CODE emmc_card_init(void)
int32_t retry;
uint32_t freq = MMC_400KHZ; /* 390KHz */
EMMC_ERROR_CODE result;
- uint32_t resultCalc;
+ uint32_t result_calc;
/* state check */
if ((mmc_drv_obj.initialize != TRUE)
@@ -161,9 +161,12 @@ static EMMC_ERROR_CODE emmc_card_init(void)
mmc_drv_obj.selected = TRUE;
- /* card speed check */
- resultCalc = emmc_calc_tran_speed(&freq); /* Card spec is calculated from TRAN_SPEED(CSD). */
- if (resultCalc == 0) {
+ /*
+ * card speed check
+ * Card spec is calculated from TRAN_SPEED(CSD)
+ */
+ result_calc = emmc_calc_tran_speed(&freq);
+ if (result_calc == 0) {
emmc_write_error_info(EMMC_FUNCNO_CARD_INIT,
EMMC_ERR_ILLEGAL_CARD);
return EMMC_ERR_ILLEGAL_CARD;
@@ -201,7 +204,8 @@ static EMMC_ERROR_CODE emmc_card_init(void)
HAL_MEMCARD_NOT_DMA);
result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
if (result != EMMC_SUCCESS) {
- /* CMD12 is not send.
+ /*
+ * CMD12 is not send.
* If BUS initialization is failed, user must be execute Bus initialization again.
* Bus initialization is start CMD0(soft reset command).
*/
@@ -217,7 +221,7 @@ static EMMC_ERROR_CODE emmc_card_init(void)
static EMMC_ERROR_CODE emmc_high_speed(void)
{
- uint32_t freq; /**< High speed mode clock frequency */
+ uint32_t freq; /* High speed mode clock frequency */
EMMC_ERROR_CODE result;
uint8_t cardType;
@@ -236,8 +240,8 @@ static EMMC_ERROR_CODE emmc_high_speed(void)
else
freq = MMC_20MHZ;
- /* Hi-Speed-mode selction */
- if ((MMC_52MHZ == freq) || (MMC_26MHZ == freq)) {
+ /* Hi-Speed-mode selection */
+ if ((freq == MMC_52MHZ) || (freq == MMC_26MHZ)) {
/* CMD6 */
emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS_TIMING);
result =
@@ -322,7 +326,8 @@ static EMMC_ERROR_CODE emmc_bus_width(uint32_t width)
return EMMC_ERR_STATE;
}
- mmc_drv_obj.bus_width = (HAL_MEMCARD_DATA_WIDTH) (width >> 2); /* 2 = 8bit, 1 = 4bit, 0 =1bit */
+ /* 2 = 8bit, 1 = 4bit, 0 =1bit */
+ mmc_drv_obj.bus_width = (HAL_MEMCARD_DATA_WIDTH) (width >> 2);
/* CMD6 */
emmc_make_nontrans_cmd(CMD6_SWITCH,
@@ -371,7 +376,6 @@ static EMMC_ERROR_CODE emmc_bus_width(uint32_t width)
return EMMC_SUCCESS;
EXIT:
-
emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, result);
ERROR("BL2: emmc bus_width error end\n");
return result;
@@ -489,82 +493,83 @@ static void emmc_get_partition_access(void)
static uint32_t emmc_calc_tran_speed(uint32_t *freq)
{
- const uint32_t unit[8] = { 10000, 100000, 1000000, 10000000,
- 0, 0, 0, 0 }; /**< frequency unit (1/10) */
- const uint32_t mult[16] = { 0, 10, 12, 13, 15, 20, 26, 30, 35, 40, 45,
- 52, 55, 60, 70, 80 };
-
- uint32_t maxFreq;
- uint32_t result;
+ const uint32_t unit[8] = { 10000U, 100000U, 1000000U, 10000000U,
+ 0U, 0U, 0U, 0U }; /* frequency unit (1/10) */
+ const uint32_t mult[16] = { 0U, 10U, 12U, 13U, 15U, 20U, 26U, 30U, 35U,
+ 40U, 45U, 52U, 55U, 60U, 70U, 80U };
uint32_t tran_speed = EMMC_CSD_TRAN_SPEED();
+ uint32_t max_freq;
+ uint32_t result;
- /* tran_speed = 0x32
+ /*
+ * tran_speed = 0x32
* unit[tran_speed&0x7] = uint[0x2] = 1000000
* mult[(tran_speed&0x78)>>3] = mult[0x30>>3] = mult[6] = 26
* 1000000 * 26 = 26000000 (26MHz)
*/
result = 1;
- maxFreq =
+ max_freq =
unit[tran_speed & EMMC_TRANSPEED_FREQ_UNIT_MASK] *
mult[(tran_speed & EMMC_TRANSPEED_MULT_MASK) >>
EMMC_TRANSPEED_MULT_SHIFT];
- if (maxFreq == 0) {
+ if (max_freq == 0) {
result = 0;
- } else if (MMC_FREQ_52MHZ <= maxFreq)
+ } else if (max_freq >= MMC_FREQ_52MHZ) {
*freq = MMC_52MHZ;
- else if (MMC_FREQ_26MHZ <= maxFreq)
+ } else if (max_freq >= MMC_FREQ_26MHZ) {
*freq = MMC_26MHZ;
- else if (MMC_FREQ_20MHZ <= maxFreq)
+ } else if (max_freq >= MMC_FREQ_20MHZ) {
*freq = MMC_20MHZ;
- else
+ } else {
*freq = MMC_400KHZ;
+ }
return result;
}
static uint32_t emmc_set_timeout_register_value(uint32_t freq)
{
- uint32_t timeoutCnt; /* SD_OPTION - Timeout Counter */
+ uint32_t timeout_cnt; /* SD_OPTION - Timeout Counter */
switch (freq) {
case 1U:
- timeoutCnt = 0xE0U;
+ timeout_cnt = 0xE0U;
break; /* SDCLK * 2^27 */
case 2U:
- timeoutCnt = 0xE0U;
+ timeout_cnt = 0xE0U;
break; /* SDCLK * 2^27 */
case 4U:
- timeoutCnt = 0xD0U;
+ timeout_cnt = 0xD0U;
break; /* SDCLK * 2^26 */
case 8U:
- timeoutCnt = 0xC0U;
+ timeout_cnt = 0xC0U;
break; /* SDCLK * 2^25 */
case 16U:
- timeoutCnt = 0xB0U;
+ timeout_cnt = 0xB0U;
break; /* SDCLK * 2^24 */
case 32U:
- timeoutCnt = 0xA0U;
+ timeout_cnt = 0xA0U;
break; /* SDCLK * 2^23 */
case 64U:
- timeoutCnt = 0x90U;
+ timeout_cnt = 0x90U;
break; /* SDCLK * 2^22 */
case 128U:
- timeoutCnt = 0x80U;
+ timeout_cnt = 0x80U;
break; /* SDCLK * 2^21 */
case 256U:
- timeoutCnt = 0x70U;
+ timeout_cnt = 0x70U;
break; /* SDCLK * 2^20 */
case 512U:
- timeoutCnt = 0x70U;
+ timeout_cnt = 0x70U;
break; /* SDCLK * 2^20 */
default:
- timeoutCnt = 0xE0U;
+ timeout_cnt = 0xE0U;
break; /* SDCLK * 2^27 */
}
- return timeoutCnt;
+ return timeout_cnt;
}
EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg)
diff --git a/drivers/renesas/rcar/emmc/emmc_read.c b/drivers/renesas/common/emmc/emmc_read.c
index 390d0caac1..96e73ca56c 100644
--- a/drivers/renesas/rcar/emmc/emmc_read.c
+++ b/drivers/renesas/common/emmc/emmc_read.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,15 +7,15 @@
#include <arch_helpers.h>
#include "emmc_config.h"
+#include "emmc_def.h"
#include "emmc_hal.h"
-#include "emmc_std.h"
#include "emmc_registers.h"
-#include "emmc_def.h"
+#include "emmc_std.h"
-#define MIN_EMMC(a, b) (((a) < (b)) ? (a) : (b))
-#define EMMC_RW_SECTOR_COUNT_MAX 0x0000ffffU
+#define MIN_EMMC(a, b) (((a) < (b)) ? (a) : (b))
+#define EMMC_RW_SECTOR_COUNT_MAX 0x0000ffffU
-static EMMC_ERROR_CODE emmc_multiple_block_read (uint32_t *buff_address_virtual,
+static EMMC_ERROR_CODE emmc_multiple_block_read(uint32_t *buff_address_virtual,
uint32_t sector_number, uint32_t count,
HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode)
{
@@ -39,7 +39,8 @@ static EMMC_ERROR_CODE emmc_multiple_block_read (uint32_t *buff_address_virtual,
}
SETR_32(SD_SECCNT, count);
SETR_32(SD_STOP, 0x00000100);
- SETR_32(CC_EXT_MODE, (CC_EXT_MODE_CLEAR | CC_EXT_MODE_DMASDRW_ENABLE)); /* SD_BUF Read/Write DMA Transfer enable */
+ /* SD_BUF Read/Write DMA Transfer enable */
+ SETR_32(CC_EXT_MODE, (CC_EXT_MODE_CLEAR | CC_EXT_MODE_DMASDRW_ENABLE));
/* CMD18 */
emmc_make_trans_cmd(CMD18_READ_MULTIPLE_BLOCK, sector_number,
diff --git a/drivers/renesas/common/emmc/emmc_registers.h b/drivers/renesas/common/emmc/emmc_registers.h
new file mode 100644
index 0000000000..392abb8fb4
--- /dev/null
+++ b/drivers/renesas/common/emmc/emmc_registers.h
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef EMMC_REGISTERS_H
+#define EMMC_REGISTERS_H
+
+/* MMC channel select */
+#define MMC_CH0 (0U) /* SDHI2/MMC0 */
+#define MMC_CH1 (1U) /* SDHI3/MMC1 */
+
+#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2M)
+#define USE_MMC_CH (MMC_CH1) /* R-Car E3 or RZ/G2M */
+#else /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2M */
+#define USE_MMC_CH (MMC_CH0) /* R-Car H3/M3/M3N */
+#endif /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2M */
+
+#define BIT0 (0x00000001U)
+#define BIT1 (0x00000002U)
+#define BIT2 (0x00000004U)
+#define BIT3 (0x00000008U)
+#define BIT4 (0x00000010U)
+#define BIT5 (0x00000020U)
+#define BIT6 (0x00000040U)
+#define BIT7 (0x00000080U)
+#define BIT8 (0x00000100U)
+#define BIT9 (0x00000200U)
+#define BIT10 (0x00000400U)
+#define BIT11 (0x00000800U)
+#define BIT12 (0x00001000U)
+#define BIT13 (0x00002000U)
+#define BIT14 (0x00004000U)
+#define BIT15 (0x00008000U)
+#define BIT16 (0x00010000U)
+#define BIT17 (0x00020000U)
+#define BIT18 (0x00040000U)
+#define BIT19 (0x00080000U)
+#define BIT20 (0x00100000U)
+#define BIT21 (0x00200000U)
+#define BIT22 (0x00400000U)
+#define BIT23 (0x00800000U)
+#define BIT24 (0x01000000U)
+#define BIT25 (0x02000000U)
+#define BIT26 (0x04000000U)
+#define BIT27 (0x08000000U)
+#define BIT28 (0x10000000U)
+#define BIT29 (0x20000000U)
+#define BIT30 (0x40000000U)
+#define BIT31 (0x80000000U)
+
+/* Clock Pulse Generator (CPG) registers */
+#define CPG_BASE (0xE6150000U)
+/* Module stop status register 3 */
+#define CPG_MSTPSR3 (CPG_BASE + 0x0048U)
+/* System module stop control register 3 */
+#define CPG_SMSTPCR3 (CPG_BASE + 0x013CU)
+/* SDHI2 clock frequency control register */
+#define CPG_SD2CKCR (CPG_BASE + 0x0268U)
+/* SDHI3 clock frequency control register */
+#define CPG_SD3CKCR (CPG_BASE + 0x026CU)
+/* CPG Write Protect Register */
+#define CPG_CPGWPR (CPG_BASE + 0x0900U)
+
+#if USE_MMC_CH == MMC_CH0
+#define CPG_SDxCKCR (CPG_SD2CKCR) /* SDHI2/MMC0 */
+#else /* USE_MMC_CH == MMC_CH0 */
+#define CPG_SDxCKCR (CPG_SD3CKCR) /* SDHI3/MMC1 */
+#endif /* USE_MMC_CH == MMC_CH0 */
+
+/* Boot Status register */
+#define MFISBTSTSR (0xE6260604U)
+
+#define MFISBTSTSR_BOOT_PARTITION (0x00000010U)
+
+/* eMMC registers */
+#define MMC0_SD_BASE (0xEE140000U)
+#define MMC1_SD_BASE (0xEE160000U)
+
+#if USE_MMC_CH == MMC_CH0
+#define MMC_SD_BASE (MMC0_SD_BASE)
+#else /* USE_MMC_CH == MMC_CH0 */
+#define MMC_SD_BASE (MMC1_SD_BASE)
+#endif /* USE_MMC_CH == MMC_CH0 */
+
+#define SD_CMD (MMC_SD_BASE + 0x0000U)
+#define SD_PORTSEL (MMC_SD_BASE + 0x0008U)
+#define SD_ARG (MMC_SD_BASE + 0x0010U)
+#define SD_ARG1 (MMC_SD_BASE + 0x0018U)
+#define SD_STOP (MMC_SD_BASE + 0x0020U)
+#define SD_SECCNT (MMC_SD_BASE + 0x0028U)
+#define SD_RSP10 (MMC_SD_BASE + 0x0030U)
+#define SD_RSP1 (MMC_SD_BASE + 0x0038U)
+#define SD_RSP32 (MMC_SD_BASE + 0x0040U)
+#define SD_RSP3 (MMC_SD_BASE + 0x0048U)
+#define SD_RSP54 (MMC_SD_BASE + 0x0050U)
+#define SD_RSP5 (MMC_SD_BASE + 0x0058U)
+#define SD_RSP76 (MMC_SD_BASE + 0x0060U)
+#define SD_RSP7 (MMC_SD_BASE + 0x0068U)
+#define SD_INFO1 (MMC_SD_BASE + 0x0070U)
+#define SD_INFO2 (MMC_SD_BASE + 0x0078U)
+#define SD_INFO1_MASK (MMC_SD_BASE + 0x0080U)
+#define SD_INFO2_MASK (MMC_SD_BASE + 0x0088U)
+#define SD_CLK_CTRL (MMC_SD_BASE + 0x0090U)
+#define SD_SIZE (MMC_SD_BASE + 0x0098U)
+#define SD_OPTION (MMC_SD_BASE + 0x00A0U)
+#define SD_ERR_STS1 (MMC_SD_BASE + 0x00B0U)
+#define SD_ERR_STS2 (MMC_SD_BASE + 0x00B8U)
+#define SD_BUF0 (MMC_SD_BASE + 0x00C0U)
+#define SDIO_MODE (MMC_SD_BASE + 0x00D0U)
+#define SDIO_INFO1 (MMC_SD_BASE + 0x00D8U)
+#define SDIO_INFO1_MASK (MMC_SD_BASE + 0x00E0U)
+#define CC_EXT_MODE (MMC_SD_BASE + 0x0360U)
+#define SOFT_RST (MMC_SD_BASE + 0x0380U)
+#define VERSION (MMC_SD_BASE + 0x0388U)
+#define HOST_MODE (MMC_SD_BASE + 0x0390U)
+#define DM_CM_DTRAN_MODE (MMC_SD_BASE + 0x0820U)
+#define DM_CM_DTRAN_CTRL (MMC_SD_BASE + 0x0828U)
+#define DM_CM_RST (MMC_SD_BASE + 0x0830U)
+#define DM_CM_INFO1 (MMC_SD_BASE + 0x0840U)
+#define DM_CM_INFO1_MASK (MMC_SD_BASE + 0x0848U)
+#define DM_CM_INFO2 (MMC_SD_BASE + 0x0850U)
+#define DM_CM_INFO2_MASK (MMC_SD_BASE + 0x0858U)
+#define DM_DTRAN_ADDR (MMC_SD_BASE + 0x0880U)
+
+/* SD_INFO1 Registers */
+#define SD_INFO1_HPIRES 0x00010000UL /* Response Reception Completion */
+#define SD_INFO1_INFO10 0x00000400UL /* Indicates the SDDAT3 state */
+#define SD_INFO1_INFO9 0x00000200UL /* SDDAT3 Card Insertion */
+#define SD_INFO1_INFO8 0x00000100UL /* SDDAT3 Card Removal */
+#define SD_INFO1_INFO7 0x00000080UL /* Write Protect */
+#define SD_INFO1_INFO5 0x00000020UL /* Indicates the ISDCD state */
+#define SD_INFO1_INFO4 0x00000010UL /* ISDCD Card Insertion */
+#define SD_INFO1_INFO3 0x00000008UL /* ISDCD Card Removal */
+#define SD_INFO1_INFO2 0x00000004UL /* Access end */
+#define SD_INFO1_INFO0 0x00000001UL /* Response end */
+
+/* SD_INFO2 Registers */
+#define SD_INFO2_ILA 0x00008000UL /* Illegal Access Error */
+#define SD_INFO2_CBSY 0x00004000UL /* Command Type Register Busy */
+#define SD_INFO2_SCLKDIVEN 0x00002000UL
+#define SD_INFO2_BWE 0x00000200UL /* SD_BUF Write Enable */
+#define SD_INFO2_BRE 0x00000100UL /* SD_BUF Read Enable */
+#define SD_INFO2_DAT0 0x00000080UL /* SDDAT0 */
+#define SD_INFO2_ERR6 0x00000040UL /* Response Timeout */
+#define SD_INFO2_ERR5 0x00000020UL /* SD_BUF Illegal Read Access */
+#define SD_INFO2_ERR4 0x00000010UL /* SD_BUF Illegal Write Access */
+#define SD_INFO2_ERR3 0x00000008UL /* Data Timeout */
+#define SD_INFO2_ERR2 0x00000004UL /* END Error */
+#define SD_INFO2_ERR1 0x00000002UL /* CRC Error */
+#define SD_INFO2_ERR0 0x00000001UL /* CMD Error */
+#define SD_INFO2_ALL_ERR 0x0000807FUL
+#define SD_INFO2_CLEAR 0x00000800UL /* BIT11 write value should always be 1. HWM_0003 */
+
+/* SOFT_RST */
+#define SOFT_RST_SDRST 0x00000001UL
+
+/* SD_CLK_CTRL */
+#define SD_CLK_CTRL_SDCLKOFFEN 0x00000200UL
+#define SD_CLK_CTRL_SCLKEN 0x00000100UL
+#define SD_CLK_CTRL_CLKDIV_MASK 0x000000FFUL
+#define SD_CLOCK_ENABLE 0x00000100UL
+#define SD_CLOCK_DISABLE 0x00000000UL
+#define SD_CLK_WRITE_MASK 0x000003FFUL
+#define SD_CLK_CLKDIV_CLEAR_MASK 0xFFFFFF0FUL
+
+/* SD_OPTION */
+#define SD_OPTION_TIMEOUT_CNT_MASK 0x000000F0UL
+
+/*
+ * MMC Clock Frequency
+ * 200MHz * 1/x = output clock
+ */
+#define MMC_CLK_OFF 0UL /* Clock output is disabled */
+#define MMC_400KHZ 512UL /* 200MHz * 1/512 = 390 KHz */
+#define MMC_20MHZ 16UL /* 200MHz * 1/16 = 12.5 MHz Normal speed mode */
+#define MMC_26MHZ 8UL /* 200MHz * 1/8 = 25 MHz HS mode 26Mhz */
+#define MMC_52MHZ 4UL /* 200MHz * 1/4 = 50 MHz HS mode 52Mhz */
+#define MMC_100MHZ 2UL /* 200MHz * 1/2 = 100 MHz */
+#define MMC_200MHZ 1UL /* 200MHz * 1/1 = 200 MHz */
+
+#define MMC_FREQ_52MHZ 52000000UL
+#define MMC_FREQ_26MHZ 26000000UL
+#define MMC_FREQ_20MHZ 20000000UL
+
+/* MMC Clock DIV */
+#define MMC_SD_CLK_START 0x00000100UL /* CLOCK On */
+#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */
+#define MMC_SD_CLK_DIV1 0x000000FFUL /* 1/1 */
+#define MMC_SD_CLK_DIV2 0x00000000UL /* 1/2 */
+#define MMC_SD_CLK_DIV4 0x00000001UL /* 1/4 */
+#define MMC_SD_CLK_DIV8 0x00000002UL /* 1/8 */
+#define MMC_SD_CLK_DIV16 0x00000004UL /* 1/16 */
+#define MMC_SD_CLK_DIV32 0x00000008UL /* 1/32 */
+#define MMC_SD_CLK_DIV64 0x00000010UL /* 1/64 */
+#define MMC_SD_CLK_DIV128 0x00000020UL /* 1/128 */
+#define MMC_SD_CLK_DIV256 0x00000040UL /* 1/256 */
+#define MMC_SD_CLK_DIV512 0x00000080UL /* 1/512 */
+
+/* DM_CM_DTRAN_MODE */
+#define DM_CM_DTRAN_MODE_CH0 0x00000000UL /* CH0(downstream) */
+#define DM_CM_DTRAN_MODE_CH1 0x00010000UL /* CH1(upstream) */
+#define DM_CM_DTRAN_MODE_BIT_WIDTH 0x00000030UL
+
+/* CC_EXT_MODE */
+#define CC_EXT_MODE_DMASDRW_ENABLE 0x00000002UL /* SD_BUF Read/Write DMA Transfer */
+#define CC_EXT_MODE_CLEAR 0x00001010UL /* BIT 12 & 4 always 1. */
+
+/* DM_CM_INFO_MASK */
+#define DM_CM_INFO_MASK_CLEAR 0xFFFCFFFEUL
+#define DM_CM_INFO_CH0_ENABLE 0x00010001UL
+#define DM_CM_INFO_CH1_ENABLE 0x00020001UL
+
+/* DM_DTRAN_ADDR */
+#define DM_DTRAN_ADDR_WRITE_MASK 0xFFFFFFF8UL
+
+/* DM_CM_DTRAN_CTRL */
+#define DM_CM_DTRAN_CTRL_START 0x00000001UL
+
+/* SYSC Registers */
+#if USE_MMC_CH == MMC_CH0
+#define CPG_MSTP_MMC (BIT12) /* SDHI2/MMC0 */
+#else /* USE_MMC_CH == MMC_CH0 */
+#define CPG_MSTP_MMC (BIT11) /* SDHI3/MMC1 */
+#endif /* USE_MMC_CH == MMC_CH0 */
+
+#endif /* EMMC_REGISTERS_H */
diff --git a/drivers/renesas/common/emmc/emmc_std.h b/drivers/renesas/common/emmc/emmc_std.h
new file mode 100644
index 0000000000..087c6e91d8
--- /dev/null
+++ b/drivers/renesas/common/emmc/emmc_std.h
@@ -0,0 +1,475 @@
+/*
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef EMMC_STD_H
+#define EMMC_STD_H
+
+#include "emmc_hal.h"
+
+#ifndef FALSE
+#define FALSE 0U
+#endif
+#ifndef TRUE
+#define TRUE 1U
+#endif
+
+/* 64bit registers */
+#define SETR_64(r, v) (*(volatile uint64_t *)(r) = (v))
+#define GETR_64(r) (*(volatile uint64_t *)(r))
+
+/* 32bit registers */
+#define SETR_32(r, v) (*(volatile uint32_t *)(r) = (v))
+#define GETR_32(r) (*(volatile uint32_t *)(r))
+
+/* 16bit registers */
+#define SETR_16(r, v) (*(volatile uint16_t *)(r) = (v))
+#define GETR_16(r) (*(volatile uint16_t *)(r))
+
+/* 8bit registers */
+#define SETR_8(r, v) (*(volatile uint8_t *)(r) = (v))
+#define GETR_8(r) (*(volatile uint8_t *)(r))
+
+/* CSD register Macros */
+#define EMMC_GET_CID(x, y) (emmc_bit_field(mmc_drv_obj.cid_data, (x), (y)))
+
+#define EMMC_CID_MID() (EMMC_GET_CID(127, 120))
+#define EMMC_CID_CBX() (EMMC_GET_CID(113, 112))
+#define EMMC_CID_OID() (EMMC_GET_CID(111, 104))
+#define EMMC_CID_PNM1() (EMMC_GET_CID(103, 88))
+#define EMMC_CID_PNM2() (EMMC_GET_CID(87, 56))
+#define EMMC_CID_PRV() (EMMC_GET_CID(55, 48))
+#define EMMC_CID_PSN() (EMMC_GET_CID(47, 16))
+#define EMMC_CID_MDT() (EMMC_GET_CID(15, 8))
+#define EMMC_CID_CRC() (EMMC_GET_CID(7, 1))
+
+/* CSD register Macros */
+#define EMMC_GET_CSD(x, y) (emmc_bit_field(mmc_drv_obj.csd_data, (x), (y)))
+
+#define EMMC_CSD_CSD_STRUCTURE() (EMMC_GET_CSD(127, 126))
+#define EMMC_CSD_SPEC_VARS() (EMMC_GET_CSD(125, 122))
+#define EMMC_CSD_TAAC() (EMMC_GET_CSD(119, 112))
+#define EMMC_CSD_NSAC() (EMMC_GET_CSD(111, 104))
+#define EMMC_CSD_TRAN_SPEED() (EMMC_GET_CSD(103, 96))
+#define EMMC_CSD_CCC() (EMMC_GET_CSD(95, 84))
+#define EMMC_CSD_READ_BL_LEN() (EMMC_GET_CSD(83, 80))
+#define EMMC_CSD_READ_BL_PARTIAL() (EMMC_GET_CSD(79, 79))
+#define EMMC_CSD_WRITE_BLK_MISALIGN() (EMMC_GET_CSD(78, 78))
+#define EMMC_CSD_READ_BLK_MISALIGN() (EMMC_GET_CSD(77, 77))
+#define EMMC_CSD_DSR_IMP() (EMMC_GET_CSD(76, 76))
+#define EMMC_CSD_C_SIZE() (EMMC_GET_CSD(73, 62))
+#define EMMC_CSD_VDD_R_CURR_MIN() (EMMC_GET_CSD(61, 59))
+#define EMMC_CSD_VDD_R_CURR_MAX() (EMMC_GET_CSD(58, 56))
+#define EMMC_CSD_VDD_W_CURR_MIN() (EMMC_GET_CSD(55, 53))
+#define EMMC_CSD_VDD_W_CURR_MAX() (EMMC_GET_CSD(52, 50))
+#define EMMC_CSD_C_SIZE_MULT() (EMMC_GET_CSD(49, 47))
+#define EMMC_CSD_ERASE_GRP_SIZE() (EMMC_GET_CSD(46, 42))
+#define EMMC_CSD_ERASE_GRP_MULT() (EMMC_GET_CSD(41, 37))
+#define EMMC_CSD_WP_GRP_SIZE() (EMMC_GET_CSD(36, 32))
+#define EMMC_CSD_WP_GRP_ENABLE() (EMMC_GET_CSD(31, 31))
+#define EMMC_CSD_DEFALT_ECC() (EMMC_GET_CSD(30, 29))
+#define EMMC_CSD_R2W_FACTOR() (EMMC_GET_CSD(28, 26))
+#define EMMC_CSD_WRITE_BL_LEN() (EMMC_GET_CSD(25, 22))
+#define EMMC_CSD_WRITE_BL_PARTIAL() (EMMC_GET_CSD(21, 21))
+#define EMMC_CSD_CONTENT_PROT_APP() (EMMC_GET_CSD(16, 16))
+#define EMMC_CSD_FILE_FORMAT_GRP() (EMMC_GET_CSD(15, 15))
+#define EMMC_CSD_COPY() (EMMC_GET_CSD(14, 14))
+#define EMMC_CSD_PERM_WRITE_PROTECT() (EMMC_GET_CSD(13, 13))
+#define EMMC_CSD_TMP_WRITE_PROTECT() (EMMC_GET_CSD(12, 12))
+#define EMMC_CSD_FILE_FORMAT() (EMMC_GET_CSD(11, 10))
+#define EMMC_CSD_ECC() (EMMC_GET_CSD(9, 8))
+#define EMMC_CSD_CRC() (EMMC_GET_CSD(7, 1))
+
+/* sector access */
+#define EMMC_4B_BOUNDARY_CHECK_MASK 0x00000003
+#define EMMC_SECTOR_SIZE_SHIFT 9U /* 512 = 2^9 */
+#define EMMC_SECTOR_SIZE 512
+#define EMMC_BLOCK_LENGTH 512
+#define EMMC_BLOCK_LENGTH_DW 128
+#define EMMC_BUF_SIZE_SHIFT 3U /* 8byte = 2^3 */
+
+/* eMMC specification clock */
+#define EMMC_CLOCK_SPEC_400K 400000UL /* initialize clock 400KHz */
+#define EMMC_CLOCK_SPEC_20M 20000000UL /* normal speed 20MHz */
+#define EMMC_CLOCK_SPEC_26M 26000000UL /* high speed 26MHz */
+#define EMMC_CLOCK_SPEC_52M 52000000UL /* high speed 52MHz */
+#define EMMC_CLOCK_SPEC_100M 100000000UL /* high speed 100MHz */
+
+/* EMMC driver error code. (extended HAL_MEMCARD_RETURN) */
+typedef enum {
+ EMMC_ERR = 0, /* unknown error */
+ EMMC_SUCCESS, /* OK */
+ EMMC_ERR_FROM_DMAC, /* DMAC allocation error */
+ EMMC_ERR_FROM_DMAC_TRANSFER, /* DMAC transfer error */
+ EMMC_ERR_CARD_STATUS_BIT, /* card status error */
+ EMMC_ERR_CMD_TIMEOUT, /* command timeout error */
+ EMMC_ERR_DATA_TIMEOUT, /* data timeout error */
+ EMMC_ERR_CMD_CRC, /* command CRC error */
+ EMMC_ERR_DATA_CRC, /* data CRC error */
+ EMMC_ERR_PARAM, /* parameter error */
+ EMMC_ERR_RESPONSE, /* response error */
+ EMMC_ERR_RESPONSE_BUSY, /* response busy error */
+ EMMC_ERR_TRANSFER, /* data transfer error */
+ EMMC_ERR_READ_SECTOR, /* read sector error */
+ EMMC_ERR_WRITE_SECTOR, /* write sector error */
+ EMMC_ERR_STATE, /* state error */
+ EMMC_ERR_TIMEOUT, /* timeout error */
+ EMMC_ERR_ILLEGAL_CARD, /* illegal card */
+ EMMC_ERR_CARD_BUSY, /* Busy state */
+ EMMC_ERR_CARD_STATE, /* card state error */
+ EMMC_ERR_SET_TRACE, /* trace information error */
+ EMMC_ERR_FROM_TIMER, /* Timer error */
+ EMMC_ERR_FORCE_TERMINATE, /* Force terminate */
+ EMMC_ERR_CARD_POWER, /* card power fail */
+ EMMC_ERR_ERASE_SECTOR, /* erase sector error */
+ EMMC_ERR_INFO2 /* exec cmd error info2 */
+} EMMC_ERROR_CODE;
+
+/* Function number */
+#define EMMC_FUNCNO_NONE 0U
+#define EMMC_FUNCNO_DRIVER_INIT 1U
+#define EMMC_FUNCNO_CARD_POWER_ON 2U
+#define EMMC_FUNCNO_MOUNT 3U
+#define EMMC_FUNCNO_CARD_INIT 4U
+#define EMMC_FUNCNO_HIGH_SPEED 5U
+#define EMMC_FUNCNO_BUS_WIDTH 6U
+#define EMMC_FUNCNO_MULTI_BOOT_SELECT_PARTITION 7U
+#define EMMC_FUNCNO_MULTI_BOOT_READ_SECTOR 8U
+#define EMMC_FUNCNO_TRANS_DATA_READ_SECTOR 9U
+#define EMMC_FUNCNO_UBOOT_IMAGE_SELECT_PARTITION 10U
+#define EMMC_FUNCNO_UBOOT_IMAGE_READ_SECTOR 11U
+#define EMMC_FUNCNO_SET_CLOCK 12U
+#define EMMC_FUNCNO_EXEC_CMD 13U
+#define EMMC_FUNCNO_READ_SECTOR 14U
+#define EMMC_FUNCNO_WRITE_SECTOR 15U
+#define EMMC_FUNCNO_ERASE_SECTOR 16U
+#define EMMC_FUNCNO_GET_PERTITION_ACCESS 17U
+/*
+ * Response
+ * R1
+ * Type 'E' bit and bit14(must be 0). ignore bit22
+ */
+#define EMMC_R1_ERROR_MASK 0xFDBFE080U
+/* Ignore bit23 (Not check CRC error) */
+#define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U)
+#define EMMC_R1_STATE_MASK 0x00001E00U /* [12:9] */
+#define EMMC_R1_READY 0x00000100U /* bit8 */
+#define EMMC_R1_STATE_SHIFT 9
+
+/* R4 */
+#define EMMC_R4_RCA_MASK 0xFFFF0000UL
+#define EMMC_R4_STATUS 0x00008000UL
+
+/* CSD */
+#define EMMC_TRANSPEED_FREQ_UNIT_MASK 0x07 /* bit[2:0] */
+#define EMMC_TRANSPEED_FREQ_UNIT_SHIFT 0
+#define EMMC_TRANSPEED_MULT_MASK 0x78 /* bit[6:3] */
+#define EMMC_TRANSPEED_MULT_SHIFT 3
+
+/* OCR */
+#define EMMC_HOST_OCR_VALUE 0x40FF8080
+#define EMMC_OCR_STATUS_BIT 0x80000000L /* Card power up status bit */
+#define EMMC_OCR_ACCESS_MODE_MASK 0x60000000L /* bit[30:29] */
+#define EMMC_OCR_ACCESS_MODE_SECT 0x40000000L
+#define EMMC_OCR_ACCESS_MODE_BYTE 0x00000000L
+
+/* EXT_CSD */
+#define EMMC_EXT_CSD_S_CMD_SET 504
+#define EMMC_EXT_CSD_INI_TIMEOUT_AP 241
+#define EMMC_EXT_CSD_PWR_CL_DDR_52_360 239
+#define EMMC_EXT_CSD_PWR_CL_DDR_52_195 238
+#define EMMC_EXT_CSD_MIN_PERF_DDR_W_8_52 235
+#define EMMC_EXT_CSD_MIN_PERF_DDR_R_8_52 234
+#define EMMC_EXT_CSD_TRIM_MULT 232
+#define EMMC_EXT_CSD_SEC_FEATURE_SUPPORT 231
+#define EMMC_EXT_CSD_SEC_ERASE_MULT 229
+#define EMMC_EXT_CSD_BOOT_INFO 228
+#define EMMC_EXT_CSD_BOOT_SIZE_MULTI 226
+#define EMMC_EXT_CSD_ACC_SIZE 225
+#define EMMC_EXT_CSD_HC_ERASE_GRP_SIZE 224
+#define EMMC_EXT_CSD_ERASE_TIMEOUT_MULT 223
+#define EMMC_EXT_CSD_PEL_WR_SEC_C 222
+#define EMMC_EXT_CSD_HC_WP_GRP_SIZE 221
+#define EMMC_EXT_CSD_S_C_VCC 220
+#define EMMC_EXT_CSD_S_C_VCCQ 219
+#define EMMC_EXT_CSD_S_A_TIMEOUT 217
+#define EMMC_EXT_CSD_SEC_COUNT 215
+#define EMMC_EXT_CSD_MIN_PERF_W_8_52 210
+#define EMMC_EXT_CSD_MIN_PERF_R_8_52 209
+#define EMMC_EXT_CSD_MIN_PERF_W_8_26_4_52 208
+#define EMMC_EXT_CSD_MIN_PERF_R_8_26_4_52 207
+#define EMMC_EXT_CSD_MIN_PERF_W_4_26 206
+#define EMMC_EXT_CSD_MIN_PERF_R_4_26 205
+#define EMMC_EXT_CSD_PWR_CL_26_360 203
+#define EMMC_EXT_CSD_PWR_CL_52_360 202
+#define EMMC_EXT_CSD_PWR_CL_26_195 201
+#define EMMC_EXT_CSD_PWR_CL_52_195 200
+#define EMMC_EXT_CSD_CARD_TYPE 196
+#define EMMC_EXT_CSD_CSD_STRUCTURE 194
+#define EMMC_EXT_CSD_EXT_CSD_REV 192
+#define EMMC_EXT_CSD_CMD_SET 191
+#define EMMC_EXT_CSD_CMD_SET_REV 189
+#define EMMC_EXT_CSD_POWER_CLASS 187
+#define EMMC_EXT_CSD_HS_TIMING 185
+#define EMMC_EXT_CSD_BUS_WIDTH 183
+#define EMMC_EXT_CSD_ERASED_MEM_CONT 181
+#define EMMC_EXT_CSD_PARTITION_CONFIG 179
+#define EMMC_EXT_CSD_BOOT_CONFIG_PROT 178
+#define EMMC_EXT_CSD_BOOT_BUS_WIDTH 177
+#define EMMC_EXT_CSD_ERASE_GROUP_DEF 175
+#define EMMC_EXT_CSD_BOOT_WP 173
+#define EMMC_EXT_CSD_USER_WP 171
+#define EMMC_EXT_CSD_FW_CONFIG 169
+#define EMMC_EXT_CSD_RPMB_SIZE_MULT 168
+#define EMMC_EXT_CSD_RST_n_FUNCTION 162
+#define EMMC_EXT_CSD_PARTITIONING_SUPPORT 160
+#define EMMC_EXT_CSD_MAX_ENH_SIZE_MULT 159
+#define EMMC_EXT_CSD_PARTITIONS_ATTRIBUTE 156
+#define EMMC_EXT_CSD_PARTITION_SETTING_COMPLETED 155
+#define EMMC_EXT_CSD_GP_SIZE_MULT 154
+#define EMMC_EXT_CSD_ENH_SIZE_MULT 142
+#define EMMC_EXT_CSD_ENH_START_ADDR 139
+#define EMMC_EXT_CSD_SEC_BAD_BLK_MGMNT 134
+
+#define EMMC_EXT_CSD_CARD_TYPE_26MHZ 0x01
+#define EMMC_EXT_CSD_CARD_TYPE_52MHZ 0x02
+#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_12V 0x04
+#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_18V 0x08
+#define EMMC_EXT_CSD_CARD_TYPE_52MHZ_MASK 0x0e
+
+/* SWITCH (CMD6) argument */
+#define EXTCSD_ACCESS_BYTE (BIT25 | BIT24)
+#define EXTCSD_SET_BITS BIT24
+
+#define HS_TIMING_ADD (185 << 16) /* H'b9 */
+#define HS_TIMING_1 (1 << 8)
+#define HS_TIMING_HS200 (2 << 8)
+#define HS_TIMING_HS400 (3 << 8)
+
+#define BUS_WIDTH_ADD (183 << 16) /* H'b7 */
+#define BUS_WIDTH_1 (0 << 8)
+#define BUS_WIDTH_4 (1 << 8)
+#define BUS_WIDTH_8 (2 << 8)
+#define BUS_WIDTH_4DDR (5 << 8)
+#define BUS_WIDTH_8DDR (6 << 8)
+
+#define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE | HS_TIMING_ADD |\
+ HS_TIMING_1) /* H'03b90100 */
+#define EMMC_SWITCH_HS_TIMING_OFF (EXTCSD_ACCESS_BYTE |\
+ HS_TIMING_ADD) /* H'03b90000 */
+
+#define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
+ BUS_WIDTH_1) /* H'03b70000 */
+#define EMMC_SWITCH_BUS_WIDTH_4 (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
+ BUS_WIDTH_4) /* H'03b70100 */
+#define EMMC_SWITCH_BUS_WIDTH_8 (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
+ BUS_WIDTH_8) /* H'03b70200 */
+#define EMMC_SWITCH_BUS_WIDTH_4DDR (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
+ BUS_WIDTH_4DDR) /* H'03b70500 */
+#define EMMC_SWITCH_BUS_WIDTH_8DDR (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
+ BUS_WIDTH_8DDR) /* H'03b70600 */
+/* Partition config = 0x00 */
+#define EMMC_SWITCH_PARTITION_CONFIG 0x03B30000UL
+
+#define TIMING_HIGH_SPEED 1UL
+#define EMMC_BOOT_PARTITION_EN_MASK 0x38U
+#define EMMC_BOOT_PARTITION_EN_SHIFT 3U
+
+/* Bus width */
+#define EMMC_BUSWIDTH_1BIT CE_CMD_SET_DATW_1BIT
+#define EMMC_BUSWIDTH_4BIT CE_CMD_SET_DATW_4BIT
+#define EMMC_BUSWIDTH_8BIT CE_CMD_SET_DATW_8BIT
+
+/* for st_mmc_base */
+#define EMMC_MAX_RESPONSE_LENGTH 17
+#define EMMC_MAX_CID_LENGTH 16
+#define EMMC_MAX_CSD_LENGTH 16
+#define EMMC_MAX_EXT_CSD_LENGTH 512U
+#define EMMC_RES_REG_ALIGNED 4U
+#define EMMC_BUF_REG_ALIGNED 8U
+
+/* TAAC mask */
+#define TAAC_TIME_UNIT_MASK (0x07)
+#define TAAC_MULTIPLIER_FACTOR_MASK (0x0F)
+
+/* Partition id */
+typedef enum {
+ PARTITION_ID_USER = 0x0, /* User Area */
+ PARTITION_ID_BOOT_1 = 0x1, /* boot partition 1 */
+ PARTITION_ID_BOOT_2 = 0x2, /* boot partition 2 */
+ PARTITION_ID_RPMB = 0x3, /* Replay Protected Memory Block */
+ PARTITION_ID_GP_1 = 0x4, /* General Purpose partition 1 */
+ PARTITION_ID_GP_2 = 0x5, /* General Purpose partition 2 */
+ PARTITION_ID_GP_3 = 0x6, /* General Purpose partition 3 */
+ PARTITION_ID_GP_4 = 0x7, /* General Purpose partition 4 */
+ PARTITION_ID_MASK = 0x7 /* [2:0] */
+} EMMC_PARTITION_ID;
+
+/* card state in R1 response [12:9] */
+typedef enum {
+ EMMC_R1_STATE_IDLE = 0,
+ EMMC_R1_STATE_READY,
+ EMMC_R1_STATE_IDENT,
+ EMMC_R1_STATE_STBY,
+ EMMC_R1_STATE_TRAN,
+ EMMC_R1_STATE_DATA,
+ EMMC_R1_STATE_RCV,
+ EMMC_R1_STATE_PRG,
+ EMMC_R1_STATE_DIS,
+ EMMC_R1_STATE_BTST,
+ EMMC_R1_STATE_SLEP
+} EMMC_R1_STATE;
+
+typedef enum {
+ ESTATE_BEGIN = 0,
+ ESTATE_ISSUE_CMD,
+ ESTATE_NON_RESP_CMD,
+ ESTATE_RCV_RESP,
+ ESTATE_RCV_RESPONSE_BUSY,
+ ESTATE_CHECK_RESPONSE_COMPLETE,
+ ESTATE_DATA_TRANSFER,
+ ESTATE_DATA_TRANSFER_COMPLETE,
+ ESTATE_ACCESS_END,
+ ESTATE_TRANSFER_ERROR,
+ ESTATE_ERROR,
+ ESTATE_END
+} EMMC_INT_STATE;
+
+/* eMMC boot driver error information */
+typedef struct {
+ uint16_t num; /* error no */
+ uint16_t code; /* error code */
+
+ volatile uint32_t info1; /* SD_INFO1. (hw dependent) */
+ volatile uint32_t info2; /* SD_INFO2. (hw dependent) */
+ volatile uint32_t status1; /* SD_ERR_STS1. (hw dependent) */
+ volatile uint32_t status2; /* SD_ERR_STS2. (hw dependent) */
+ volatile uint32_t dm_info1; /* DM_CM_INFO1. (hw dependent) */
+ volatile uint32_t dm_info2; /* DM_CM_INFO2. (hw dependent) */
+} st_error_info;
+
+/* Command information */
+typedef struct {
+ HAL_MEMCARD_COMMAND cmd; /* Command information */
+ uint32_t arg; /* argument */
+ HAL_MEMCARD_OPERATION dir; /* direction */
+ uint32_t hw; /* SD_CMD register value. */
+} st_command_info;
+
+/* MMC driver base */
+typedef struct {
+ st_error_info error_info; /* error information */
+ st_command_info cmd_info; /* command information */
+
+ /* for data transfer */
+ uint32_t *buff_address_virtual; /* Dest or Src buff */
+ uint32_t *buff_address_physical; /* Dest or Src buff */
+ HAL_MEMCARD_DATA_WIDTH bus_width; /* bus width */
+
+ uint32_t trans_size; /* transfer size for this command */
+ uint32_t remain_size; /* remain size for this command */
+ uint32_t response_length; /* response length for this command */
+ uint32_t sector_size; /* sector_size */
+
+ /* clock */
+ uint32_t base_clock; /* MMC host controller clock */
+ /*
+ * Max freq (Card Spec)[Hz]. It changes dynamically by CSD and
+ * EXT_CSD.
+ */
+ uint32_t max_freq;
+ /* request freq [Hz] (400K, 26MHz, 52MHz, etc) */
+ uint32_t request_freq;
+ /* current MMC clock[Hz] (the closest frequency supported by HW) */
+ uint32_t current_freq;
+
+ /* state flag */
+ /* presence status of the memory card */
+ HAL_MEMCARD_PRESENCE_STATUS card_present;
+
+ uint32_t card_power_enable;
+ uint32_t clock_enable;
+ /* True : initialize complete. */
+ uint32_t initialize;
+ /* True : sector access, FALSE : byte access */
+ uint32_t access_mode;
+ /* True : mount complete. */
+ uint32_t mount;
+ /* True : selected card. */
+ uint32_t selected;
+ /* 0: DMA, 1:PIO */
+ HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode;
+
+ /* loaded ISSW image No. ISSW have copy image. */
+ uint32_t image_num;
+ /* card state */
+ EMMC_R1_STATE current_state;
+ /* True : during command processing */
+ volatile uint32_t during_cmd_processing;
+ /* True : during transfer */
+ volatile uint32_t during_transfer;
+ /* True : during transfer (DMA) */
+ volatile uint32_t during_dma_transfer;
+ /* True : occurred DMAC error */
+ volatile uint32_t dma_error_flag;
+ /* force terminate flag */
+ volatile uint32_t force_terminate;
+ /* state machine blocking flag : True or False */
+ volatile uint32_t state_machine_blocking;
+ /* True : get partition access processing */
+ volatile uint32_t get_partition_access_flag;
+
+ EMMC_PARTITION_ID boot_partition_en; /* Boot partition */
+ EMMC_PARTITION_ID partition_access; /* Current access partition */
+
+ /* timeout */
+ uint32_t hs_timing;
+
+ /* read and write data timeout */
+ uint32_t data_timeout;
+
+ /* retry */
+ uint32_t retries_after_fail;
+
+ /* interrupt */
+ volatile uint32_t int_event1; /* interrupt SD_INFO1 Event */
+ volatile uint32_t int_event2; /* interrupt SD_INFO2 Event */
+ volatile uint32_t dm_event1; /* interrupt DM_CM_INFO1 Event */
+ volatile uint32_t dm_event2; /* interrupt DM_CM_INFO2 Event */
+
+ /* response */
+ uint32_t *response; /* buffer ptr for executing command. */
+ uint32_t r1_card_status; /* R1 response data */
+ uint32_t r3_ocr; /* R3 response data */
+ uint32_t r4_resp; /* R4 response data */
+ uint32_t r5_resp; /* R5 response data */
+
+ /* True : clock mode is low. (MMC clock = Max26MHz) */
+ uint32_t low_clock_mode_enable;
+
+ uint32_t reserved2;
+ uint32_t reserved3;
+ uint32_t reserved4;
+
+ /* CSD registers (4byte align) */
+ uint8_t csd_data[EMMC_MAX_CSD_LENGTH] /* CSD */
+ __attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
+ /* CID registers (4byte align) */
+ uint8_t cid_data[EMMC_MAX_CID_LENGTH] /* CID */
+ __attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
+ /* EXT CSD registers (8byte align) */
+ uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH] /* EXT_CSD */
+ __attribute__ ((aligned(EMMC_BUF_REG_ALIGNED)));
+ /* Response registers (4byte align) */
+ uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH] /* other response */
+ __attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
+} st_mmc_base;
+
+typedef int (*func) (void);
+
+uint32_t emmc_get_csd_time(void);
+
+#define MMC_DEBUG
+#endif /* EMMC_STD_H */
diff --git a/drivers/renesas/rcar/emmc/emmc_utility.c b/drivers/renesas/common/emmc/emmc_utility.c
index 39d9ede5ac..2e88abc75f 100644
--- a/drivers/renesas/rcar/emmc/emmc_utility.c
+++ b/drivers/renesas/common/emmc/emmc_utility.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,10 +7,10 @@
#include <common/debug.h>
#include "emmc_config.h"
+#include "emmc_def.h"
#include "emmc_hal.h"
-#include "emmc_std.h"
#include "emmc_registers.h"
-#include "emmc_def.h"
+#include "emmc_std.h"
static const uint32_t cmd_reg_hw[EMMC_CMD_MAX + 1] = {
0x00000000, /* CMD0 */
@@ -97,8 +97,8 @@ uint32_t emmc_bit_field(uint8_t *data, uint32_t top, uint32_t bottom)
value =
(uint32_t) ((data[index_top] << 24) |
(data[index_top + 1] << 16) |
- (data[index_top + 2] << 8) | data[index_top +
- 3]);
+ (data[index_top + 2] << 8) |
+ data[index_top + 3]);
}
value = ((value >> (bottom & 0x07)) & ((1 << (top - bottom + 1)) - 1));
@@ -150,7 +150,7 @@ void emmc_make_nontrans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg)
mmc_drv_obj.response = &mmc_drv_obj.r1_card_status;
break;
case HAL_MEMCARD_RESPONSE_R1b:
- mmc_drv_obj.cmd_info.hw |= BIT10; /* bit10 = R1 busy bit */
+ mmc_drv_obj.cmd_info.hw |= BIT10; /* bit10 = R1 busy bit */
mmc_drv_obj.response = &mmc_drv_obj.r1_card_status;
break;
case HAL_MEMCARD_RESPONSE_R2:
diff --git a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c b/drivers/renesas/common/iic_dvfs/iic_dvfs.c
index 28b56c10ec..e1c9a5bd4d 100644
--- a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
+++ b/drivers/renesas/common/iic_dvfs/iic_dvfs.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,59 +7,59 @@
#include <common/debug.h>
#include <lib/mmio.h>
-#include "rcar_def.h"
#include "cpg_registers.h"
#include "iic_dvfs.h"
+#include "rcar_def.h"
#include "rcar_private.h"
#define DVFS_RETRY_MAX (2U)
-#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_0 (0x07)
-#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_1 (0x09)
-#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_2 (0x0B)
-#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_3 (0x0E)
-#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_E (0x15)
-
-#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_0 (0x01)
-#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_1 (0x02)
-#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_2 (0x03)
-#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_3 (0x05)
-#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_E (0x07)
-
-#define CPG_BIT_SMSTPCR9_DVFS (0x04000000)
-
-#define IIC_DVFS_REG_BASE (0xE60B0000)
-#define IIC_DVFS_REG_ICDR (IIC_DVFS_REG_BASE + 0x0000)
-#define IIC_DVFS_REG_ICCR (IIC_DVFS_REG_BASE + 0x0004)
-#define IIC_DVFS_REG_ICSR (IIC_DVFS_REG_BASE + 0x0008)
-#define IIC_DVFS_REG_ICIC (IIC_DVFS_REG_BASE + 0x000C)
-#define IIC_DVFS_REG_ICCL (IIC_DVFS_REG_BASE + 0x0010)
-#define IIC_DVFS_REG_ICCH (IIC_DVFS_REG_BASE + 0x0014)
-
-#define IIC_DVFS_BIT_ICSR_BUSY (0x10)
-#define IIC_DVFS_BIT_ICSR_AL (0x08)
-#define IIC_DVFS_BIT_ICSR_TACK (0x04)
-#define IIC_DVFS_BIT_ICSR_WAIT (0x02)
-#define IIC_DVFS_BIT_ICSR_DTE (0x01)
-
-#define IIC_DVFS_BIT_ICCR_ENABLE (0x80)
-#define IIC_DVFS_SET_ICCR_START (0x94)
-#define IIC_DVFS_SET_ICCR_STOP (0x90)
-#define IIC_DVFS_SET_ICCR_RETRANSMISSION (0x94)
-#define IIC_DVFS_SET_ICCR_CHANGE (0x81)
-#define IIC_DVFS_SET_ICCR_STOP_READ (0xC0)
-
-#define IIC_DVFS_BIT_ICIC_TACKE (0x04)
-#define IIC_DVFS_BIT_ICIC_WAITE (0x02)
-#define IIC_DVFS_BIT_ICIC_DTEE (0x01)
-
-#define DVFS_READ_MODE (0x01)
-#define DVFS_WRITE_MODE (0x00)
-
-#define IIC_DVFS_SET_DUMMY (0x52)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_0 (0x07U)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_1 (0x09U)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_2 (0x0BU)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_3 (0x0EU)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_E (0x15U)
+
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_0 (0x01U)
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_1 (0x02U)
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_2 (0x03U)
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_3 (0x05U)
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_E (0x07U)
+
+#define CPG_BIT_SMSTPCR9_DVFS (0x04000000U)
+
+#define IIC_DVFS_REG_BASE (0xE60B0000U)
+#define IIC_DVFS_REG_ICDR (IIC_DVFS_REG_BASE + 0x0000U)
+#define IIC_DVFS_REG_ICCR (IIC_DVFS_REG_BASE + 0x0004U)
+#define IIC_DVFS_REG_ICSR (IIC_DVFS_REG_BASE + 0x0008U)
+#define IIC_DVFS_REG_ICIC (IIC_DVFS_REG_BASE + 0x000CU)
+#define IIC_DVFS_REG_ICCL (IIC_DVFS_REG_BASE + 0x0010U)
+#define IIC_DVFS_REG_ICCH (IIC_DVFS_REG_BASE + 0x0014U)
+
+#define IIC_DVFS_BIT_ICSR_BUSY (0x10U)
+#define IIC_DVFS_BIT_ICSR_AL (0x08U)
+#define IIC_DVFS_BIT_ICSR_TACK (0x04U)
+#define IIC_DVFS_BIT_ICSR_WAIT (0x02U)
+#define IIC_DVFS_BIT_ICSR_DTE (0x01U)
+
+#define IIC_DVFS_BIT_ICCR_ENABLE (0x80U)
+#define IIC_DVFS_SET_ICCR_START (0x94U)
+#define IIC_DVFS_SET_ICCR_STOP (0x90U)
+#define IIC_DVFS_SET_ICCR_RETRANSMISSION (0x94U)
+#define IIC_DVFS_SET_ICCR_CHANGE (0x81U)
+#define IIC_DVFS_SET_ICCR_STOP_READ (0xC0U)
+
+#define IIC_DVFS_BIT_ICIC_TACKE (0x04U)
+#define IIC_DVFS_BIT_ICIC_WAITE (0x02U)
+#define IIC_DVFS_BIT_ICIC_DTEE (0x01U)
+
+#define DVFS_READ_MODE (0x01U)
+#define DVFS_WRITE_MODE (0x00U)
+
+#define IIC_DVFS_SET_DUMMY (0x52U)
#define IIC_DVFS_SET_BUSY_LOOP (500000000U)
-typedef enum {
+enum dvfs_state_t {
DVFS_START = 0,
DVFS_STOP,
DVFS_RETRANSMIT,
@@ -69,9 +69,9 @@ typedef enum {
DVFS_SET_SLAVE,
DVFS_WRITE_ADDR,
DVFS_WRITE_DATA,
- DVFS_CHANGE_SEND_TO_RECIEVE,
+ DVFS_CHANGE_SEND_TO_RECEIVE,
DVFS_DONE,
-} DVFS_STATE_T;
+};
#define DVFS_PROCESS (1)
#define DVFS_COMPLETE (0)
@@ -79,26 +79,26 @@ typedef enum {
#if IMAGE_BL31
#define IIC_DVFS_FUNC(__name, ...) \
-static int32_t __attribute__ ((section (".system_ram"))) \
+static int32_t __attribute__ ((section(".system_ram"))) \
dvfs_ ##__name(__VA_ARGS__)
#define RCAR_DVFS_API(__name, ...) \
-int32_t __attribute__ ((section (".system_ram"))) \
+int32_t __attribute__ ((section(".system_ram"))) \
rcar_iic_dvfs_ ##__name(__VA_ARGS__)
#else
-#define IIC_DVFS_FUNC(__name, ...) \
+#define IIC_DVFS_FUNC(__name, ...) \
static int32_t dvfs_ ##__name(__VA_ARGS__)
#define RCAR_DVFS_API(__name, ...) \
int32_t rcar_iic_dvfs_ ##__name(__VA_ARGS__)
#endif
-IIC_DVFS_FUNC(check_error, DVFS_STATE_T *state, uint32_t *err, uint8_t mode)
+IIC_DVFS_FUNC(check_error, enum dvfs_state_t *state, uint32_t *err, uint8_t mode)
{
- uint8_t icsr_al = 0, icsr_tack = 0;
+ uint8_t icsr_al = 0U, icsr_tack = 0U;
uint8_t reg, stop;
- uint32_t i = 0;
+ uint32_t i = 0U;
stop = mode == DVFS_READ_MODE ? IIC_DVFS_SET_ICCR_STOP_READ :
IIC_DVFS_SET_ICCR_STOP;
@@ -107,43 +107,48 @@ IIC_DVFS_FUNC(check_error, DVFS_STATE_T *state, uint32_t *err, uint8_t mode)
icsr_al = (reg & IIC_DVFS_BIT_ICSR_AL) == IIC_DVFS_BIT_ICSR_AL;
icsr_tack = (reg & IIC_DVFS_BIT_ICSR_TACK) == IIC_DVFS_BIT_ICSR_TACK;
- if (icsr_al == 0 && icsr_tack == 0)
+ if (icsr_al == 0U && icsr_tack == 0U) {
return DVFS_PROCESS;
+ }
if (icsr_al) {
reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_AL;
mmio_write_8(IIC_DVFS_REG_ICSR, reg);
- if (*state == DVFS_SET_SLAVE)
+ if (*state == DVFS_SET_SLAVE) {
mmio_write_8(IIC_DVFS_REG_ICDR, IIC_DVFS_SET_DUMMY);
+ }
do {
reg = mmio_read_8(IIC_DVFS_REG_ICSR) &
IIC_DVFS_BIT_ICSR_WAIT;
- } while (reg == 0);
+ } while (reg == 0U);
mmio_write_8(IIC_DVFS_REG_ICCR, stop);
reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
mmio_write_8(IIC_DVFS_REG_ICSR, reg);
- i = 0;
+ i = 0U;
do {
reg = mmio_read_8(IIC_DVFS_REG_ICSR) &
IIC_DVFS_BIT_ICSR_BUSY;
- if (reg == 0)
+ if (reg == 0U) {
break;
+ }
- if (i++ > IIC_DVFS_SET_BUSY_LOOP)
+ if (i++ > IIC_DVFS_SET_BUSY_LOOP) {
panic();
+ }
- } while (1);
+ } while (true);
mmio_write_8(IIC_DVFS_REG_ICCR, 0x00U);
(*err)++;
- if (*err > DVFS_RETRY_MAX)
+ if (*err > DVFS_RETRY_MAX) {
return DVFS_ERROR;
+ }
*state = DVFS_START;
@@ -161,24 +166,26 @@ IIC_DVFS_FUNC(check_error, DVFS_STATE_T *state, uint32_t *err, uint8_t mode)
reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_TACK;
mmio_write_8(IIC_DVFS_REG_ICSR, reg);
- i = 0;
- while ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) != 0) {
- if (i++ > IIC_DVFS_SET_BUSY_LOOP)
+ i = 0U;
+ while ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) != 0U) {
+ if (i++ > IIC_DVFS_SET_BUSY_LOOP) {
panic();
+ }
}
- mmio_write_8(IIC_DVFS_REG_ICCR, 0);
+ mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
(*err)++;
- if (*err > DVFS_RETRY_MAX)
+ if (*err > DVFS_RETRY_MAX) {
return DVFS_ERROR;
+ }
*state = DVFS_START;
return DVFS_PROCESS;
}
-IIC_DVFS_FUNC(start, DVFS_STATE_T * state)
+IIC_DVFS_FUNC(start, enum dvfs_state_t *state)
{
uint8_t iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_E;
uint8_t icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_E;
@@ -190,8 +197,9 @@ IIC_DVFS_FUNC(start, DVFS_STATE_T * state)
mmio_write_8(IIC_DVFS_REG_ICCR, mode);
lsi_product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
- if (lsi_product == PRR_PRODUCT_E3)
+ if (lsi_product == PRR_PRODUCT_E3) {
goto start;
+ }
reg = mmio_read_32(RCAR_MODEMR) & CHECK_MD13_MD14;
switch (reg) {
@@ -228,19 +236,21 @@ start:
return result;
}
-IIC_DVFS_FUNC(set_slave, DVFS_STATE_T * state, uint32_t *err, uint8_t slave)
+IIC_DVFS_FUNC(set_slave, enum dvfs_state_t *state, uint32_t *err, uint8_t slave)
{
uint8_t mode;
int32_t result;
uint8_t address;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
- if (mode != IIC_DVFS_BIT_ICSR_DTE)
+ if (mode != IIC_DVFS_BIT_ICSR_DTE) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
mmio_write_8(IIC_DVFS_REG_ICIC, mode);
@@ -253,18 +263,20 @@ IIC_DVFS_FUNC(set_slave, DVFS_STATE_T * state, uint32_t *err, uint8_t slave)
return result;
}
-IIC_DVFS_FUNC(write_addr, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_addr)
+IIC_DVFS_FUNC(write_addr, enum dvfs_state_t *state, uint32_t *err, uint8_t reg_addr)
{
uint8_t mode;
int32_t result;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr);
@@ -276,18 +288,21 @@ IIC_DVFS_FUNC(write_addr, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_addr)
return result;
}
-IIC_DVFS_FUNC(write_data, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_data)
+IIC_DVFS_FUNC(write_data, enum dvfs_state_t *state, uint32_t *err,
+ uint8_t reg_data)
{
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICDR, reg_data);
@@ -299,18 +314,20 @@ IIC_DVFS_FUNC(write_data, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_data)
return result;
}
-IIC_DVFS_FUNC(stop, DVFS_STATE_T *state, uint32_t *err)
+IIC_DVFS_FUNC(stop, enum dvfs_state_t *state, uint32_t *err)
{
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP);
@@ -326,32 +343,35 @@ IIC_DVFS_FUNC(done, void)
{
uint32_t i;
- for (i = 0; i < IIC_DVFS_SET_BUSY_LOOP; i++) {
- if (mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY)
+ for (i = 0U; i < IIC_DVFS_SET_BUSY_LOOP; i++) {
+ if ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) != 0U) {
continue;
+ }
goto done;
}
panic();
done:
- mmio_write_8(IIC_DVFS_REG_ICCR, 0);
+ mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
return DVFS_COMPLETE;
}
-IIC_DVFS_FUNC(write_reg_addr_read, DVFS_STATE_T *state, uint32_t *err,
- uint8_t reg_addr)
+IIC_DVFS_FUNC(write_reg_addr_read, enum dvfs_state_t *state, uint32_t *err,
+ uint8_t reg_addr)
{
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr);
@@ -363,18 +383,20 @@ IIC_DVFS_FUNC(write_reg_addr_read, DVFS_STATE_T *state, uint32_t *err,
return result;
}
-IIC_DVFS_FUNC(retransmit, DVFS_STATE_T *state, uint32_t *err)
+IIC_DVFS_FUNC(retransmit, enum dvfs_state_t *state, uint32_t *err)
{
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_RETRANSMISSION);
@@ -389,20 +411,22 @@ IIC_DVFS_FUNC(retransmit, DVFS_STATE_T *state, uint32_t *err)
return result;
}
-IIC_DVFS_FUNC(set_slave_read, DVFS_STATE_T *state, uint32_t *err,
- uint8_t slave)
+IIC_DVFS_FUNC(set_slave_read, enum dvfs_state_t *state, uint32_t *err,
+ uint8_t slave)
{
uint8_t address;
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
- if (mode != IIC_DVFS_BIT_ICSR_DTE)
+ if (mode != IIC_DVFS_BIT_ICSR_DTE) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
mmio_write_8(IIC_DVFS_REG_ICIC, mode);
@@ -410,23 +434,25 @@ IIC_DVFS_FUNC(set_slave_read, DVFS_STATE_T *state, uint32_t *err,
address = ((uint8_t) (slave << 1) + DVFS_READ_MODE);
mmio_write_8(IIC_DVFS_REG_ICDR, address);
- *state = DVFS_CHANGE_SEND_TO_RECIEVE;
+ *state = DVFS_CHANGE_SEND_TO_RECEIVE;
return result;
}
-IIC_DVFS_FUNC(change_send_to_recieve, DVFS_STATE_T *state, uint32_t *err)
+IIC_DVFS_FUNC(change_send_to_receive, enum dvfs_state_t *state, uint32_t *err)
{
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_CHANGE);
@@ -438,18 +464,20 @@ IIC_DVFS_FUNC(change_send_to_recieve, DVFS_STATE_T *state, uint32_t *err)
return result;
}
-IIC_DVFS_FUNC(stop_read, DVFS_STATE_T *state, uint32_t *err)
+IIC_DVFS_FUNC(stop_read, enum dvfs_state_t *state, uint32_t *err)
{
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_READ_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP_READ);
@@ -464,13 +492,14 @@ IIC_DVFS_FUNC(stop_read, DVFS_STATE_T *state, uint32_t *err)
return result;
}
-IIC_DVFS_FUNC(read, DVFS_STATE_T *state, uint8_t *reg_data)
+IIC_DVFS_FUNC(read, enum dvfs_state_t *state, uint8_t *reg_data)
{
uint8_t mode;
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
- if (mode != IIC_DVFS_BIT_ICSR_DTE)
+ if (mode != IIC_DVFS_BIT_ICSR_DTE) {
return DVFS_PROCESS;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
mmio_write_8(IIC_DVFS_REG_ICIC, mode);
@@ -483,12 +512,12 @@ IIC_DVFS_FUNC(read, DVFS_STATE_T *state, uint8_t *reg_data)
RCAR_DVFS_API(send, uint8_t slave, uint8_t reg_addr, uint8_t reg_data)
{
- DVFS_STATE_T state = DVFS_START;
+ enum dvfs_state_t state = DVFS_START;
int32_t result = DVFS_PROCESS;
- uint32_t err = 0;
+ uint32_t err = 0U;
mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
- mmio_write_8(IIC_DVFS_REG_ICCR, 0);
+ mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
again:
switch (state) {
case DVFS_START:
@@ -514,20 +543,21 @@ again:
break;
}
- if (result == DVFS_PROCESS)
+ if (result == DVFS_PROCESS) {
goto again;
+ }
return result;
}
RCAR_DVFS_API(receive, uint8_t slave, uint8_t reg, uint8_t *data)
{
- DVFS_STATE_T state = DVFS_START;
+ enum dvfs_state_t state = DVFS_START;
int32_t result = DVFS_PROCESS;
- uint32_t err = 0;
+ uint32_t err = 0U;
mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
- mmio_write_8(IIC_DVFS_REG_ICCR, 0);
+ mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
again:
switch (state) {
case DVFS_START:
@@ -545,8 +575,8 @@ again:
case DVFS_SET_SLAVE_READ:
result = dvfs_set_slave_read(&state, &err, slave);
break;
- case DVFS_CHANGE_SEND_TO_RECIEVE:
- result = dvfs_change_send_to_recieve(&state, &err);
+ case DVFS_CHANGE_SEND_TO_RECEIVE:
+ result = dvfs_change_send_to_receive(&state, &err);
break;
case DVFS_STOP_READ:
result = dvfs_stop_read(&state, &err);
@@ -562,8 +592,9 @@ again:
break;
}
- if (result == DVFS_PROCESS)
+ if (result == DVFS_PROCESS) {
goto again;
+ }
return result;
}
diff --git a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.h b/drivers/renesas/common/iic_dvfs/iic_dvfs.h
index 2dec58f647..244c06cfdc 100644
--- a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.h
+++ b/drivers/renesas/common/iic_dvfs/iic_dvfs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,14 +8,14 @@
#define IIC_DVFS_H
/* PMIC slave */
-#define PMIC (0x30)
-#define BKUP_MODE_CNT (0x20)
-#define DVFS_SET_VID (0x54)
-#define REG_KEEP10 (0x79)
+#define PMIC (0x30U)
+#define BKUP_MODE_CNT (0x20U)
+#define DVFS_SET_VID (0x54U)
+#define REG_KEEP10 (0x79U)
/* EEPROM slave */
-#define EEPROM (0x50)
-#define BOARD_ID (0x70)
+#define EEPROM (0x50U)
+#define BOARD_ID (0x70U)
int32_t rcar_iic_dvfs_receive(uint8_t slave, uint8_t reg, uint8_t *data);
int32_t rcar_iic_dvfs_send(uint8_t slave, uint8_t regr, uint8_t data);
diff --git a/drivers/renesas/rcar/io/io_common.h b/drivers/renesas/common/io/io_common.h
index 6eb77777a9..6eb77777a9 100644
--- a/drivers/renesas/rcar/io/io_common.h
+++ b/drivers/renesas/common/io/io_common.h
diff --git a/drivers/renesas/rcar/io/io_emmcdrv.c b/drivers/renesas/common/io/io_emmcdrv.c
index 84240d2606..c2b5f7c089 100644
--- a/drivers/renesas/rcar/io/io_emmcdrv.c
+++ b/drivers/renesas/common/io/io_emmcdrv.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,13 +10,13 @@
#include <drivers/io/io_driver.h>
#include <drivers/io/io_storage.h>
-#include "io_common.h"
-#include "io_emmcdrv.h"
-#include "io_private.h"
#include "emmc_config.h"
+#include "emmc_def.h"
#include "emmc_hal.h"
#include "emmc_std.h"
-#include "emmc_def.h"
+#include "io_common.h"
+#include "io_emmcdrv.h"
+#include "io_private.h"
static int32_t emmcdrv_dev_open(const uintptr_t spec __attribute__ ((unused)),
io_dev_info_t **dev_info);
@@ -41,8 +41,9 @@ static io_type_t device_type_emmcdrv(void)
static int32_t emmcdrv_block_seek(io_entity_t *entity, int32_t mode,
signed long long offset)
{
- if (mode != IO_SEEK_SET)
+ if (mode != IO_SEEK_SET) {
return IO_FAIL;
+ }
((file_state_t *) entity->info)->file_pos = offset;
@@ -64,12 +65,14 @@ static int32_t emmcdrv_block_read(io_entity_t *entity, uintptr_t buffer,
current_file.partition, current_file.file_pos,
sector_add, length, sector_num);
- if ((buffer + length - 1U) <= (uintptr_t)UINT32_MAX)
+ if ((buffer + length - 1U) <= (uintptr_t)UINT32_MAX) {
emmc_dma = LOADIMAGE_FLAGS_DMA_ENABLE;
+ }
if (emmc_read_sector((uint32_t *) buffer, sector_add, sector_num,
- emmc_dma) != EMMC_SUCCESS)
+ emmc_dma) != EMMC_SUCCESS) {
result = IO_FAIL;
+ }
*length_read = length;
fp->file_pos += (signed long long)length;
@@ -92,8 +95,8 @@ static int32_t emmcdrv_block_open(io_dev_info_t *dev_info,
if (emmcdrv_bootpartition == PARTITION_ID_USER) {
emmcdrv_bootpartition = mmc_drv_obj.boot_partition_en;
- if ((PARTITION_ID_BOOT_1 == emmcdrv_bootpartition) ||
- (PARTITION_ID_BOOT_2 == emmcdrv_bootpartition)) {
+ if ((emmcdrv_bootpartition == PARTITION_ID_BOOT_1) ||
+ (emmcdrv_bootpartition == PARTITION_ID_BOOT_2)) {
current_file.partition = emmcdrv_bootpartition;
NOTICE("BL2: eMMC boot from partition %d\n",
@@ -103,16 +106,18 @@ static int32_t emmcdrv_block_open(io_dev_info_t *dev_info,
return IO_FAIL;
}
- if ((PARTITION_ID_USER == block_spec->partition) ||
- (PARTITION_ID_BOOT_1 == block_spec->partition) ||
- (PARTITION_ID_BOOT_2 == block_spec->partition))
+ if ((block_spec->partition == PARTITION_ID_USER) ||
+ (block_spec->partition == PARTITION_ID_BOOT_1) ||
+ (block_spec->partition == PARTITION_ID_BOOT_2)) {
current_file.partition = block_spec->partition;
- else
+ } else {
current_file.partition = emmcdrv_bootpartition;
+ }
done:
- if (emmc_select_partition(current_file.partition) != EMMC_SUCCESS)
+ if (emmc_select_partition(current_file.partition) != EMMC_SUCCESS) {
return IO_FAIL;
+ }
entity->info = (uintptr_t) &current_file;
@@ -166,8 +171,9 @@ int32_t rcar_register_io_dev_emmcdrv(const io_dev_connector_t **dev_con)
int32_t rc;
rc = io_register_device(&emmcdrv_dev_info);
- if (rc == IO_SUCCESS)
+ if (rc == IO_SUCCESS) {
*dev_con = &emmcdrv_dev_connector;
+ }
return rc;
}
diff --git a/drivers/renesas/rcar/io/io_emmcdrv.h b/drivers/renesas/common/io/io_emmcdrv.h
index 95070f24b6..95070f24b6 100644
--- a/drivers/renesas/rcar/io/io_emmcdrv.h
+++ b/drivers/renesas/common/io/io_emmcdrv.h
diff --git a/drivers/renesas/rcar/io/io_memdrv.c b/drivers/renesas/common/io/io_memdrv.c
index 7e8c1d3a65..1f31c0fb93 100644
--- a/drivers/renesas/rcar/io/io_memdrv.c
+++ b/drivers/renesas/common/io/io_memdrv.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,8 +11,8 @@
#include <drivers/io/io_storage.h>
#include "io_common.h"
-#include "io_private.h"
#include "io_memdrv.h"
+#include "io_private.h"
#include "rcar_def.h"
extern void rcar_dma_exec(uintptr_t dst, uint32_t src, uint32_t len);
@@ -21,7 +21,8 @@ static int32_t memdrv_dev_open(const uintptr_t dev __attribute__ ((unused)),
io_dev_info_t **dev_info);
static int32_t memdrv_dev_close(io_dev_info_t *dev_info);
-/* As we need to be able to keep state for seek, only one file can be open
+/*
+ * As we need to be able to keep state for seek, only one file can be open
* at a time. Make this a structure and point to the entity->info. When we
* can malloc memory we can change this to support more open files.
*/
@@ -43,12 +44,14 @@ static int32_t memdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
{
const io_drv_spec_t *block_spec = (io_drv_spec_t *) spec;
- /* Since we need to track open state for seek() we only allow one open
+ /*
+ * Since we need to track open state for seek() we only allow one open
* spec at a time. When we have dynamic memory we can malloc and set
* entity->info.
*/
- if (current_file.in_use != 0U)
+ if (current_file.in_use != 0U) {
return IO_RESOURCES_EXHAUSTED;
+ }
/* File cursor offset for seek and incremental reads etc. */
current_file.base = block_spec->offset;
@@ -63,8 +66,9 @@ static int32_t memdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
static int32_t memdrv_block_seek(io_entity_t *entity, int32_t mode,
signed long long offset)
{
- if (mode != IO_SEEK_SET)
+ if (mode != IO_SEEK_SET) {
return IO_FAIL;
+ }
((file_state_t *) entity->info)->file_pos = offset;
@@ -142,8 +146,9 @@ int32_t rcar_register_io_dev_memdrv(const io_dev_connector_t **dev_con)
int32_t result;
result = io_register_device(&memdrv_dev_info);
- if (result == IO_SUCCESS)
+ if (result == IO_SUCCESS) {
*dev_con = &memdrv_dev_connector;
+ }
return result;
}
diff --git a/drivers/renesas/rcar/io/io_memdrv.h b/drivers/renesas/common/io/io_memdrv.h
index 90e68123ee..90e68123ee 100644
--- a/drivers/renesas/rcar/io/io_memdrv.h
+++ b/drivers/renesas/common/io/io_memdrv.h
diff --git a/drivers/renesas/rcar/io/io_private.h b/drivers/renesas/common/io/io_private.h
index 207523a73e..207523a73e 100644
--- a/drivers/renesas/rcar/io/io_private.h
+++ b/drivers/renesas/common/io/io_private.h
diff --git a/drivers/renesas/rcar/io/io_rcar.c b/drivers/renesas/common/io/io_rcar.c
index b82c510780..c3e8319de4 100644
--- a/drivers/renesas/rcar/io/io_rcar.c
+++ b/drivers/renesas/common/io/io_rcar.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,8 +8,6 @@
#include <stdint.h>
#include <string.h>
-#include <platform_def.h>
-
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
@@ -24,6 +22,7 @@
#include "io_rcar.h"
#include "io_common.h"
#include "io_private.h"
+#include <platform_def.h>
extern int32_t plat_get_drv_source(uint32_t id, uintptr_t *dev,
uintptr_t *image_spec);
@@ -39,7 +38,8 @@ typedef struct {
} plat_rcar_name_offset_t;
typedef struct {
- /* Put position above the struct to allow {0} on static init.
+ /*
+ * Put position above the struct to allow {0} on static init.
* It is a workaround for a known bug in GCC
* http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119
*/
@@ -59,7 +59,7 @@ typedef struct {
#define RCAR_ATTR_SET_ISNOLOAD(a) (((a) & 0x1) << 16U)
#define RCAR_ATTR_SET_CERTOFF(a) (((a) & 0xF) << 8U)
#define RCAR_ATTR_SET_ALL(a, b, c) ((uint32_t)(RCAR_ATTR_SET_CALCADDR(a) |\
- RCAR_ATTR_SET_ISNOLOAD(b) | \
+ RCAR_ATTR_SET_ISNOLOAD(b) |\
RCAR_ATTR_SET_CERTOFF(c)))
#define RCAR_ATTR_GET_CALCADDR(a) ((a) & 0xFU)
@@ -136,9 +136,11 @@ int32_t rcar_get_certificate(const int32_t name, uint32_t *cert)
{
#if TRUSTED_BOARD_BOOT
int32_t i;
+
for (i = 0; i < ARRAY_SIZE(cert_offset); i++) {
- if (name != cert_offset[i].name)
+ if (name != cert_offset[i].name) {
continue;
+ }
*cert = RCAR_CERT_SIZE;
*cert *= RCAR_ATTR_GET_CERTOFF(cert_offset[i].attr);
@@ -157,12 +159,14 @@ static int32_t file_to_offset(const int32_t name, uintptr_t *offset,
int32_t i;
for (i = 0; i < ARRAY_SIZE(name_offset); i++) {
- if (name != name_offset[i].name)
+ if (name != name_offset[i].name) {
continue;
+ }
addr = RCAR_ATTR_GET_CALCADDR(name_offset[i].attr);
- if (rcar_image_number + 2 < addr)
+ if (rcar_image_number + 2U < addr) {
continue;
+ }
*offset = rcar_image_header[addr];
*cert = RCAR_CERT_SIZE;
@@ -175,8 +179,9 @@ static int32_t file_to_offset(const int32_t name, uintptr_t *offset,
#if TRUSTED_BOARD_BOOT
for (i = 0; i < ARRAY_SIZE(cert_offset); i++) {
- if (name != cert_offset[i].name)
+ if (name != cert_offset[i].name) {
continue;
+ }
*no_load = RCAR_ATTR_GET_ISNOLOAD(cert_offset[i].attr);
*partition = 0U;
@@ -282,8 +287,9 @@ static int32_t check_load_area(uintptr_t dst, uintptr_t len)
result = IO_FAIL;
}
done:
- if (result == IO_FAIL)
+ if (result == IO_FAIL) {
ERROR("BL2: Out of range : dst=0x%lx len=0x%lx\n", dst, len);
+ }
return result;
}
@@ -307,14 +313,15 @@ static int32_t load_bl33x(void)
BL338_IMAGE_ID
};
- if (loaded != IO_NOT_SUPPORTED)
+ if (loaded != IO_NOT_SUPPORTED) {
return loaded;
+ }
for (i = 1; i < rcar_image_number; i++) {
rc = file_to_offset(img[i], &offset, &cert, &noload,
&partition);
if (rc != IO_SUCCESS) {
- WARN("load_bl33x: failed to get offset\n");
+ WARN("%s: failed to get offset\n", __func__);
loaded = IO_FAIL;
return loaded;
}
@@ -324,34 +331,34 @@ static int32_t load_bl33x(void)
rc = io_open(rcar_handle, rcar_spec, &handle);
if (rc != IO_SUCCESS) {
- WARN("Failed to open FIP (%i)\n", rc);
+ WARN("%s: Failed to open FIP (%i)\n", __func__, rc);
loaded = IO_FAIL;
return loaded;
}
rc = io_seek(handle, IO_SEEK_SET, offset);
if (rc != IO_SUCCESS) {
- WARN("load_bl33x: failed to seek\n");
+ WARN("%s: failed to seek\n", __func__);
loaded = IO_FAIL;
return loaded;
}
rc = check_load_area(dst, len);
if (rc != IO_SUCCESS) {
- WARN("load_bl33x: check load area\n");
+ WARN("%s: check load area\n", __func__);
loaded = IO_FAIL;
return loaded;
}
rc = io_read(handle, dst, len, &cnt);
if (rc != IO_SUCCESS) {
- WARN("load_bl33x: failed to read\n");
+ WARN("%s: failed to read\n", __func__);
loaded = IO_FAIL;
return loaded;
}
#if TRUSTED_BOARD_BOOT
rc = auth_mod_verify_img(img[i], (void *)dst, len);
- if (rc) {
+ if (rc != 0) {
memset((void *)dst, 0x00, len);
loaded = IO_FAIL;
return loaded;
@@ -367,8 +374,7 @@ static int32_t load_bl33x(void)
static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name)
{
- uint64_t header[64] __aligned(FLASH_TRANS_SIZE_UNIT) = {
- 0};
+ uint64_t header[64] __aligned(FLASH_TRANS_SIZE_UNIT) = {0UL};
uintptr_t handle;
ssize_t offset;
uint32_t i;
@@ -382,8 +388,9 @@ static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name)
return IO_FAIL;
}
- if (RCAR_CERT_LOAD == rcar_cert_load)
+ if (rcar_cert_load == RCAR_CERT_LOAD) {
return IO_SUCCESS;
+ }
rc = io_open(rcar_handle, rcar_spec, &handle);
if (rc != IO_SUCCESS) {
@@ -391,16 +398,18 @@ static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name)
return IO_FAIL;
}
- /* get start address list */
- /* [0] address num */
- /* [1] BL33-1 image address */
- /* [2] BL33-2 image address */
- /* [3] BL33-3 image address */
- /* [4] BL33-4 image address */
- /* [5] BL33-5 image address */
- /* [6] BL33-6 image address */
- /* [7] BL33-7 image address */
- /* [8] BL33-8 image address */
+ /*
+ * get start address list
+ * [0] address num
+ * [1] BL33-1 image address
+ * [2] BL33-2 image address
+ * [3] BL33-3 image address
+ * [4] BL33-4 image address
+ * [5] BL33-5 image address
+ * [6] BL33-6 image address
+ * [7] BL33-7 image address
+ * [8] BL33-8 image address
+ */
offset = name == EMMC_DEV_ID ? RCAR_EMMC_CERT_HEADER :
RCAR_FLASH_CERT_HEADER;
rc = io_seek(handle, IO_SEEK_SET, offset);
@@ -447,8 +456,9 @@ static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name)
rcar_cert_load = RCAR_CERT_LOAD;
error:
- if (rc != IO_SUCCESS)
+ if (rc != IO_SUCCESS) {
rc = IO_FAIL;
+ }
io_close(handle);
@@ -464,13 +474,15 @@ static int32_t rcar_file_open(io_dev_info_t *info, const uintptr_t file_spec,
uint32_t noload, cert, len;
int32_t rc;
- /* Only one file open at a time. We need to track state (ie, file
- * cursor position). Since the header lives at * offset zero, this entry
+ /*
+ * Only one file open at a time. We need to track state (ie, file
+ * cursor position). Since the header lives at offset zero, this entry
* should never be zero in an active file.
* Once the system supports dynamic memory allocation we will allow more
- * than one open file at a time. */
+ * than one open file at a time.
+ */
if (current_file.offset != 0U) {
- WARN("rcar_file_open : Only one open file at a time.\n");
+ WARN("%s: Only one open file at a time.\n", __func__);
return IO_RESOURCES_EXHAUSTED;
}
@@ -480,7 +492,7 @@ static int32_t rcar_file_open(io_dev_info_t *info, const uintptr_t file_spec,
return IO_FAIL;
}
- if (noload) {
+ if (noload != 0U) {
current_file.offset = 1;
current_file.dst = 0;
current_file.size = 1;
@@ -494,12 +506,10 @@ static int32_t rcar_file_open(io_dev_info_t *info, const uintptr_t file_spec,
rcar_read_certificate((uint64_t) cert, &len, &dst);
- /*----------------*
- * Baylibre: HACK *
- *----------------*/
- if (BL31_IMAGE_ID == spec->offset && len < RCAR_TRUSTED_SRAM_SIZE) {
- WARN("r-car ignoring the BL31 size from certificate,"
- "using RCAR_TRUSTED_SRAM_SIZE instead\n");
+ /* Baylibre: HACK */
+ if (spec->offset == BL31_IMAGE_ID && len < RCAR_TRUSTED_SRAM_SIZE) {
+ WARN("%s,%s\n", "r-car ignoring the BL31 size from certificate",
+ "using RCAR_TRUSTED_SRAM_SIZE instead");
len = RCAR_TRUSTED_SRAM_SIZE;
}
@@ -536,7 +546,7 @@ static int32_t rcar_file_read(io_entity_t *entity, uintptr_t buffer,
#else
static uint32_t load_bl33x_counter;
#endif
- if (current_file.no_load) {
+ if (current_file.no_load != 0U) {
*cnt = length;
return IO_SUCCESS;
}
@@ -551,14 +561,14 @@ static int32_t rcar_file_read(io_entity_t *entity, uintptr_t buffer,
rc = io_seek(handle, IO_SEEK_SET, offset);
if (rc != IO_SUCCESS) {
- WARN("rcar_file_read: failed to seek\n");
+ WARN("%s: failed to seek\n", __func__);
goto error;
}
if (load_bl33x_counter == RCAR_COUNT_LOAD_BL33) {
rc = check_load_area(buffer, length);
if (rc != IO_SUCCESS) {
- WARN("rcar_file_read: load area err\n");
+ WARN("%s: load area err\n", __func__);
goto error;
}
}
@@ -573,8 +583,9 @@ static int32_t rcar_file_read(io_entity_t *entity, uintptr_t buffer,
io_close(handle);
load_bl33x_counter += 1;
- if (load_bl33x_counter == RCAR_COUNT_LOAD_BL33X)
+ if (load_bl33x_counter == RCAR_COUNT_LOAD_BL33X) {
return load_bl33x();
+ }
return IO_SUCCESS;
error:
@@ -584,8 +595,9 @@ error:
static int32_t rcar_file_close(io_entity_t *entity)
{
- if (current_file.offset)
+ if (current_file.offset != 0U) {
memset(&current_file, 0, sizeof(current_file));
+ }
entity->info = 0U;
@@ -634,8 +646,9 @@ int32_t rcar_register_io_dev(const io_dev_connector_t **dev_con)
int32_t result;
result = io_register_device(&rcar_dev_info);
- if (result == IO_SUCCESS)
+ if (result == IO_SUCCESS) {
*dev_con = &rcar_dev_connector;
+ }
return result;
}
diff --git a/drivers/renesas/rcar/io/io_rcar.h b/drivers/renesas/common/io/io_rcar.h
index c26a617678..c26a617678 100644
--- a/drivers/renesas/rcar/io/io_rcar.h
+++ b/drivers/renesas/common/io/io_rcar.h
diff --git a/drivers/renesas/rcar/pfc/pfc_regs.h b/drivers/renesas/common/pfc_regs.h
index 418773366c..418773366c 100644
--- a/drivers/renesas/rcar/pfc/pfc_regs.h
+++ b/drivers/renesas/common/pfc_regs.h
diff --git a/drivers/renesas/rcar/pwrc/call_sram.S b/drivers/renesas/common/pwrc/call_sram.S
index aa8644cb98..aa8644cb98 100644
--- a/drivers/renesas/rcar/pwrc/call_sram.S
+++ b/drivers/renesas/common/pwrc/call_sram.S
diff --git a/drivers/renesas/rcar/pwrc/pwrc.c b/drivers/renesas/common/pwrc/pwrc.c
index 2ce6b61392..c0f015f04b 100644
--- a/drivers/renesas/rcar/pwrc/pwrc.c
+++ b/drivers/renesas/common/pwrc/pwrc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,10 +16,10 @@
#include <plat/common/platform.h>
#include "iic_dvfs.h"
-#include "rcar_def.h"
-#include "rcar_private.h"
#include "micro_delay.h"
#include "pwrc.h"
+#include "rcar_def.h"
+#include "rcar_private.h"
/*
* Someday there will be a generic power controller api. At the moment each
@@ -27,105 +27,105 @@
*/
RCAR_INSTANTIATE_LOCK
-#define WUP_IRQ_SHIFT (0U)
-#define WUP_FIQ_SHIFT (8U)
-#define WUP_CSD_SHIFT (16U)
-#define BIT_SOFTRESET (1U<<15)
-#define BIT_CA53_SCU (1U<<21)
-#define BIT_CA57_SCU (1U<<12)
-#define REQ_RESUME (1U<<1)
-#define REQ_OFF (1U<<0)
-#define STATUS_PWRUP (1U<<4)
-#define STATUS_PWRDOWN (1U<<0)
-#define STATE_CA57_CPU (27U)
-#define STATE_CA53_CPU (22U)
-#define MODE_L2_DOWN (0x00000002U)
-#define CPU_PWR_OFF (0x00000003U)
-#define RCAR_PSTR_MASK (0x00000003U)
-#define ST_ALL_STANDBY (0x00003333U)
+#define WUP_IRQ_SHIFT (0U)
+#define WUP_FIQ_SHIFT (8U)
+#define WUP_CSD_SHIFT (16U)
+#define BIT_SOFTRESET (1U << 15)
+#define BIT_CA53_SCU (1U << 21)
+#define BIT_CA57_SCU (1U << 12)
+#define REQ_RESUME (1U << 1)
+#define REQ_OFF (1U << 0)
+#define STATUS_PWRUP (1U << 4)
+#define STATUS_PWRDOWN (1U << 0)
+#define STATE_CA57_CPU (27U)
+#define STATE_CA53_CPU (22U)
+#define MODE_L2_DOWN (0x00000002U)
+#define CPU_PWR_OFF (0x00000003U)
+#define RCAR_PSTR_MASK (0x00000003U)
+#define ST_ALL_STANDBY (0x00003333U)
/* Suspend to ram */
-#define DBSC4_REG_BASE (0xE6790000U)
-#define DBSC4_REG_DBSYSCNT0 (DBSC4_REG_BASE + 0x0100U)
-#define DBSC4_REG_DBACEN (DBSC4_REG_BASE + 0x0200U)
-#define DBSC4_REG_DBCMD (DBSC4_REG_BASE + 0x0208U)
-#define DBSC4_REG_DBRFEN (DBSC4_REG_BASE + 0x0204U)
-#define DBSC4_REG_DBWAIT (DBSC4_REG_BASE + 0x0210U)
-#define DBSC4_REG_DBCALCNF (DBSC4_REG_BASE + 0x0424U)
-#define DBSC4_REG_DBDFIPMSTRCNF (DBSC4_REG_BASE + 0x0520U)
-#define DBSC4_REG_DBPDLK0 (DBSC4_REG_BASE + 0x0620U)
-#define DBSC4_REG_DBPDRGA0 (DBSC4_REG_BASE + 0x0624U)
-#define DBSC4_REG_DBPDRGD0 (DBSC4_REG_BASE + 0x0628U)
-#define DBSC4_REG_DBCAM0CTRL0 (DBSC4_REG_BASE + 0x0940U)
-#define DBSC4_REG_DBCAM0STAT0 (DBSC4_REG_BASE + 0x0980U)
-#define DBSC4_REG_DBCAM1STAT0 (DBSC4_REG_BASE + 0x0990U)
-#define DBSC4_REG_DBCAM2STAT0 (DBSC4_REG_BASE + 0x09A0U)
-#define DBSC4_REG_DBCAM3STAT0 (DBSC4_REG_BASE + 0x09B0U)
-#define DBSC4_BIT_DBACEN_ACCEN ((uint32_t)(1U << 0))
-#define DBSC4_BIT_DBRFEN_ARFEN ((uint32_t)(1U << 0))
-#define DBSC4_BIT_DBCAMxSTAT0 (0x00000001U)
-#define DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN (0x00000001U)
-#define DBSC4_SET_DBCMD_OPC_PRE (0x04000000U)
-#define DBSC4_SET_DBCMD_OPC_SR (0x0A000000U)
-#define DBSC4_SET_DBCMD_OPC_PD (0x08000000U)
-#define DBSC4_SET_DBCMD_OPC_MRW (0x0E000000U)
-#define DBSC4_SET_DBCMD_CH_ALL (0x00800000U)
-#define DBSC4_SET_DBCMD_RANK_ALL (0x00040000U)
-#define DBSC4_SET_DBCMD_ARG_ALL (0x00000010U)
-#define DBSC4_SET_DBCMD_ARG_ENTER (0x00000000U)
-#define DBSC4_SET_DBCMD_ARG_MRW_ODTC (0x00000B00U)
-#define DBSC4_SET_DBSYSCNT0_WRITE_ENABLE (0x00001234U)
-#define DBSC4_SET_DBSYSCNT0_WRITE_DISABLE (0x00000000U)
-#define DBSC4_SET_DBPDLK0_PHY_ACCESS (0x0000A55AU)
-#define DBSC4_SET_DBPDRGA0_ACIOCR0 (0x0000001AU)
-#define DBSC4_SET_DBPDRGD0_ACIOCR0 (0x33C03C11U)
-#define DBSC4_SET_DBPDRGA0_DXCCR (0x00000020U)
-#define DBSC4_SET_DBPDRGD0_DXCCR (0x00181006U)
-#define DBSC4_SET_DBPDRGA0_PGCR1 (0x00000003U)
-#define DBSC4_SET_DBPDRGD0_PGCR1 (0x0380C600U)
-#define DBSC4_SET_DBPDRGA0_ACIOCR1 (0x0000001BU)
-#define DBSC4_SET_DBPDRGD0_ACIOCR1 (0xAAAAAAAAU)
-#define DBSC4_SET_DBPDRGA0_ACIOCR3 (0x0000001DU)
-#define DBSC4_SET_DBPDRGD0_ACIOCR3 (0xAAAAAAAAU)
-#define DBSC4_SET_DBPDRGA0_ACIOCR5 (0x0000001FU)
-#define DBSC4_SET_DBPDRGD0_ACIOCR5 (0x000000AAU)
-#define DBSC4_SET_DBPDRGA0_DX0GCR2 (0x000000A2U)
-#define DBSC4_SET_DBPDRGD0_DX0GCR2 (0xAAAA0000U)
-#define DBSC4_SET_DBPDRGA0_DX1GCR2 (0x000000C2U)
-#define DBSC4_SET_DBPDRGD0_DX1GCR2 (0xAAAA0000U)
-#define DBSC4_SET_DBPDRGA0_DX2GCR2 (0x000000E2U)
-#define DBSC4_SET_DBPDRGD0_DX2GCR2 (0xAAAA0000U)
-#define DBSC4_SET_DBPDRGA0_DX3GCR2 (0x00000102U)
-#define DBSC4_SET_DBPDRGD0_DX3GCR2 (0xAAAA0000U)
-#define DBSC4_SET_DBPDRGA0_ZQCR (0x00000090U)
-#define DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 (0x04058904U)
-#define DBSC4_SET_DBPDRGD0_ZQCR_MD19_1 (0x04058A04U)
-#define DBSC4_SET_DBPDRGA0_DX0GCR0 (0x000000A0U)
-#define DBSC4_SET_DBPDRGD0_DX0GCR0 (0x7C0002E5U)
-#define DBSC4_SET_DBPDRGA0_DX1GCR0 (0x000000C0U)
-#define DBSC4_SET_DBPDRGD0_DX1GCR0 (0x7C0002E5U)
-#define DBSC4_SET_DBPDRGA0_DX2GCR0 (0x000000E0U)
-#define DBSC4_SET_DBPDRGD0_DX2GCR0 (0x7C0002E5U)
-#define DBSC4_SET_DBPDRGA0_DX3GCR0 (0x00000100U)
-#define DBSC4_SET_DBPDRGD0_DX3GCR0 (0x7C0002E5U)
-#define DBSC4_SET_DBPDRGA0_DX0GCR1 (0x000000A1U)
-#define DBSC4_SET_DBPDRGD0_DX0GCR1 (0x55550000U)
-#define DBSC4_SET_DBPDRGA0_DX1GCR1 (0x000000C1U)
-#define DBSC4_SET_DBPDRGD0_DX1GCR1 (0x55550000U)
-#define DBSC4_SET_DBPDRGA0_DX2GCR1 (0x000000E1U)
-#define DBSC4_SET_DBPDRGD0_DX2GCR1 (0x55550000U)
-#define DBSC4_SET_DBPDRGA0_DX3GCR1 (0x00000101U)
-#define DBSC4_SET_DBPDRGD0_DX3GCR1 (0x55550000U)
-#define DBSC4_SET_DBPDRGA0_DX0GCR3 (0x000000A3U)
-#define DBSC4_SET_DBPDRGD0_DX0GCR3 (0x00008484U)
-#define DBSC4_SET_DBPDRGA0_DX1GCR3 (0x000000C3U)
-#define DBSC4_SET_DBPDRGD0_DX1GCR3 (0x00008484U)
-#define DBSC4_SET_DBPDRGA0_DX2GCR3 (0x000000E3U)
-#define DBSC4_SET_DBPDRGD0_DX2GCR3 (0x00008484U)
-#define DBSC4_SET_DBPDRGA0_DX3GCR3 (0x00000103U)
-#define DBSC4_SET_DBPDRGD0_DX3GCR3 (0x00008484U)
-#define RST_BASE (0xE6160000U)
-#define RST_MODEMR (RST_BASE + 0x0060U)
-#define RST_MODEMR_BIT0 (0x00000001U)
+#define DBSC4_REG_BASE (0xE6790000U)
+#define DBSC4_REG_DBSYSCNT0 (DBSC4_REG_BASE + 0x0100U)
+#define DBSC4_REG_DBACEN (DBSC4_REG_BASE + 0x0200U)
+#define DBSC4_REG_DBCMD (DBSC4_REG_BASE + 0x0208U)
+#define DBSC4_REG_DBRFEN (DBSC4_REG_BASE + 0x0204U)
+#define DBSC4_REG_DBWAIT (DBSC4_REG_BASE + 0x0210U)
+#define DBSC4_REG_DBCALCNF (DBSC4_REG_BASE + 0x0424U)
+#define DBSC4_REG_DBDFIPMSTRCNF (DBSC4_REG_BASE + 0x0520U)
+#define DBSC4_REG_DBPDLK0 (DBSC4_REG_BASE + 0x0620U)
+#define DBSC4_REG_DBPDRGA0 (DBSC4_REG_BASE + 0x0624U)
+#define DBSC4_REG_DBPDRGD0 (DBSC4_REG_BASE + 0x0628U)
+#define DBSC4_REG_DBCAM0CTRL0 (DBSC4_REG_BASE + 0x0940U)
+#define DBSC4_REG_DBCAM0STAT0 (DBSC4_REG_BASE + 0x0980U)
+#define DBSC4_REG_DBCAM1STAT0 (DBSC4_REG_BASE + 0x0990U)
+#define DBSC4_REG_DBCAM2STAT0 (DBSC4_REG_BASE + 0x09A0U)
+#define DBSC4_REG_DBCAM3STAT0 (DBSC4_REG_BASE + 0x09B0U)
+#define DBSC4_BIT_DBACEN_ACCEN ((uint32_t)(1U << 0))
+#define DBSC4_BIT_DBRFEN_ARFEN ((uint32_t)(1U << 0))
+#define DBSC4_BIT_DBCAMxSTAT0 (0x00000001U)
+#define DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN (0x00000001U)
+#define DBSC4_SET_DBCMD_OPC_PRE (0x04000000U)
+#define DBSC4_SET_DBCMD_OPC_SR (0x0A000000U)
+#define DBSC4_SET_DBCMD_OPC_PD (0x08000000U)
+#define DBSC4_SET_DBCMD_OPC_MRW (0x0E000000U)
+#define DBSC4_SET_DBCMD_CH_ALL (0x00800000U)
+#define DBSC4_SET_DBCMD_RANK_ALL (0x00040000U)
+#define DBSC4_SET_DBCMD_ARG_ALL (0x00000010U)
+#define DBSC4_SET_DBCMD_ARG_ENTER (0x00000000U)
+#define DBSC4_SET_DBCMD_ARG_MRW_ODTC (0x00000B00U)
+#define DBSC4_SET_DBSYSCNT0_WRITE_ENABLE (0x00001234U)
+#define DBSC4_SET_DBSYSCNT0_WRITE_DISABLE (0x00000000U)
+#define DBSC4_SET_DBPDLK0_PHY_ACCESS (0x0000A55AU)
+#define DBSC4_SET_DBPDRGA0_ACIOCR0 (0x0000001AU)
+#define DBSC4_SET_DBPDRGD0_ACIOCR0 (0x33C03C11U)
+#define DBSC4_SET_DBPDRGA0_DXCCR (0x00000020U)
+#define DBSC4_SET_DBPDRGD0_DXCCR (0x00181006U)
+#define DBSC4_SET_DBPDRGA0_PGCR1 (0x00000003U)
+#define DBSC4_SET_DBPDRGD0_PGCR1 (0x0380C600U)
+#define DBSC4_SET_DBPDRGA0_ACIOCR1 (0x0000001BU)
+#define DBSC4_SET_DBPDRGD0_ACIOCR1 (0xAAAAAAAAU)
+#define DBSC4_SET_DBPDRGA0_ACIOCR3 (0x0000001DU)
+#define DBSC4_SET_DBPDRGD0_ACIOCR3 (0xAAAAAAAAU)
+#define DBSC4_SET_DBPDRGA0_ACIOCR5 (0x0000001FU)
+#define DBSC4_SET_DBPDRGD0_ACIOCR5 (0x000000AAU)
+#define DBSC4_SET_DBPDRGA0_DX0GCR2 (0x000000A2U)
+#define DBSC4_SET_DBPDRGD0_DX0GCR2 (0xAAAA0000U)
+#define DBSC4_SET_DBPDRGA0_DX1GCR2 (0x000000C2U)
+#define DBSC4_SET_DBPDRGD0_DX1GCR2 (0xAAAA0000U)
+#define DBSC4_SET_DBPDRGA0_DX2GCR2 (0x000000E2U)
+#define DBSC4_SET_DBPDRGD0_DX2GCR2 (0xAAAA0000U)
+#define DBSC4_SET_DBPDRGA0_DX3GCR2 (0x00000102U)
+#define DBSC4_SET_DBPDRGD0_DX3GCR2 (0xAAAA0000U)
+#define DBSC4_SET_DBPDRGA0_ZQCR (0x00000090U)
+#define DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 (0x04058904U)
+#define DBSC4_SET_DBPDRGD0_ZQCR_MD19_1 (0x04058A04U)
+#define DBSC4_SET_DBPDRGA0_DX0GCR0 (0x000000A0U)
+#define DBSC4_SET_DBPDRGD0_DX0GCR0 (0x7C0002E5U)
+#define DBSC4_SET_DBPDRGA0_DX1GCR0 (0x000000C0U)
+#define DBSC4_SET_DBPDRGD0_DX1GCR0 (0x7C0002E5U)
+#define DBSC4_SET_DBPDRGA0_DX2GCR0 (0x000000E0U)
+#define DBSC4_SET_DBPDRGD0_DX2GCR0 (0x7C0002E5U)
+#define DBSC4_SET_DBPDRGA0_DX3GCR0 (0x00000100U)
+#define DBSC4_SET_DBPDRGD0_DX3GCR0 (0x7C0002E5U)
+#define DBSC4_SET_DBPDRGA0_DX0GCR1 (0x000000A1U)
+#define DBSC4_SET_DBPDRGD0_DX0GCR1 (0x55550000U)
+#define DBSC4_SET_DBPDRGA0_DX1GCR1 (0x000000C1U)
+#define DBSC4_SET_DBPDRGD0_DX1GCR1 (0x55550000U)
+#define DBSC4_SET_DBPDRGA0_DX2GCR1 (0x000000E1U)
+#define DBSC4_SET_DBPDRGD0_DX2GCR1 (0x55550000U)
+#define DBSC4_SET_DBPDRGA0_DX3GCR1 (0x00000101U)
+#define DBSC4_SET_DBPDRGD0_DX3GCR1 (0x55550000U)
+#define DBSC4_SET_DBPDRGA0_DX0GCR3 (0x000000A3U)
+#define DBSC4_SET_DBPDRGD0_DX0GCR3 (0x00008484U)
+#define DBSC4_SET_DBPDRGA0_DX1GCR3 (0x000000C3U)
+#define DBSC4_SET_DBPDRGD0_DX1GCR3 (0x00008484U)
+#define DBSC4_SET_DBPDRGA0_DX2GCR3 (0x000000E3U)
+#define DBSC4_SET_DBPDRGD0_DX2GCR3 (0x00008484U)
+#define DBSC4_SET_DBPDRGA0_DX3GCR3 (0x00000103U)
+#define DBSC4_SET_DBPDRGD0_DX3GCR3 (0x00008484U)
+#define RST_BASE (0xE6160000U)
+#define RST_MODEMR (RST_BASE + 0x0060U)
+#define RST_MODEMR_BIT0 (0x00000001U)
#define RCAR_CNTCR_OFF (0x00U)
#define RCAR_CNTCVL_OFF (0x08U)
@@ -136,17 +136,17 @@ RCAR_INSTANTIATE_LOCK
#define RCAR_CNTCR_FCREQ(x) ((uint32_t)(x) << 8U)
#if PMIC_ROHM_BD9571
-#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
-#define PMIC_BKUP_MODE_CNT (0x20U)
-#define PMIC_QLLM_CNT (0x27U)
-#define PMIC_RETRY_MAX (100U)
-#endif
-#define SCTLR_EL3_M_BIT ((uint32_t)1U << 0)
-#define RCAR_CA53CPU_NUM_MAX (4U)
-#define RCAR_CA57CPU_NUM_MAX (4U)
-#define IS_A53A57(c) ((c) == RCAR_CLUSTER_A53A57)
-#define IS_CA57(c) ((c) == RCAR_CLUSTER_CA57)
-#define IS_CA53(c) ((c) == RCAR_CLUSTER_CA53)
+#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
+#define PMIC_BKUP_MODE_CNT (0x20U)
+#define PMIC_QLLM_CNT (0x27U)
+#define PMIC_RETRY_MAX (100U)
+#endif /* PMIC_ROHM_BD9571 */
+#define SCTLR_EL3_M_BIT ((uint32_t)1U << 0)
+#define RCAR_CA53CPU_NUM_MAX (4U)
+#define RCAR_CA57CPU_NUM_MAX (4U)
+#define IS_A53A57(c) ((c) == RCAR_CLUSTER_A53A57)
+#define IS_CA57(c) ((c) == RCAR_CLUSTER_CA57)
+#define IS_CA53(c) ((c) == RCAR_CLUSTER_CA53)
#ifndef __ASSEMBLER__
IMPORT_SYM(unsigned long, __system_ram_start__, SYSTEM_RAM_START);
@@ -320,11 +320,13 @@ void rcar_pwrc_clusteroff(uint64_t mpidr)
c = rcar_pwrc_get_mpidr_cluster(mpidr);
dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR;
- if (PRR_PRODUCT_M3 == product && cut < PRR_PRODUCT_30)
+ if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) {
goto done;
+ }
- if (PRR_PRODUCT_H3 == product && cut <= PRR_PRODUCT_20)
+ if (product == PRR_PRODUCT_H3 && cut <= PRR_PRODUCT_20) {
goto done;
+ }
/* all of the CPUs in the cluster is in the CoreStandby mode */
mmio_write_32(dst, MODE_L2_DOWN);
@@ -343,7 +345,7 @@ static void rcar_pwrc_save_timer_state(void)
rcar_pwrc_saved_cntfid =
mmio_read_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF));
}
-#endif
+#endif /* RCAR_SYSTEM_SUSPEND */
void rcar_pwrc_restore_timer_state(void)
{
@@ -372,10 +374,10 @@ void rcar_pwrc_system_reset(void)
}
#endif /* PMIC_ROHM_BD9571 */
-#define RST_CA53_CPU0_BARH (0xE6160080U)
-#define RST_CA53_CPU0_BARL (0xE6160084U)
-#define RST_CA57_CPU0_BARH (0xE61600C0U)
-#define RST_CA57_CPU0_BARL (0xE61600C4U)
+#define RST_CA53_CPU0_BARH (0xE6160080U)
+#define RST_CA53_CPU0_BARL (0xE6160084U)
+#define RST_CA57_CPU0_BARH (0xE61600C0U)
+#define RST_CA57_CPU0_BARL (0xE61600C4U)
void rcar_pwrc_setup(void)
{
@@ -427,11 +429,13 @@ static void __attribute__ ((section(".system_ram")))
product = reg & PRR_PRODUCT_MASK;
cut = reg & PRR_CUT_MASK;
- if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30)
+ if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) {
goto self_refresh;
+ }
- if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
+ if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20) {
goto self_refresh;
+ }
mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
@@ -509,7 +513,7 @@ self_refresh:
}
static void __attribute__ ((section(".system_ram")))
- rcar_pwrc_set_self_refresh_e3(void)
+rcar_pwrc_set_self_refresh_e3(void)
{
uint32_t ddr_md;
uint32_t reg;
@@ -533,8 +537,10 @@ static void __attribute__ ((section(".system_ram")))
while (mmio_read_32(DBSC4_REG_DBWAIT))
;
- /* Set the auto-refresh enable register */
- /* Set the ARFEN bit to 0 in the DBRFEN */
+ /*
+ * Set the auto-refresh enable register
+ * Set the ARFEN bit to 0 in the DBRFEN
+ */
mmio_write_32(DBSC4_REG_DBRFEN, 0);
mmio_write_32(DBSC4_REG_DBPDLK0, DBSC4_SET_DBPDLK0_PHY_ACCESS);
@@ -638,7 +644,7 @@ static void __attribute__ ((section(".system_ram")))
}
void __attribute__ ((section(".system_ram"))) __attribute__ ((noinline))
- rcar_pwrc_go_suspend_to_ram(void)
+rcar_pwrc_go_suspend_to_ram(void)
{
#if PMIC_ROHM_BD9571
int32_t rc = -1, qllm = -1;
@@ -713,7 +719,7 @@ void rcar_pwrc_suspend_to_ram(void)
error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, 0);
if (error) {
- ERROR("Failed send KEEP10 init ret=%d \n", error);
+ ERROR("Failed send KEEP10 init ret=%d\n", error);
return;
}
#endif
@@ -835,7 +841,6 @@ int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr)
uint64_t my_cpu;
int32_t rtn;
uint32_t my_cluster_type;
-
const uint32_t cluster_type[PLATFORM_CLUSTER_COUNT] = {
RCAR_CLUSTER_CA53,
RCAR_CLUSTER_CA57
@@ -861,6 +866,6 @@ int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr)
}
}
}
- return (rtn);
+ return rtn;
}
diff --git a/drivers/renesas/rcar/pwrc/pwrc.h b/drivers/renesas/common/pwrc/pwrc.h
index 2b81783972..f73099b0b5 100644
--- a/drivers/renesas/rcar/pwrc/pwrc.h
+++ b/drivers/renesas/common/pwrc/pwrc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -31,12 +31,12 @@
#define WKUP_PPONR 0x2
#define WKUP_GICREQ 0x3
-#define RCAR_INVALID (0xffffffffU)
+#define RCAR_INVALID (0xffffffffU)
#define PSYSR_INVALID 0xffffffff
-#define RCAR_CLUSTER_A53A57 (0U)
-#define RCAR_CLUSTER_CA53 (1U)
-#define RCAR_CLUSTER_CA57 (2U)
+#define RCAR_CLUSTER_A53A57 (0U)
+#define RCAR_CLUSTER_CA53 (1U)
+#define RCAR_CLUSTER_CA57 (2U)
#ifndef __ASSEMBLER__
void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr);
diff --git a/drivers/renesas/rcar/qos/qos_reg.h b/drivers/renesas/common/qos_reg.h
index f2012fa45f..f2012fa45f 100644
--- a/drivers/renesas/rcar/qos/qos_reg.h
+++ b/drivers/renesas/common/qos_reg.h
diff --git a/drivers/renesas/rcar/rom/rom_api.c b/drivers/renesas/common/rom/rom_api.c
index fda28150e9..fda28150e9 100644
--- a/drivers/renesas/rcar/rom/rom_api.c
+++ b/drivers/renesas/common/rom/rom_api.c
diff --git a/drivers/renesas/rcar/rom/rom_api.h b/drivers/renesas/common/rom/rom_api.h
index 1d5b03d7f5..1d5b03d7f5 100644
--- a/drivers/renesas/rcar/rom/rom_api.h
+++ b/drivers/renesas/common/rom/rom_api.h
diff --git a/drivers/renesas/rcar/rpc/rpc_driver.c b/drivers/renesas/common/rpc/rpc_driver.c
index 63de5b851a..63de5b851a 100644
--- a/drivers/renesas/rcar/rpc/rpc_driver.c
+++ b/drivers/renesas/common/rpc/rpc_driver.c
diff --git a/drivers/renesas/rcar/rpc/rpc_registers.h b/drivers/renesas/common/rpc/rpc_registers.h
index 79aea85990..79aea85990 100644
--- a/drivers/renesas/rcar/rpc/rpc_registers.h
+++ b/drivers/renesas/common/rpc/rpc_registers.h
diff --git a/drivers/renesas/rcar/scif/scif.S b/drivers/renesas/common/scif/scif.S
index ae26cc4023..beb8dd8383 100644
--- a/drivers/renesas/rcar/scif/scif.S
+++ b/drivers/renesas/common/scif/scif.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,43 +9,43 @@
#include <console_macros.S>
#include <drivers/renesas/rcar/console/console.h>
-#define SCIF_INTERNAL_CLK 0
-#define SCIF_EXTARNAL_CLK 1
-#define SCIF_CLK SCIF_INTERNAL_CLK
+#define SCIF_INTERNAL_CLK 0
+#define SCIF_EXTARNAL_CLK 1
+#define SCIF_CLK SCIF_INTERNAL_CLK
/* product register */
-#define PRR (0xFFF00044)
-#define PRR_PRODUCT_MASK (0x00007F00)
-#define PRR_CUT_MASK (0x000000FF)
-#define PRR_PRODUCT_H3_VER_10 (0x00004F00)
-#define PRR_PRODUCT_E3 (0x00005700)
-#define PRR_PRODUCT_D3 (0x00005800)
+#define PRR (0xFFF00044)
+#define PRR_PRODUCT_MASK (0x00007F00)
+#define PRR_CUT_MASK (0x000000FF)
+#define PRR_PRODUCT_H3_VER_10 (0x00004F00)
+#define PRR_PRODUCT_E3 (0x00005700)
+#define PRR_PRODUCT_D3 (0x00005800)
/* module stop */
-#define CPG_BASE (0xE6150000)
-#define CPG_SMSTPCR2 (0x0138)
-#define CPG_SMSTPCR3 (0x013C)
+#define CPG_BASE (0xE6150000)
+#define CPG_SMSTPCR2 (0x0138)
+#define CPG_SMSTPCR3 (0x013C)
#define CPG_MSTPSR2 (0x0040)
-#define CPG_MSTPSR3 (0x0048)
-#define MSTP207 (1 << 7)
-#define MSTP310 (1 << 10)
-#define CPG_CPGWPR (0x0900)
+#define CPG_MSTPSR3 (0x0048)
+#define MSTP207 (1 << 7)
+#define MSTP310 (1 << 10)
+#define CPG_CPGWPR (0x0900)
/* scif */
-#define SCIF0_BASE (0xE6E60000)
-#define SCIF2_BASE (0xE6E88000)
-#define SCIF_SCSMR (0x00)
-#define SCIF_SCBRR (0x04)
-#define SCIF_SCSCR (0x08)
-#define SCIF_SCFTDR (0x0C)
-#define SCIF_SCFSR (0x10)
-#define SCIF_SCFRDR (0x14)
-#define SCIF_SCFCR (0x18)
-#define SCIF_SCFDR (0x1C)
-#define SCIF_SCSPTR (0x20)
-#define SCIF_SCLSR (0x24)
-#define SCIF_DL (0x30)
-#define SCIF_CKS (0x34)
+#define SCIF0_BASE (0xE6E60000)
+#define SCIF2_BASE (0xE6E88000)
+#define SCIF_SCSMR (0x00)
+#define SCIF_SCBRR (0x04)
+#define SCIF_SCSCR (0x08)
+#define SCIF_SCFTDR (0x0C)
+#define SCIF_SCFSR (0x10)
+#define SCIF_SCFRDR (0x14)
+#define SCIF_SCFCR (0x18)
+#define SCIF_SCFDR (0x1C)
+#define SCIF_SCSPTR (0x20)
+#define SCIF_SCLSR (0x24)
+#define SCIF_DL (0x30)
+#define SCIF_CKS (0x34)
#if RCAR_LSI == RCAR_V3M
#define SCIF_BASE SCIF0_BASE
@@ -60,70 +60,71 @@
#endif
/* mode pin */
-#define RST_MODEMR (0xE6160060)
-#define MODEMR_MD12 (0x00001000)
+#define RST_MODEMR (0xE6160060)
+#define MODEMR_MD12 (0x00001000)
-#define SCSMR_CA_MASK (1 << 7)
-#define SCSMR_CA_ASYNC (0x0000)
-#define SCSMR_CHR_MASK (1 << 6)
-#define SCSMR_CHR_8 (0x0000)
-#define SCSMR_PE_MASK (1 << 5)
-#define SCSMR_PE_DIS (0x0000)
-#define SCSMR_STOP_MASK (1 << 3)
-#define SCSMR_STOP_1 (0x0000)
-#define SCSMR_CKS_MASK (3 << 0)
-#define SCSMR_CKS_DIV1 (0x0000)
-#define SCSMR_INIT_DATA (SCSMR_CA_ASYNC + \
+#define SCSMR_CA_MASK (1 << 7)
+#define SCSMR_CA_ASYNC (0x0000)
+#define SCSMR_CHR_MASK (1 << 6)
+#define SCSMR_CHR_8 (0x0000)
+#define SCSMR_PE_MASK (1 << 5)
+#define SCSMR_PE_DIS (0x0000)
+#define SCSMR_STOP_MASK (1 << 3)
+#define SCSMR_STOP_1 (0x0000)
+#define SCSMR_CKS_MASK (3 << 0)
+#define SCSMR_CKS_DIV1 (0x0000)
+#define SCSMR_INIT_DATA (SCSMR_CA_ASYNC + \
SCSMR_CHR_8 + \
SCSMR_PE_DIS + \
SCSMR_STOP_1 + \
SCSMR_CKS_DIV1)
-#define SCBRR_115200BPS (17)
-#define SCBRR_115200BPSON (16)
-#define SCBRR_115200BPS_E3_SSCG (15)
-#define SCBRR_230400BPS (8)
+#define SCBRR_115200BPS (17)
+#define SCBRR_115200BPSON (16)
+#define SCBRR_115200BPS_E3_SSCG (15)
+#define SCBRR_230400BPS (8)
-#define SCSCR_TE_MASK (1 << 5)
-#define SCSCR_TE_DIS (0x0000)
-#define SCSCR_TE_EN (0x0020)
-#define SCSCR_RE_MASK (1 << 4)
-#define SCSCR_RE_DIS (0x0000)
-#define SCSCR_RE_EN (0x0010)
-#define SCSCR_CKE_MASK (3 << 0)
-#define SCSCR_CKE_INT (0x0000)
-#define SCSCR_CKE_BRG (0x0002)
+#define SCSCR_TE_MASK (1 << 5)
+#define SCSCR_TE_DIS (0x0000)
+#define SCSCR_TE_EN (0x0020)
+#define SCSCR_RE_MASK (1 << 4)
+#define SCSCR_RE_DIS (0x0000)
+#define SCSCR_RE_EN (0x0010)
+#define SCSCR_CKE_MASK (3 << 0)
+#define SCSCR_CKE_INT (0x0000)
+#define SCSCR_CKE_BRG (0x0002)
#if SCIF_CLK == SCIF_EXTARNAL_CLK
-#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG)
+#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG)
#else
-#define SCFSR_TEND_MASK (1 << 6)
-#define SCFSR_TEND_TRANS_END (0x0040)
-#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT)
+#define SCFSR_TEND_MASK (1 << 6)
+#define SCFSR_TEND_TRANS_END (0x0040)
+#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT)
#endif
-#define SCFSR_INIT_DATA (0x0000)
-#define SCFCR_TTRG_MASK (3 << 4)
-#define SCFCR_TTRG_8 (0x0000)
-#define SCFCR_TTRG_0 (0x0030)
-#define SCFCR_TFRST_MASK (1 << 2)
-#define SCFCR_TFRST_DIS (0x0000)
-#define SCFCR_TFRST_EN (0x0004)
-#define SCFCR_RFRS_MASK (1 << 1)
-#define SCFCR_RFRS_DIS (0x0000)
-#define SCFCR_RFRS_EN (0x0002)
-#define SCFCR_INIT_DATA (SCFCR_TTRG_8)
-#define SCFDR_T_MASK (0x1f << 8)
-#define DL_INIT_DATA (8)
-#define CKS_CKS_DIV_MASK (1 << 15)
-#define CKS_CKS_DIV_CLK (0x0000)
-#define CKS_XIN_MASK (1 << 14)
-#define CKS_XIN_SCIF_CLK (0x0000)
-#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK)
+#define SCFSR_INIT_DATA (0x0000)
+#define SCFCR_TTRG_MASK (3 << 4)
+#define SCFCR_TTRG_8 (0x0000)
+#define SCFCR_TTRG_0 (0x0030)
+#define SCFCR_TFRST_MASK (1 << 2)
+#define SCFCR_TFRST_DIS (0x0000)
+#define SCFCR_TFRST_EN (0x0004)
+#define SCFCR_RFRS_MASK (1 << 1)
+#define SCFCR_RFRS_DIS (0x0000)
+#define SCFCR_RFRS_EN (0x0002)
+#define SCFCR_INIT_DATA (SCFCR_TTRG_8)
+#define SCFDR_T_MASK (0x1f << 8)
+#define DL_INIT_DATA (8)
+#define CKS_CKS_DIV_MASK (1 << 15)
+#define CKS_CKS_DIV_CLK (0x0000)
+#define CKS_XIN_MASK (1 << 14)
+#define CKS_XIN_SCIF_CLK (0x0000)
+#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK)
.globl console_rcar_register
.globl console_rcar_init
.globl console_rcar_putc
.globl console_rcar_flush
- /* -----------------------------------------------
+ /*
+ * -----------------------------------------------
* int console_rcar_register(
* uintptr_t base, uint32_t clk, uint32_t baud,
* console_t *console)
@@ -154,7 +155,7 @@ register_fail:
ret x7
endfunc console_rcar_register
- /* -----------------------------------------------
+ /*
* int console_rcar_init(unsigned long base_addr,
* unsigned int uart_clk, unsigned int baud_rate)
* Function to initialize the console without a
@@ -166,7 +167,6 @@ endfunc console_rcar_register
* w2 - Baud rate
* Out: return 1 on success
* Clobber list : x1, x2
- * -----------------------------------------------
*/
func console_rcar_init
ldr x0, =CPG_BASE
@@ -188,8 +188,10 @@ func console_rcar_init
ldrh w1, [x0, #SCIF_SCFCR]
orr w1, w1, #(SCFCR_TFRST_EN + SCFCR_RFRS_EN)
strh w1, [x0, #SCIF_SCFCR]
- /* Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER
- in SCLSR, then clear them to 0 */
+ /*
+ * Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER
+ * in SCLSR, then clear them to 0
+ */
mov w1, #SCFSR_INIT_DATA
strh w1, [x0, #SCIF_SCFSR]
mov w1, #0
@@ -265,7 +267,7 @@ func console_rcar_init
ret
endfunc console_rcar_init
- /* --------------------------------------------------------
+ /*
* int console_rcar_putc(int c, unsigned int base_addr)
* Function to output a character over the console. It
* returns the character printed on success or -1 on error.
@@ -273,7 +275,6 @@ endfunc console_rcar_init
* x1 - pointer to console_t structure
* Out : return -1 on error else return character.
* Clobber list : x2
- * --------------------------------------------------------
*/
func console_rcar_putc
ldr x1, =SCIF_BASE
@@ -304,12 +305,11 @@ func console_rcar_putc
ret
endfunc console_rcar_putc
- /* ---------------------------------------------
+ /*
* void console_rcar_flush(void)
* Function to force a write of all buffered
* data that hasn't been output. It returns void
* Clobber list : x0, x1
- * ---------------------------------------------
*/
func console_rcar_flush
ldr x0, =SCIF_BASE
diff --git a/drivers/renesas/rcar/watchdog/swdt.c b/drivers/renesas/common/watchdog/swdt.c
index 111e651741..05987ab704 100644
--- a/drivers/renesas/rcar/watchdog/swdt.c
+++ b/drivers/renesas/common/watchdog/swdt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -162,6 +162,6 @@ void rcar_swdt_exec(uint64_t p)
gicv2_end_of_interrupt(ARM_IRQ_SEC_WDT);
rcar_swdt_release();
ERROR("\n");
- ERROR("System WDT overflow, occured address is %p\n", (void *)p);
+ ERROR("System WDT overflow, occurred address is %p\n", (void *)p);
panic();
}
diff --git a/drivers/renesas/rcar/common.c b/drivers/renesas/rcar/common.c
deleted file mode 100644
index 42bdce5797..0000000000
--- a/drivers/renesas/rcar/common.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <lib/mmio.h>
-
-#include "rcar_private.h"
-
-void
-#if IMAGE_BL31
- __attribute__ ((section(".system_ram")))
-#endif
- cpg_write(uintptr_t regadr, uint32_t regval)
-{
- uint32_t value = (regval);
- mmio_write_32((uintptr_t) RCAR_CPGWPR, ~value);
- mmio_write_32(regadr, value);
-}
-
-void
-#if IMAGE_BL31
- __attribute__ ((section(".system_ram")))
-#endif
- mstpcr_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t target_bit)
-{
- uint32_t reg;
- reg = mmio_read_32(mstpcr);
- reg &= ~target_bit;
- cpg_write(mstpcr, reg);
- while ((mmio_read_32(mstpsr) & target_bit) != 0U) {
- }
-}
diff --git a/drivers/renesas/rcar/emmc/emmc_config.h b/drivers/renesas/rcar/emmc/emmc_config.h
deleted file mode 100644
index 686ccb99c5..0000000000
--- a/drivers/renesas/rcar/emmc/emmc_config.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/**
- * @file emmc_config.h
- * @brief Configuration file
- *
- */
-
-#ifndef EMMC_CONFIG_H
-#define EMMC_CONFIG_H
-
-/* ************************ HEADER (INCLUDE) SECTION *********************** */
-
-/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
-
-/** @brief MMC driver config
- */
-#define EMMC_RCA 1UL /* RCA */
-#define EMMC_RW_DATA_TIMEOUT 0x40UL /* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */
-#define EMMC_RETRY_COUNT 0 /* how many times to try after fail. Don't change. */
-#define EMMC_CMD_MAX 60UL /* Don't change. */
-
-/** @brief etc
- */
-#define LOADIMAGE_FLAGS_DMA_ENABLE 0x00000001UL
-
-/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
-
-/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
-
-/* ************************** FUNCTION PROTOTYPES ************************** */
-
-/* ********************************* CODE ********************************** */
-
-#endif /* EMMC_CONFIG_H */
-/* ******************************** END ************************************ */
diff --git a/drivers/renesas/rcar/emmc/emmc_hal.h b/drivers/renesas/rcar/emmc/emmc_hal.h
deleted file mode 100644
index f0b7e9d775..0000000000
--- a/drivers/renesas/rcar/emmc/emmc_hal.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/**
- * @file emmc_hal.h
- * @brief emmc boot driver is expecting this header file
- *
- */
-
-#ifndef EMMC_HAL_H
-#define EMMC_HAL_H
-/* ************************ HEADER (INCLUDE) SECTION *********************** */
-#include <stdint.h>
-/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
-
-/** @brief memory card error/status types
- */
-#define HAL_MEMCARD_OUT_OF_RANGE 0x80000000L
-#define HAL_MEMCARD_ADDRESS_ERROR 0x40000000L
-#define HAL_MEMCARD_BLOCK_LEN_ERROR 0x20000000L
-#define HAL_MEMCARD_ERASE_SEQ_ERROR 0x10000000L
-#define HAL_MEMCARD_ERASE_PARAM 0x08000000L
-#define HAL_MEMCARD_WP_VIOLATION 0x04000000L
-#define HAL_MEMCARD_CARD_IS_LOCKED 0x02000000L
-#define HAL_MEMCARD_LOCK_UNLOCK_FAILED 0x01000000L
-#define HAL_MEMCARD_COM_CRC_ERROR 0x00800000L
-#define HAL_MEMCARD_ILEGAL_COMMAND 0x00400000L
-#define HAL_MEMCARD_CARD_ECC_FAILED 0x00200000L
-#define HAL_MEMCARD_CC_ERROR 0x00100000L
-#define HAL_MEMCARD_ERROR 0x00080000L
-#define HAL_MEMCARD_UNDERRUN 0x00040000L
-#define HAL_MEMCARD_OVERRUN 0x00020000L
-#define HAL_MEMCARD_CIDCSD_OVERWRITE 0x00010000L
-#define HAL_MEMCARD_WP_ERASE_SKIP 0x00008000L
-#define HAL_MEMCARD_CARD_ECC_DISABLED 0x00004000L
-#define HAL_MEMCARD_ERASE_RESET 0x00002000L
-#define HAL_MEMCARD_CARD_STATE 0x00001E00L
-#define HAL_MEMCARD_CARD_READY_FOR_DATA 0x00000100L
-#define HAL_MEMCARD_APP_CMD 0x00000020L
-#define HAL_MEMCARD_SWITCH_ERROR 0x00000080L
-#define HAL_MEMCARD_AKE_SEQ_ERROR 0x00000008L
-#define HAL_MEMCARD_NO_ERRORS 0x00000000L
-
-/** @brief Memory card response types
- */
-#define HAL_MEMCARD_COMMAND_INDEX_MASK 0x0003f
-
-/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
-
-/** @brief Type of the return value.
- */
-typedef enum {
- HAL_MEMCARD_FAIL = 0U,
- HAL_MEMCARD_OK = 1U,
- HAL_MEMCARD_DMA_ALLOC_FAIL = 2U, /**< DMA channel allocation failed */
- HAL_MEMCARD_DMA_TRANSFER_FAIL = 3U, /**< DMA transfer failed */
- HAL_MEMCARD_CARD_STATUS_ERROR = 4U, /**< A non-masked error bit was set in the card status */
- HAL_MEMCARD_CMD_TIMEOUT = 5U, /**< Command timeout occurred */
- HAL_MEMCARD_DATA_TIMEOUT = 6U, /**< Data timeout occurred */
- HAL_MEMCARD_CMD_CRC_ERROR = 7U, /**< Command CRC error occurred */
- HAL_MEMCARD_DATA_CRC_ERROR = 8U /**< Data CRC error occurred */
-} HAL_MEMCARD_RETURN;
-
-/** @brief memory access operation
- */
-typedef enum {
- HAL_MEMCARD_READ = 0U, /**< read */
- HAL_MEMCARD_WRITE = 1U /**< write */
-} HAL_MEMCARD_OPERATION;
-
-/** @brief Type of data width on memorycard bus
- */
-typedef enum {
- HAL_MEMCARD_DATA_WIDTH_1_BIT = 0U,
- HAL_MEMCARD_DATA_WIDTH_4_BIT = 1U,
- HAL_MEMCARD_DATA_WIDTH_8_BIT = 2U
-} HAL_MEMCARD_DATA_WIDTH; /**< data (bus) width types */
-
-/** @brief Presence of the memory card
- */
-typedef enum {
- HAL_MEMCARD_CARD_IS_IN = 0U,
- HAL_MEMCARD_CARD_IS_OUT = 1U
-} HAL_MEMCARD_PRESENCE_STATUS; /* presence status of the memory card */
-
-/** @brief mode of data transfer
- */
-typedef enum {
- HAL_MEMCARD_DMA = 0U,
- HAL_MEMCARD_NOT_DMA = 1U
-} HAL_MEMCARD_DATA_TRANSFER_MODE;
-
-/** @brief Memory card response types.
- */
-typedef enum hal_memcard_response_type {
- HAL_MEMCARD_RESPONSE_NONE = 0x00000U,
- HAL_MEMCARD_RESPONSE_R1 = 0x00100U,
- HAL_MEMCARD_RESPONSE_R1b = 0x00200U,
- HAL_MEMCARD_RESPONSE_R2 = 0x00300U,
- HAL_MEMCARD_RESPONSE_R3 = 0x00400U,
- HAL_MEMCARD_RESPONSE_R4 = 0x00500U,
- HAL_MEMCARD_RESPONSE_R5 = 0x00600U,
- HAL_MEMCARD_RESPONSE_R6 = 0x00700U,
- HAL_MEMCARD_RESPONSE_R7 = 0x00800U,
- HAL_MEMCARD_RESPONSE_TYPE_MASK = 0x00f00U
-} HAL_MEMCARD_RESPONSE_TYPE;
-
-/** @brief Memory card command types.
- */
-typedef enum hal_memcard_command_type {
- HAL_MEMCARD_COMMAND_TYPE_BC = 0x00000U,
- HAL_MEMCARD_COMMAND_TYPE_BCR = 0x01000U,
- HAL_MEMCARD_COMMAND_TYPE_AC = 0x02000U,
- HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE = 0x03000U,
- HAL_MEMCARD_COMMAND_TYPE_ADTC_READ = 0x04000U,
- HAL_MEMCARD_COMMAND_TYPE_MASK = 0x07000U
-} HAL_MEMCARD_COMMAND_TYPE;
-
-/** @brief Type of memory card
- */
-typedef enum hal_memcard_command_card_type {
- HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON = 0x00000U,
- HAL_MEMCARD_COMMAND_CARD_TYPE_MMC = 0x08000U,
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD = 0x10000U,
- HAL_MEMCARD_COMMAND_CARD_TYPE_MASK = 0x18000U
-} HAL_MEMCARD_COMMAND_CARD_TYPE;
-
-/** @brief Memory card application command.
- */
-typedef enum hal_memcard_command_app_norm {
- HAL_MEMCARD_COMMAND_NORMAL = 0x00000U,
- HAL_MEMCARD_COMMAND_APP = 0x20000U,
- HAL_MEMCARD_COMMAND_APP_NORM_MASK = 0x20000U
-} HAL_MEMCARD_COMMAND_APP_NORM;
-
-/** @brief Memory card command codes.
- */
-typedef enum {
-/* class 0 and class 1 */
- CMD0_GO_IDLE_STATE = 0 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD0 */
- CMD1_SEND_OP_COND = 1 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD1 */
- CMD2_ALL_SEND_CID_MMC = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD2 */
- CMD2_ALL_SEND_CID_SD =
- 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
- CMD3_SET_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD3 */
- CMD3_SEND_RELATIVE_ADDR =
- 3 | HAL_MEMCARD_RESPONSE_R6 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
- CMD4_SET_DSR = 4 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD4 */
- CMD5_SLEEP_AWAKE = 5 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD5 */
- CMD6_SWITCH = 6 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD6 */
- CMD6_SWITCH_FUNC =
- 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
- ACMD6_SET_BUS_WIDTH =
- 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
- CMD7_SELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7 */
- CMD7_SELECT_CARD_PROG = 7 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7(from Disconnected State to Programming State) */
- CMD7_DESELECT_CARD =
- 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,
- CMD8_SEND_EXT_CSD = 8 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD8 */
- CMD8_SEND_IF_COND =
- 8 | HAL_MEMCARD_RESPONSE_R7 | HAL_MEMCARD_COMMAND_TYPE_BCR |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
- CMD9_SEND_CSD = 9 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD9 */
- CMD10_SEND_CID = 10 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD10 */
- CMD11_READ_DAT_UNTIL_STOP = 11 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD11 */
- CMD12_STOP_TRANSMISSION = 12 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 */
- CMD12_STOP_TRANSMISSION_WRITE = 12 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12(R1b : write case) */
- CMD13_SEND_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD13 */
- ACMD13_SD_STATUS =
- 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
- CMD14_BUSTEST_R = 14 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD14 */
- CMD15_GO_INACTIVE_STATE = 15 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD15 */
-
-/* class 2 */
- CMD16_SET_BLOCKLEN = 16 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD16 */
- CMD17_READ_SINGLE_BLOCK = 17 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD17 */
- CMD18_READ_MULTIPLE_BLOCK = 18 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD18 */
- CMD19_BUS_TEST_W = 19 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD19 */
-
-/* class 3 */
- CMD20_WRITE_DAT_UNTIL_STOP = 20 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD20 */
- CMD21 = 21, /* CMD21 */
- CMD22 = 22, /* CMD22 */
- ACMD22_SEND_NUM_WR_BLOCKS =
- 22 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
-
-/* class 4 */
- CMD23_SET_BLOCK_COUNT = 23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD23 */
- ACMD23_SET_WR_BLK_ERASE_COUNT =
- 23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
- CMD24_WRITE_BLOCK = 24 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD24 */
- CMD25_WRITE_MULTIPLE_BLOCK = 25 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD25 */
- CMD26_PROGRAM_CID = 26 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD26 */
- CMD27_PROGRAM_CSD = 27 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD27 */
-
-/* class 6 */
- CMD28_SET_WRITE_PROT = 28 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD28 */
- CMD29_CLR_WRITE_PROT = 29 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD29 */
- CMD30_SEND_WRITE_PROT = 30 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD30 */
- CMD30_SEND_WRITE_PROT_TYPE = 31 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD31 */
-
-/* class 5 */
- CMD32_ERASE_WR_BLK_START = 32 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD32 */
- CMD33_ERASE_WR_BLK_END = 33 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD33 */
- CMD34 = 34, /* CMD34 */
- CMD35_ERASE_GROUP_START = 35 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD35 */
- CMD36_ERASE_GROUP_END = 36 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD36 */
- CMD37 = 37, /* CMD37 */
- CMD38_ERASE = 38 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD38 */
-
-/* class 9 */
- CMD39_FASTIO = 39 | HAL_MEMCARD_RESPONSE_R4 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD39 */
- CMD40_GO_IRQSTATE = 40 | HAL_MEMCARD_RESPONSE_R5 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD40 */
- CMD41 = 41, /* CMD41 */
- ACMD41_SD_SEND_OP_COND =
- 41 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
-
-/* class 7 */
- CMD42_LOCK_UNLOCK = 42 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD42 */
- ACMD42_SET_CLR_CARD_DETECT =
- 42 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
- CMD43 = 43, /* CMD43 */
- CMD44 = 44, /* CMD44 */
- CMD45 = 45, /* CMD45 */
- CMD46 = 46, /* CMD46 */
- CMD47 = 47, /* CMD47 */
- CMD48 = 48, /* CMD48 */
- CMD49 = 49, /* CMD49 */
- CMD50 = 50, /* CMD50 */
- CMD51 = 51, /* CMD51 */
- ACMD51_SEND_SCR =
- 51 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
- CMD52 = 52, /* CMD52 */
- CMD53 = 53, /* CMD53 */
- CMD54 = 54, /* CMD54 */
-
-/* class 8 */
- CMD55_APP_CMD = 55 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD55 */
- CMD56_GEN_CMD = 56 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD56 */
- CMD57 = 57, /* CMD57 */
- CMD58 = 58, /* CMD58 */
- CMD59 = 59, /* CMD59 */
- CMD60 = 60, /* CMD60 */
- CMD61 = 61, /* CMD61 */
- CMD62 = 62, /* CMD62 */
- CMD63 = 63 /* CMD63 */
-} HAL_MEMCARD_COMMAND;
-
-/** @brief Configuration structure from HAL layer.
- *
- * If some field is not available it should be filled with 0xFF.
- * The API version is 32-bit unsigned integer telling the version of the API. The integer is divided to four sections which each can be treated as a 8-bit unsigned number:
- * Bits 31-24 make the most significant part of the version number. This number starts from 1 i.e. the second version of the API will be 0x02xxxxxx. This number changes only, if the API itself changes so much that it is not compatible anymore with older releases.
- * Bits 23-16 API minor version number. For example API version 2.1 would be 0x0201xxxx.
- * Bits 15-8 are the number of the year when release is done. The 0 is year 2000, 1 is year 2001 and so on
- * Bits 7- are the week number when release is done. First full week of the year is 1
- *
- * @note Example: let's assume that release 2.1 is done on week 10 year 2008 the version will get the value 0x0201080A
- */
-typedef struct {
- /**
- * Version of the chipset API implementation
- *
- * bits [31:24] API specification major version number.<br>
- * bits [23:16] API specification minor version number.<br>
- * bits [15:8] API implemention year. (2000 = 0, 2001 = 1, ...)<br>
- * bits [7:0] API implemention week.<br>
- * Example: API specification version 4.0, implementation w46 2008 => 0x0400082E
- */
- uint32_t api_version;
-
- /** maximum block count which can be transferred at once */
- uint32_t max_block_count;
-
- /** maximum clock frequence in Hz supported by HW */
- uint32_t max_clock_freq;
-
- /** maximum data bus width supported by HW */
- uint16_t max_data_width;
-
- /** Is high-speed mode supported by HW (yes=1, no=0) */
- uint8_t hs_mode_supported;
-
- /** Is memory card removable (yes=1, no=0) */
- uint8_t card_removable;
-
-} HAL_MEMCARD_HW_CONF;
-
-/** @brief Configuration structure to HAL layer.
- */
-typedef struct {
- /** how many times to try after fail, for instance sending command */
- uint32_t retries_after_fail;
-} HAL_MEMCARD_INIT_CONF;
-
-/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
-
-/* ************************** FUNCTION PROTOTYPES ************************** */
-
-/* ********************************* CODE ********************************** */
-
-#endif /* EMMC_HAL_H */
-
-/* ******************************** END ************************************ */
diff --git a/drivers/renesas/rcar/emmc/emmc_registers.h b/drivers/renesas/rcar/emmc/emmc_registers.h
deleted file mode 100644
index 55ff33d8c7..0000000000
--- a/drivers/renesas/rcar/emmc/emmc_registers.h
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/**
- * @file emmc_registers.h
- * @brief emmc boot driver is expecting this header file. HS-MMC module header file.
- *
- */
-
-#ifndef EMMC_REGISTERS_H
-#define EMMC_REGISTERS_H
-
-/* ************************ HEADER (INCLUDE) SECTION *********************** */
-
-/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
-
-/* MMC channel select */
-#define MMC_CH0 (0U) /* SDHI2/MMC0 */
-#define MMC_CH1 (1U) /* SDHI3/MMC1 */
-
-#if RCAR_LSI == RCAR_E3
-#define USE_MMC_CH (MMC_CH1) /* R-Car E3 */
-#else /* RCAR_LSI == RCAR_E3 */
-#define USE_MMC_CH (MMC_CH0) /* R-Car H3/M3/M3N */
-#endif /* RCAR_LSI == RCAR_E3 */
-
-#define BIT0 (0x00000001U)
-#define BIT1 (0x00000002U)
-#define BIT2 (0x00000004U)
-#define BIT3 (0x00000008U)
-#define BIT4 (0x00000010U)
-#define BIT5 (0x00000020U)
-#define BIT6 (0x00000040U)
-#define BIT7 (0x00000080U)
-#define BIT8 (0x00000100U)
-#define BIT9 (0x00000200U)
-#define BIT10 (0x00000400U)
-#define BIT11 (0x00000800U)
-#define BIT12 (0x00001000U)
-#define BIT13 (0x00002000U)
-#define BIT14 (0x00004000U)
-#define BIT15 (0x00008000U)
-#define BIT16 (0x00010000U)
-#define BIT17 (0x00020000U)
-#define BIT18 (0x00040000U)
-#define BIT19 (0x00080000U)
-#define BIT20 (0x00100000U)
-#define BIT21 (0x00200000U)
-#define BIT22 (0x00400000U)
-#define BIT23 (0x00800000U)
-#define BIT24 (0x01000000U)
-#define BIT25 (0x02000000U)
-#define BIT26 (0x04000000U)
-#define BIT27 (0x08000000U)
-#define BIT28 (0x10000000U)
-#define BIT29 (0x20000000U)
-#define BIT30 (0x40000000U)
-#define BIT31 (0x80000000U)
-
-/** @brief Clock Pulse Generator (CPG) registers
- */
-#define CPG_BASE (0xE6150000U)
-
-#define CPG_MSTPSR3 (CPG_BASE+0x0048U) /* Module stop status register 3 */
-
-#define CPG_SMSTPCR3 (CPG_BASE+0x013CU) /* System module stop control register 3 */
-
-#define CPG_SD2CKCR (CPG_BASE+0x0268U) /* SDHI2 clock frequency control register */
-#define CPG_SD3CKCR (CPG_BASE+0x026CU) /* SDHI3 clock frequency control register */
-
-#define CPG_CPGWPR (CPG_BASE+0x0900U) /* CPG Write Protect Register */
-
-#if USE_MMC_CH == MMC_CH0
-#define CPG_SDxCKCR (CPG_SD2CKCR) /* SDHI2/MMC0 */
-#else /* USE_MMC_CH == MMC_CH0 */
-#define CPG_SDxCKCR (CPG_SD3CKCR) /* SDHI3/MMC1 */
-#endif /* USE_MMC_CH == MMC_CH0 */
-
-/** Boot Status register
- */
-#define MFISBTSTSR (0xE6260604U)
-
-#define MFISBTSTSR_BOOT_PARTITION (0x00000010U)
-
-/** brief eMMC registers
- */
-#define MMC0_SD_BASE (0xEE140000U)
-#define MMC1_SD_BASE (0xEE160000U)
-
-#if USE_MMC_CH == MMC_CH0
-#define MMC_SD_BASE (MMC0_SD_BASE)
-#else /* USE_MMC_CH == MMC_CH0 */
-#define MMC_SD_BASE (MMC1_SD_BASE)
-#endif /* USE_MMC_CH == MMC_CH0 */
-
-#define SD_CMD (MMC_SD_BASE + 0x0000U)
-#define SD_PORTSEL (MMC_SD_BASE + 0x0008U)
-#define SD_ARG (MMC_SD_BASE + 0x0010U)
-#define SD_ARG1 (MMC_SD_BASE + 0x0018U)
-#define SD_STOP (MMC_SD_BASE + 0x0020U)
-#define SD_SECCNT (MMC_SD_BASE + 0x0028U)
-#define SD_RSP10 (MMC_SD_BASE + 0x0030U)
-#define SD_RSP1 (MMC_SD_BASE + 0x0038U)
-#define SD_RSP32 (MMC_SD_BASE + 0x0040U)
-#define SD_RSP3 (MMC_SD_BASE + 0x0048U)
-#define SD_RSP54 (MMC_SD_BASE + 0x0050U)
-#define SD_RSP5 (MMC_SD_BASE + 0x0058U)
-#define SD_RSP76 (MMC_SD_BASE + 0x0060U)
-#define SD_RSP7 (MMC_SD_BASE + 0x0068U)
-#define SD_INFO1 (MMC_SD_BASE + 0x0070U)
-#define SD_INFO2 (MMC_SD_BASE + 0x0078U)
-#define SD_INFO1_MASK (MMC_SD_BASE + 0x0080U)
-#define SD_INFO2_MASK (MMC_SD_BASE + 0x0088U)
-#define SD_CLK_CTRL (MMC_SD_BASE + 0x0090U)
-#define SD_SIZE (MMC_SD_BASE + 0x0098U)
-#define SD_OPTION (MMC_SD_BASE + 0x00A0U)
-#define SD_ERR_STS1 (MMC_SD_BASE + 0x00B0U)
-#define SD_ERR_STS2 (MMC_SD_BASE + 0x00B8U)
-#define SD_BUF0 (MMC_SD_BASE + 0x00C0U)
-#define SDIO_MODE (MMC_SD_BASE + 0x00D0U)
-#define SDIO_INFO1 (MMC_SD_BASE + 0x00D8U)
-#define SDIO_INFO1_MASK (MMC_SD_BASE + 0x00E0U)
-#define CC_EXT_MODE (MMC_SD_BASE + 0x0360U)
-#define SOFT_RST (MMC_SD_BASE + 0x0380U)
-#define VERSION (MMC_SD_BASE + 0x0388U)
-#define HOST_MODE (MMC_SD_BASE + 0x0390U)
-#define DM_CM_DTRAN_MODE (MMC_SD_BASE + 0x0820U)
-#define DM_CM_DTRAN_CTRL (MMC_SD_BASE + 0x0828U)
-#define DM_CM_RST (MMC_SD_BASE + 0x0830U)
-#define DM_CM_INFO1 (MMC_SD_BASE + 0x0840U)
-#define DM_CM_INFO1_MASK (MMC_SD_BASE + 0x0848U)
-#define DM_CM_INFO2 (MMC_SD_BASE + 0x0850U)
-#define DM_CM_INFO2_MASK (MMC_SD_BASE + 0x0858U)
-#define DM_DTRAN_ADDR (MMC_SD_BASE + 0x0880U)
-
-/** @brief SD_INFO1 Registers
- */
-#define SD_INFO1_HPIRES 0x00010000UL /* Response Reception Completion */
-#define SD_INFO1_INFO10 0x00000400UL /* Indicates the SDDAT3 state */
-#define SD_INFO1_INFO9 0x00000200UL /* SDDAT3 Card Insertion */
-#define SD_INFO1_INFO8 0x00000100UL /* SDDAT3 Card Removal */
-#define SD_INFO1_INFO7 0x00000080UL /* Write Protect */
-#define SD_INFO1_INFO5 0x00000020UL /* Indicates the ISDCD state */
-#define SD_INFO1_INFO4 0x00000010UL /* ISDCD Card Insertion */
-#define SD_INFO1_INFO3 0x00000008UL /* ISDCD Card Removal */
-#define SD_INFO1_INFO2 0x00000004UL /* Access end */
-#define SD_INFO1_INFO0 0x00000001UL /* Response end */
-
-/** @brief SD_INFO2 Registers
- */
-#define SD_INFO2_ILA 0x00008000UL /* Illegal Access Error */
-#define SD_INFO2_CBSY 0x00004000UL /* Command Type Register Busy */
-#define SD_INFO2_SCLKDIVEN 0x00002000UL
-#define SD_INFO2_BWE 0x00000200UL /* SD_BUF Write Enable */
-#define SD_INFO2_BRE 0x00000100UL /* SD_BUF Read Enable */
-#define SD_INFO2_DAT0 0x00000080UL /* SDDAT0 */
-#define SD_INFO2_ERR6 0x00000040UL /* Response Timeout */
-#define SD_INFO2_ERR5 0x00000020UL /* SD_BUF Illegal Read Access */
-#define SD_INFO2_ERR4 0x00000010UL /* SD_BUF Illegal Write Access */
-#define SD_INFO2_ERR3 0x00000008UL /* Data Timeout */
-#define SD_INFO2_ERR2 0x00000004UL /* END Error */
-#define SD_INFO2_ERR1 0x00000002UL /* CRC Error */
-#define SD_INFO2_ERR0 0x00000001UL /* CMD Error */
-#define SD_INFO2_ALL_ERR 0x0000807FUL
-#define SD_INFO2_CLEAR 0x00000800UL /* BIT11 The write value should always be 1. HWM_0003 */
-
-/** @brief SOFT_RST
- */
-#define SOFT_RST_SDRST 0x00000001UL
-
-/** @brief SD_CLK_CTRL
- */
-#define SD_CLK_CTRL_SDCLKOFFEN 0x00000200UL
-#define SD_CLK_CTRL_SCLKEN 0x00000100UL
-#define SD_CLK_CTRL_CLKDIV_MASK 0x000000FFUL
-#define SD_CLOCK_ENABLE 0x00000100UL
-#define SD_CLOCK_DISABLE 0x00000000UL
-#define SD_CLK_WRITE_MASK 0x000003FFUL
-#define SD_CLK_CLKDIV_CLEAR_MASK 0xFFFFFF0FUL
-
-/** @brief SD_OPTION
- */
-#define SD_OPTION_TIMEOUT_CNT_MASK 0x000000F0UL
-
-/** @brief MMC Clock Frequency
- * 200MHz * 1/x = output clock
- */
-#define MMC_CLK_OFF 0UL /* Clock output is disabled */
-#define MMC_400KHZ 512UL /* 200MHz * 1/512 = 390 KHz */
-#define MMC_20MHZ 16UL /* 200MHz * 1/16 = 12.5 MHz Normal speed mode */
-#define MMC_26MHZ 8UL /* 200MHz * 1/8 = 25 MHz High speed mode 26Mhz */
-#define MMC_52MHZ 4UL /* 200MHz * 1/4 = 50 MHz High speed mode 52Mhz */
-#define MMC_100MHZ 2UL /* 200MHz * 1/2 = 100 MHz */
-#define MMC_200MHZ 1UL /* 200MHz * 1/1 = 200 MHz */
-
-#define MMC_FREQ_52MHZ 52000000UL
-#define MMC_FREQ_26MHZ 26000000UL
-#define MMC_FREQ_20MHZ 20000000UL
-
-/** @brief MMC Clock DIV
- */
-#define MMC_SD_CLK_START 0x00000100UL /* CLOCK On */
-#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */
-#define MMC_SD_CLK_DIV1 0x000000FFUL /* 1/1 */
-#define MMC_SD_CLK_DIV2 0x00000000UL /* 1/2 */
-#define MMC_SD_CLK_DIV4 0x00000001UL /* 1/4 */
-#define MMC_SD_CLK_DIV8 0x00000002UL /* 1/8 */
-#define MMC_SD_CLK_DIV16 0x00000004UL /* 1/16 */
-#define MMC_SD_CLK_DIV32 0x00000008UL /* 1/32 */
-#define MMC_SD_CLK_DIV64 0x00000010UL /* 1/64 */
-#define MMC_SD_CLK_DIV128 0x00000020UL /* 1/128 */
-#define MMC_SD_CLK_DIV256 0x00000040UL /* 1/256 */
-#define MMC_SD_CLK_DIV512 0x00000080UL /* 1/512 */
-
-/** @brief DM_CM_DTRAN_MODE
- */
-#define DM_CM_DTRAN_MODE_CH0 0x00000000UL /* CH0(downstream) */
-#define DM_CM_DTRAN_MODE_CH1 0x00010000UL /* CH1(upstream) */
-#define DM_CM_DTRAN_MODE_BIT_WIDTH 0x00000030UL
-
-/** @brief CC_EXT_MODE
- */
-#define CC_EXT_MODE_DMASDRW_ENABLE 0x00000002UL /* SD_BUF Read/Write DMA Transfer */
-#define CC_EXT_MODE_CLEAR 0x00001010UL /* BIT 12 & 4 always 1. */
-
-/** @brief DM_CM_INFO_MASK
- */
-#define DM_CM_INFO_MASK_CLEAR 0xFFFCFFFEUL
-#define DM_CM_INFO_CH0_ENABLE 0x00010001UL
-#define DM_CM_INFO_CH1_ENABLE 0x00020001UL
-
-/** @brief DM_DTRAN_ADDR
- */
-#define DM_DTRAN_ADDR_WRITE_MASK 0xFFFFFFF8UL
-
-/** @brief DM_CM_DTRAN_CTRL
- */
-#define DM_CM_DTRAN_CTRL_START 0x00000001UL
-
-/** @brief SYSC Registers
- */
-#if USE_MMC_CH == MMC_CH0
-#define CPG_MSTP_MMC (BIT12) /* SDHI2/MMC0 */
-#else /* USE_MMC_CH == MMC_CH0 */
-#define CPG_MSTP_MMC (BIT11) /* SDHI3/MMC1 */
-#endif /* USE_MMC_CH == MMC_CH0 */
-
-/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
-
-/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
-
-/* ************************** FUNCTION PROTOTYPES ************************** */
-
-/* ********************************* CODE ********************************** */
-
-#endif /* EMMC_REGISTERS_H */
-/* ******************************** END ************************************ */
diff --git a/drivers/renesas/rcar/emmc/emmc_std.h b/drivers/renesas/rcar/emmc/emmc_std.h
deleted file mode 100644
index 99cb6b992a..0000000000
--- a/drivers/renesas/rcar/emmc/emmc_std.h
+++ /dev/null
@@ -1,474 +0,0 @@
-/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/**
- * @file emmc_std.h
- * @brief eMMC boot is expecting this header file
- *
- */
-
-#ifndef EMMC_STD_H
-#define EMMC_STD_H
-
-#include "emmc_hal.h"
-
-/* ************************ HEADER (INCLUDE) SECTION *********************** */
-
-/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
-#ifndef FALSE
-#define FALSE 0U
-#endif
-#ifndef TRUE
-#define TRUE 1U
-#endif
-
-/** @brief 64bit registers
- **/
-#define SETR_64(r, v) (*(volatile uint64_t *)(r) = (v))
-#define GETR_64(r) (*(volatile uint64_t *)(r))
-
-/** @brief 32bit registers
- **/
-#define SETR_32(r, v) (*(volatile uint32_t *)(r) = (v))
-#define GETR_32(r) (*(volatile uint32_t *)(r))
-
-/** @brief 16bit registers
- */
-#define SETR_16(r, v) (*(volatile uint16_t *)(r) = (v))
-#define GETR_16(r) (*(volatile uint16_t *)(r))
-
-/** @brief 8bit registers
- */
-#define SETR_8(r, v) (*(volatile uint8_t *)(r) = (v))
-#define GETR_8(r) (*(volatile uint8_t *)(r))
-
-/** @brief CSD register Macros
- */
-#define EMMC_GET_CID(x, y) (emmc_bit_field(mmc_drv_obj.cid_data, (x), (y)))
-
-#define EMMC_CID_MID() (EMMC_GET_CID(127, 120))
-#define EMMC_CID_CBX() (EMMC_GET_CID(113, 112))
-#define EMMC_CID_OID() (EMMC_GET_CID(111, 104))
-#define EMMC_CID_PNM1() (EMMC_GET_CID(103, 88))
-#define EMMC_CID_PNM2() (EMMC_GET_CID(87, 56))
-#define EMMC_CID_PRV() (EMMC_GET_CID(55, 48))
-#define EMMC_CID_PSN() (EMMC_GET_CID(47, 16))
-#define EMMC_CID_MDT() (EMMC_GET_CID(15, 8))
-#define EMMC_CID_CRC() (EMMC_GET_CID(7, 1))
-
-/** @brief CSD register Macros
- */
-#define EMMC_GET_CSD(x, y) (emmc_bit_field(mmc_drv_obj.csd_data, (x), (y)))
-
-#define EMMC_CSD_CSD_STRUCTURE() (EMMC_GET_CSD(127, 126))
-#define EMMC_CSD_SPEC_VARS() (EMMC_GET_CSD(125, 122))
-#define EMMC_CSD_TAAC() (EMMC_GET_CSD(119, 112))
-#define EMMC_CSD_NSAC() (EMMC_GET_CSD(111, 104))
-#define EMMC_CSD_TRAN_SPEED() (EMMC_GET_CSD(103, 96))
-#define EMMC_CSD_CCC() (EMMC_GET_CSD(95, 84))
-#define EMMC_CSD_READ_BL_LEN() (EMMC_GET_CSD(83, 80))
-#define EMMC_CSD_READ_BL_PARTIAL() (EMMC_GET_CSD(79, 79))
-#define EMMC_CSD_WRITE_BLK_MISALIGN() (EMMC_GET_CSD(78, 78))
-#define EMMC_CSD_READ_BLK_MISALIGN() (EMMC_GET_CSD(77, 77))
-#define EMMC_CSD_DSR_IMP() (EMMC_GET_CSD(76, 76))
-#define EMMC_CSD_C_SIZE() (EMMC_GET_CSD(73, 62))
-#define EMMC_CSD_VDD_R_CURR_MIN() (EMMC_GET_CSD(61, 59))
-#define EMMC_CSD_VDD_R_CURR_MAX() (EMMC_GET_CSD(58, 56))
-#define EMMC_CSD_VDD_W_CURR_MIN() (EMMC_GET_CSD(55, 53))
-#define EMMC_CSD_VDD_W_CURR_MAX() (EMMC_GET_CSD(52, 50))
-#define EMMC_CSD_C_SIZE_MULT() (EMMC_GET_CSD(49, 47))
-#define EMMC_CSD_ERASE_GRP_SIZE() (EMMC_GET_CSD(46, 42))
-#define EMMC_CSD_ERASE_GRP_MULT() (EMMC_GET_CSD(41, 37))
-#define EMMC_CSD_WP_GRP_SIZE() (EMMC_GET_CSD(36, 32))
-#define EMMC_CSD_WP_GRP_ENABLE() (EMMC_GET_CSD(31, 31))
-#define EMMC_CSD_DEFALT_ECC() (EMMC_GET_CSD(30, 29))
-#define EMMC_CSD_R2W_FACTOR() (EMMC_GET_CSD(28, 26))
-#define EMMC_CSD_WRITE_BL_LEN() (EMMC_GET_CSD(25, 22))
-#define EMMC_CSD_WRITE_BL_PARTIAL() (EMMC_GET_CSD(21, 21))
-#define EMMC_CSD_CONTENT_PROT_APP() (EMMC_GET_CSD(16, 16))
-#define EMMC_CSD_FILE_FORMAT_GRP() (EMMC_GET_CSD(15, 15))
-#define EMMC_CSD_COPY() (EMMC_GET_CSD(14, 14))
-#define EMMC_CSD_PERM_WRITE_PROTECT() (EMMC_GET_CSD(13, 13))
-#define EMMC_CSD_TMP_WRITE_PROTECT() (EMMC_GET_CSD(12, 12))
-#define EMMC_CSD_FILE_FORMAT() (EMMC_GET_CSD(11, 10))
-#define EMMC_CSD_ECC() (EMMC_GET_CSD(9, 8))
-#define EMMC_CSD_CRC() (EMMC_GET_CSD(7, 1))
-
-/** @brief for sector access
- */
-#define EMMC_4B_BOUNDARY_CHECK_MASK 0x00000003
-#define EMMC_SECTOR_SIZE_SHIFT 9U /* 512 = 2^9 */
-#define EMMC_SECTOR_SIZE 512
-#define EMMC_BLOCK_LENGTH 512
-#define EMMC_BLOCK_LENGTH_DW 128
-#define EMMC_BUF_SIZE_SHIFT 3U /* 8byte = 2^3 */
-
-/** @brief eMMC specification clock
- */
-#define EMMC_CLOCK_SPEC_400K 400000UL /**< initialize clock 400KHz */
-#define EMMC_CLOCK_SPEC_20M 20000000UL /**< normal speed 20MHz */
-#define EMMC_CLOCK_SPEC_26M 26000000UL /**< high speed 26MHz */
-#define EMMC_CLOCK_SPEC_52M 52000000UL /**< high speed 52MHz */
-#define EMMC_CLOCK_SPEC_100M 100000000UL /**< high speed 100MHz */
-
-/** @brief EMMC driver error code. (extended HAL_MEMCARD_RETURN)
- */
-typedef enum {
- EMMC_ERR = 0, /**< unknown error */
- EMMC_SUCCESS, /**< OK */
- EMMC_ERR_FROM_DMAC, /**< DMAC allocation error */
- EMMC_ERR_FROM_DMAC_TRANSFER, /**< DMAC transfer error */
- EMMC_ERR_CARD_STATUS_BIT, /**< card status error. Non-masked error bit was set in the card status */
- EMMC_ERR_CMD_TIMEOUT, /**< command timeout error */
- EMMC_ERR_DATA_TIMEOUT, /**< data timeout error */
- EMMC_ERR_CMD_CRC, /**< command CRC error */
- EMMC_ERR_DATA_CRC, /**< data CRC error */
- EMMC_ERR_PARAM, /**< parameter error */
- EMMC_ERR_RESPONSE, /**< response error */
- EMMC_ERR_RESPONSE_BUSY, /**< response busy error */
- EMMC_ERR_TRANSFER, /**< data transfer error */
- EMMC_ERR_READ_SECTOR, /**< read sector error */
- EMMC_ERR_WRITE_SECTOR, /**< write sector error */
- EMMC_ERR_STATE, /**< state error */
- EMMC_ERR_TIMEOUT, /**< timeout error */
- EMMC_ERR_ILLEGAL_CARD, /**< illegal card */
- EMMC_ERR_CARD_BUSY, /**< Busy state */
- EMMC_ERR_CARD_STATE, /**< card state error */
- EMMC_ERR_SET_TRACE, /**< trace information error */
- EMMC_ERR_FROM_TIMER, /**< Timer error */
- EMMC_ERR_FORCE_TERMINATE, /**< Force terminate */
- EMMC_ERR_CARD_POWER, /**< card power fail */
- EMMC_ERR_ERASE_SECTOR, /**< erase sector error */
- EMMC_ERR_INFO2 /**< exec cmd error info2 */
-} EMMC_ERROR_CODE;
-
-/** @brief Function number */
-#define EMMC_FUNCNO_NONE 0U
-#define EMMC_FUNCNO_DRIVER_INIT 1U
-#define EMMC_FUNCNO_CARD_POWER_ON 2U
-#define EMMC_FUNCNO_MOUNT 3U
-#define EMMC_FUNCNO_CARD_INIT 4U
-#define EMMC_FUNCNO_HIGH_SPEED 5U
-#define EMMC_FUNCNO_BUS_WIDTH 6U
-#define EMMC_FUNCNO_MULTI_BOOT_SELECT_PARTITION 7U
-#define EMMC_FUNCNO_MULTI_BOOT_READ_SECTOR 8U
-#define EMMC_FUNCNO_TRANS_DATA_READ_SECTOR 9U
-#define EMMC_FUNCNO_UBOOT_IMAGE_SELECT_PARTITION 10U
-#define EMMC_FUNCNO_UBOOT_IMAGE_READ_SECTOR 11U
-#define EMMC_FUNCNO_SET_CLOCK 12U
-#define EMMC_FUNCNO_EXEC_CMD 13U
-#define EMMC_FUNCNO_READ_SECTOR 14U
-#define EMMC_FUNCNO_WRITE_SECTOR 15U
-#define EMMC_FUNCNO_ERASE_SECTOR 16U
-#define EMMC_FUNCNO_GET_PERTITION_ACCESS 17U
-/** @brief Response
- */
-/** R1 */
-#define EMMC_R1_ERROR_MASK 0xFDBFE080U /* Type 'E' bit and bit14(must be 0). ignore bit22 */
-#define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U) /* Ignore bit23 (Not check CRC error) */
-#define EMMC_R1_STATE_MASK 0x00001E00U /* [12:9] */
-#define EMMC_R1_READY 0x00000100U /* bit8 */
-#define EMMC_R1_STATE_SHIFT 9
-
-/** R4 */
-#define EMMC_R4_RCA_MASK 0xFFFF0000UL
-#define EMMC_R4_STATUS 0x00008000UL
-
-/** CSD */
-#define EMMC_TRANSPEED_FREQ_UNIT_MASK 0x07 /* bit[2:0] */
-#define EMMC_TRANSPEED_FREQ_UNIT_SHIFT 0
-#define EMMC_TRANSPEED_MULT_MASK 0x78 /* bit[6:3] */
-#define EMMC_TRANSPEED_MULT_SHIFT 3
-
-/** OCR */
-#define EMMC_HOST_OCR_VALUE 0x40FF8080
-#define EMMC_OCR_STATUS_BIT 0x80000000L /* Card power up status bit */
-#define EMMC_OCR_ACCESS_MODE_MASK 0x60000000L /* bit[30:29] */
-#define EMMC_OCR_ACCESS_MODE_SECT 0x40000000L
-#define EMMC_OCR_ACCESS_MODE_BYTE 0x00000000L
-
-/** EXT_CSD */
-#define EMMC_EXT_CSD_S_CMD_SET 504
-#define EMMC_EXT_CSD_INI_TIMEOUT_AP 241
-#define EMMC_EXT_CSD_PWR_CL_DDR_52_360 239
-#define EMMC_EXT_CSD_PWR_CL_DDR_52_195 238
-#define EMMC_EXT_CSD_MIN_PERF_DDR_W_8_52 235
-#define EMMC_EXT_CSD_MIN_PERF_DDR_R_8_52 234
-#define EMMC_EXT_CSD_TRIM_MULT 232
-#define EMMC_EXT_CSD_SEC_FEATURE_SUPPORT 231
-#define EMMC_EXT_CSD_SEC_ERASE_MULT 229
-#define EMMC_EXT_CSD_BOOT_INFO 228
-#define EMMC_EXT_CSD_BOOT_SIZE_MULTI 226
-#define EMMC_EXT_CSD_ACC_SIZE 225
-#define EMMC_EXT_CSD_HC_ERASE_GRP_SIZE 224
-#define EMMC_EXT_CSD_ERASE_TIMEOUT_MULT 223
-#define EMMC_EXT_CSD_PEL_WR_SEC_C 222
-#define EMMC_EXT_CSD_HC_WP_GRP_SIZE 221
-#define EMMC_EXT_CSD_S_C_VCC 220
-#define EMMC_EXT_CSD_S_C_VCCQ 219
-#define EMMC_EXT_CSD_S_A_TIMEOUT 217
-#define EMMC_EXT_CSD_SEC_COUNT 215
-#define EMMC_EXT_CSD_MIN_PERF_W_8_52 210
-#define EMMC_EXT_CSD_MIN_PERF_R_8_52 209
-#define EMMC_EXT_CSD_MIN_PERF_W_8_26_4_52 208
-#define EMMC_EXT_CSD_MIN_PERF_R_8_26_4_52 207
-#define EMMC_EXT_CSD_MIN_PERF_W_4_26 206
-#define EMMC_EXT_CSD_MIN_PERF_R_4_26 205
-#define EMMC_EXT_CSD_PWR_CL_26_360 203
-#define EMMC_EXT_CSD_PWR_CL_52_360 202
-#define EMMC_EXT_CSD_PWR_CL_26_195 201
-#define EMMC_EXT_CSD_PWR_CL_52_195 200
-#define EMMC_EXT_CSD_CARD_TYPE 196
-#define EMMC_EXT_CSD_CSD_STRUCTURE 194
-#define EMMC_EXT_CSD_EXT_CSD_REV 192
-#define EMMC_EXT_CSD_CMD_SET 191
-#define EMMC_EXT_CSD_CMD_SET_REV 189
-#define EMMC_EXT_CSD_POWER_CLASS 187
-#define EMMC_EXT_CSD_HS_TIMING 185
-#define EMMC_EXT_CSD_BUS_WIDTH 183
-#define EMMC_EXT_CSD_ERASED_MEM_CONT 181
-#define EMMC_EXT_CSD_PARTITION_CONFIG 179
-#define EMMC_EXT_CSD_BOOT_CONFIG_PROT 178
-#define EMMC_EXT_CSD_BOOT_BUS_WIDTH 177
-#define EMMC_EXT_CSD_ERASE_GROUP_DEF 175
-#define EMMC_EXT_CSD_BOOT_WP 173
-#define EMMC_EXT_CSD_USER_WP 171
-#define EMMC_EXT_CSD_FW_CONFIG 169
-#define EMMC_EXT_CSD_RPMB_SIZE_MULT 168
-#define EMMC_EXT_CSD_RST_n_FUNCTION 162
-#define EMMC_EXT_CSD_PARTITIONING_SUPPORT 160
-#define EMMC_EXT_CSD_MAX_ENH_SIZE_MULT 159
-#define EMMC_EXT_CSD_PARTITIONS_ATTRIBUTE 156
-#define EMMC_EXT_CSD_PARTITION_SETTING_COMPLETED 155
-#define EMMC_EXT_CSD_GP_SIZE_MULT 154
-#define EMMC_EXT_CSD_ENH_SIZE_MULT 142
-#define EMMC_EXT_CSD_ENH_START_ADDR 139
-#define EMMC_EXT_CSD_SEC_BAD_BLK_MGMNT 134
-
-#define EMMC_EXT_CSD_CARD_TYPE_26MHZ 0x01
-#define EMMC_EXT_CSD_CARD_TYPE_52MHZ 0x02
-#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_12V 0x04
-#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_18V 0x08
-#define EMMC_EXT_CSD_CARD_TYPE_52MHZ_MASK 0x0e
-
-/** SWITCH (CMD6) argument */
-#define EXTCSD_ACCESS_BYTE (BIT25|BIT24)
-#define EXTCSD_SET_BITS BIT24
-
-#define HS_TIMING_ADD (185<<16) /* H'b9 */
-#define HS_TIMING_1 (1<<8)
-#define HS_TIMING_HS200 (2<<8)
-#define HS_TIMING_HS400 (3<<8)
-
-#define BUS_WIDTH_ADD (183<<16) /* H'b7 */
-#define BUS_WIDTH_1 (0<<8)
-#define BUS_WIDTH_4 (1<<8)
-#define BUS_WIDTH_8 (2<<8)
-#define BUS_WIDTH_4DDR (5<<8)
-#define BUS_WIDTH_8DDR (6<<8)
-
-#define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_1) /**< H'03b90100 */
-#define EMMC_SWITCH_HS_TIMING_OFF (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD) /**< H'03b90000 */
-
-#define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_1) /**< H'03b70000 */
-#define EMMC_SWITCH_BUS_WIDTH_4 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_4) /**< H'03b70100 */
-#define EMMC_SWITCH_BUS_WIDTH_8 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8) /**< H'03b70200 */
-#define EMMC_SWITCH_BUS_WIDTH_4DDR (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_4DDR) /**< H'03b70500 */
-#define EMMC_SWITCH_BUS_WIDTH_8DDR (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8DDR) /**< H'03b70600 */
-#define EMMC_SWITCH_PARTITION_CONFIG 0x03B30000UL /**< Partition config = 0x00 */
-
-#define TIMING_HIGH_SPEED 1UL
-#define EMMC_BOOT_PARTITION_EN_MASK 0x38U
-#define EMMC_BOOT_PARTITION_EN_SHIFT 3U
-
-/** Bus width */
-#define EMMC_BUSWIDTH_1BIT CE_CMD_SET_DATW_1BIT
-#define EMMC_BUSWIDTH_4BIT CE_CMD_SET_DATW_4BIT
-#define EMMC_BUSWIDTH_8BIT CE_CMD_SET_DATW_8BIT
-
-/** for st_mmc_base */
-#define EMMC_MAX_RESPONSE_LENGTH 17
-#define EMMC_MAX_CID_LENGTH 16
-#define EMMC_MAX_CSD_LENGTH 16
-#define EMMC_MAX_EXT_CSD_LENGTH 512U
-#define EMMC_RES_REG_ALIGNED 4U
-#define EMMC_BUF_REG_ALIGNED 8U
-
-/** @brief for TAAC mask
- */
-#define TAAC_TIME_UNIT_MASK (0x07)
-#define TAAC_MULTIPLIER_FACTOR_MASK (0x0F)
-
-/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
-
-/** @brief Partition id
- */
-typedef enum {
- PARTITION_ID_USER = 0x0, /**< User Area */
- PARTITION_ID_BOOT_1 = 0x1, /**< boot partition 1 */
- PARTITION_ID_BOOT_2 = 0x2, /**< boot partition 2 */
- PARTITION_ID_RPMB = 0x3, /**< Replay Protected Memory Block */
- PARTITION_ID_GP_1 = 0x4, /**< General Purpose partition 1 */
- PARTITION_ID_GP_2 = 0x5, /**< General Purpose partition 2 */
- PARTITION_ID_GP_3 = 0x6, /**< General Purpose partition 3 */
- PARTITION_ID_GP_4 = 0x7, /**< General Purpose partition 4 */
- PARTITION_ID_MASK = 0x7 /**< [2:0] */
-} EMMC_PARTITION_ID;
-
-/** @brief card state in R1 response [12:9]
- */
-typedef enum {
- EMMC_R1_STATE_IDLE = 0,
- EMMC_R1_STATE_READY,
- EMMC_R1_STATE_IDENT,
- EMMC_R1_STATE_STBY,
- EMMC_R1_STATE_TRAN,
- EMMC_R1_STATE_DATA,
- EMMC_R1_STATE_RCV,
- EMMC_R1_STATE_PRG,
- EMMC_R1_STATE_DIS,
- EMMC_R1_STATE_BTST,
- EMMC_R1_STATE_SLEP
-} EMMC_R1_STATE;
-
-typedef enum {
- ESTATE_BEGIN = 0,
- ESTATE_ISSUE_CMD,
- ESTATE_NON_RESP_CMD,
- ESTATE_RCV_RESP,
- ESTATE_RCV_RESPONSE_BUSY,
- ESTATE_CHECK_RESPONSE_COMPLETE,
- ESTATE_DATA_TRANSFER,
- ESTATE_DATA_TRANSFER_COMPLETE,
- ESTATE_ACCESS_END,
- ESTATE_TRANSFER_ERROR,
- ESTATE_ERROR,
- ESTATE_END
-} EMMC_INT_STATE;
-
-/** @brief eMMC boot driver error information
- */
-typedef struct {
- uint16_t num; /**< error no */
- uint16_t code; /**< error code */
- volatile uint32_t info1; /**< SD_INFO1 register value. (hardware dependence) */
- volatile uint32_t info2; /**< SD_INFO2 register value. (hardware dependence) */
- volatile uint32_t status1;/**< SD_ERR_STS1 register value. (hardware dependence) */
- volatile uint32_t status2;/**< SD_ERR_STS2 register value. (hardware dependence) */
- volatile uint32_t dm_info1;/**< DM_CM_INFO1 register value. (hardware dependence) */
- volatile uint32_t dm_info2;/**< DM_CM_INFO2 register value. (hardware dependence) */
-} st_error_info;
-
-/** @brief Command information
- */
-typedef struct {
- HAL_MEMCARD_COMMAND cmd; /**< Command information */
- uint32_t arg; /**< argument */
- HAL_MEMCARD_OPERATION dir; /**< direction */
- uint32_t hw; /**< H/W dependence. SD_CMD register value. */
-} st_command_info;
-
-/** @brief MMC driver base
- */
-typedef struct {
- st_error_info error_info; /**< error information */
- st_command_info cmd_info; /**< command information */
-
- /* for data transfer */
- uint32_t *buff_address_virtual; /**< Dest or Src buff */
- uint32_t *buff_address_physical; /**< Dest or Src buff */
- HAL_MEMCARD_DATA_WIDTH bus_width;
- /**< bus width */
- uint32_t trans_size; /**< transfer size for this command */
- uint32_t remain_size; /**< remain size for this command */
- uint32_t response_length; /**< response length for this command */
- uint32_t sector_size; /**< sector_size */
-
- /* clock */
- uint32_t base_clock; /**< MMC host controller clock */
- uint32_t max_freq; /**< Max frequency (Card Spec)[Hz]. It changes dynamically by CSD and EXT_CSD. */
- uint32_t request_freq; /**< request freq [Hz] (400K, 26MHz, 52MHz, etc) */
- uint32_t current_freq; /**< current MMC clock[Hz] (the closest frequency supported by HW) */
-
- /* state flag */
- HAL_MEMCARD_PRESENCE_STATUS card_present;
- /**< presence status of the memory card */
- uint32_t card_power_enable; /**< True : Power ON */
- uint32_t clock_enable; /**< True : Clock ON */
- uint32_t initialize; /**< True : initialize complete. */
- uint32_t access_mode; /**< True : sector access, FALSE : byte access */
- uint32_t mount; /**< True : mount complete. */
- uint32_t selected; /**< True : selected card. */
- HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode;
- /**< 0: DMA, 1:PIO */
- uint32_t image_num; /**< loaded ISSW image No. ISSW have copy image. */
- EMMC_R1_STATE current_state; /**< card state */
- volatile uint32_t during_cmd_processing; /**< True : during command processing */
- volatile uint32_t during_transfer; /**< True : during transfer */
- volatile uint32_t during_dma_transfer; /**< True : during transfer (DMA)*/
- volatile uint32_t dma_error_flag; /**< True : occurred DMAC error */
- volatile uint32_t force_terminate; /**< force terminate flag */
- volatile uint32_t state_machine_blocking; /**< state machine blocking flag : True or False */
- volatile uint32_t get_partition_access_flag;
- /**< True : get partition access processing */
-
- EMMC_PARTITION_ID boot_partition_en; /**< Boot partition */
- EMMC_PARTITION_ID partition_access; /**< Current access partition */
-
- /* timeout */
- uint32_t hs_timing; /**< high speed */
-
- /* timeout */
- uint32_t data_timeout; /**< read and write data timeout.*/
-
- /* retry */
- uint32_t retries_after_fail; /**< how many times to try after fail, for instance sending command */
-
- /* interrupt */
- volatile uint32_t int_event1; /**< interrupt SD_INFO1 Event */
- volatile uint32_t int_event2; /**< interrupt SD_INFO2 Event */
- volatile uint32_t dm_event1; /**< interrupt DM_CM_INFO1 Event */
- volatile uint32_t dm_event2; /**< interrupt DM_CM_INFO2 Event */
-
- /* response */
- uint32_t *response; /**< pointer to buffer for executing command. */
- uint32_t r1_card_status; /**< R1 response data */
- uint32_t r3_ocr; /**< R3 response data */
- uint32_t r4_resp; /**< R4 response data */
- uint32_t r5_resp; /**< R5 response data */
-
- uint32_t low_clock_mode_enable;
- /**< True : clock mode is low. (MMC clock = Max26MHz) */
- uint32_t reserved2;
- uint32_t reserved3;
- uint32_t reserved4;
-
- /* CSD registers (4byte align) */
- uint8_t csd_data[EMMC_MAX_CSD_LENGTH] /**< CSD */
- __attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
- /* CID registers (4byte align) */
- uint8_t cid_data[EMMC_MAX_CID_LENGTH] /**< CID */
- __attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
- /* EXT CSD registers (8byte align) */
- uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH] /**< EXT_CSD */
- __attribute__ ((aligned(EMMC_BUF_REG_ALIGNED)));
- /* Response registers (4byte align) */
- uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH] /**< other response */
- __attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
-} st_mmc_base;
-
-typedef int (*func) (void);
-
-/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
-
-/* ************************** FUNCTION PROTOTYPES ************************** */
-uint32_t emmc_get_csd_time(void);
-
-#define MMC_DEBUG
-/* ********************************* CODE ********************************** */
-
-/* ******************************** END ************************************ */
-#endif /* EMMC_STD_H */
diff --git a/drivers/renesas/rzg/board/board.c b/drivers/renesas/rzg/board/board.c
new file mode 100644
index 0000000000..cfbb047194
--- /dev/null
+++ b/drivers/renesas/rzg/board/board.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+#include "board.h"
+#include "rcar_def.h"
+
+#ifndef BOARD_DEFAULT
+#define BOARD_DEFAULT (BOARD_HIHOPE_RZ_G2M << BOARD_CODE_SHIFT)
+#endif /* BOARD_DEFAULT */
+
+#define BOARD_CODE_MASK (0xF8U)
+#define BOARD_REV_MASK (0x07U)
+#define BOARD_CODE_SHIFT (0x03)
+#define BOARD_ID_UNKNOWN (0xFFU)
+
+#define GPIO_INDT5 0xE605500C
+#define GP5_19_BIT (0x01U << 19)
+#define GP5_21_BIT (0x01U << 21)
+#define GP5_25_BIT (0x01U << 25)
+
+#define HM_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+
+const char *g_board_tbl[] = {
+ [BOARD_HIHOPE_RZ_G2M] = "HiHope RZ/G2M",
+ [BOARD_UNKNOWN] = "unknown"
+};
+
+void rzg_get_board_type(uint32_t *type, uint32_t *rev)
+{
+ static uint8_t board_id = BOARD_ID_UNKNOWN;
+ const uint8_t board_tbl[][8] = {
+ [BOARD_HIHOPE_RZ_G2M] = HM_ID,
+ };
+ uint32_t reg, boardInfo;
+
+ if (board_id == BOARD_ID_UNKNOWN) {
+ board_id = BOARD_DEFAULT;
+ }
+
+ *type = ((uint32_t) board_id & BOARD_CODE_MASK) >> BOARD_CODE_SHIFT;
+
+ if (*type >= ARRAY_SIZE(board_tbl)) {
+ /* no revision information, set Rev0.0. */
+ *rev = 0;
+ } else {
+ reg = mmio_read_32(RCAR_PRR);
+ if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) {
+ *rev = board_tbl[*type][(uint8_t)(board_id & BOARD_REV_MASK)];
+ } else {
+ boardInfo = mmio_read_32(GPIO_INDT5) &
+ (GP5_19_BIT | GP5_21_BIT);
+ *rev = (((boardInfo & GP5_19_BIT) >> 14) |
+ ((boardInfo & GP5_21_BIT) >> 17)) + 0x30U;
+ }
+ }
+}
diff --git a/drivers/renesas/rzg/board/board.h b/drivers/renesas/rzg/board/board.h
new file mode 100644
index 0000000000..c0c3d0cda3
--- /dev/null
+++ b/drivers/renesas/rzg/board/board.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RZ_G2_BOARD_H
+#define RZ_G2_BOARD_H
+
+enum rzg2_board_id {
+ BOARD_HIHOPE_RZ_G2M = 0,
+ BOARD_UNKNOWN
+};
+
+#define BOARD_REV_UNKNOWN (0xFFU)
+
+extern const char *g_board_tbl[];
+
+/************************************************************************
+ * Revisions are expressed in 8 bits.
+ * The upper 4 bits are major version.
+ * The lower 4 bits are minor version.
+ ************************************************************************/
+#define GET_BOARD_MAJOR(a) ((uint32_t)(a) >> 0x4)
+#define GET_BOARD_MINOR(a) ((uint32_t)(a) & 0xF)
+#define GET_BOARD_NAME(a) (g_board_tbl[(a)])
+
+void rzg_get_board_type(uint32_t *type, uint32_t *rev);
+
+#endif /* RZ_G2_BOARD_H */
diff --git a/drivers/renesas/rzg/ddr/boot_init_dram.h b/drivers/renesas/rzg/ddr/boot_init_dram.h
new file mode 100644
index 0000000000..294582fa70
--- /dev/null
+++ b/drivers/renesas/rzg/ddr/boot_init_dram.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BOOT_INIT_DRAM_H
+#define BOOT_INIT_DRAM_H
+
+extern int32_t rzg_dram_init(void);
+
+#define INITDRAM_OK 0
+#define INITDRAM_NG 0xffffffff
+#define INITDRAM_ERR_I 0xffffffff
+#define INITDRAM_ERR_O 0xfffffffe
+#define INITDRAM_ERR_T 0xfffffff0
+
+#endif /* BOOT_INIT_DRAM_H */
diff --git a/drivers/renesas/rzg/ddr/ddr.mk b/drivers/renesas/rzg/ddr/ddr.mk
new file mode 100644
index 0000000000..7558216e3b
--- /dev/null
+++ b/drivers/renesas/rzg/ddr/ddr.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk
diff --git a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c
new file mode 100644
index 0000000000..45259e3c50
--- /dev/null
+++ b/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c
@@ -0,0 +1,3700 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "boot_init_dram.h"
+#include "boot_init_dram_regdef.h"
+#include "ddr_regdef.h"
+#include "dram_sub_func.h"
+#include "init_dram_tbl_g2m.h"
+#include "micro_delay.h"
+#include "rcar_def.h"
+
+/* load board configuration */
+#include "boot_init_dram_config.c"
+
+#define DDR_BACKUPMODE
+#define FATAL_MSG(x) NOTICE(x)
+
+/* variables */
+#ifdef RCAR_DDR_FIXED_LSI_TYPE
+#ifndef RCAR_AUTO
+#define RCAR_AUTO 99U
+#define RZ_G2M 100U
+
+#define RCAR_CUT_10 0U
+#define RCAR_CUT_11 1U
+#define RCAR_CUT_20 10U
+#define RCAR_CUT_30 20U
+#endif /* RCAR_AUTO */
+#ifndef RCAR_LSI
+#define RCAR_LSI RCAR_AUTO
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO)
+static uint32_t prr_product;
+static uint32_t prr_cut;
+#else /* RCAR_LSI == RCAR_AUTO */
+#if (RCAR_LSI == RZ_G2M)
+static const uint32_t prr_product = PRR_PRODUCT_M3;
+#endif /* RCAR_LSI == RZ_G2M */
+
+#ifndef RCAR_LSI_CUT
+static uint32_t prr_cut;
+#else /* RCAR_LSI_CUT */
+#if (RCAR_LSI_CUT == RCAR_CUT_10)
+static const uint32_t prr_cut = PRR_PRODUCT_10;
+#elif(RCAR_LSI_CUT == RCAR_CUT_11)
+static const uint32_t prr_cut = PRR_PRODUCT_11;
+#elif(RCAR_LSI_CUT == RCAR_CUT_20)
+static const uint32_t prr_cut = PRR_PRODUCT_20;
+#elif(RCAR_LSI_CUT == RCAR_CUT_30)
+static const uint32_t prr_cut = PRR_PRODUCT_30;
+#endif /* RCAR_LSI_CUT == RCAR_CUT_10 */
+#endif /* RCAR_LSI_CUT */
+#endif /* RCAR_LSI == RCAR_AUTO */
+#else /* RCAR_DDR_FIXED_LSI_TYPE */
+static uint32_t prr_product;
+static uint32_t prr_cut;
+#endif /* RCAR_DDR_FIXED_LSI_TYPE */
+
+static const uint32_t *p_ddr_regdef_tbl;
+static uint32_t brd_clk;
+static uint32_t brd_clkdiv;
+static uint32_t brd_clkdiva;
+static uint32_t ddr_mbps;
+static uint32_t ddr_mbpsdiv;
+static uint32_t ddr_tccd;
+static uint32_t ddr_phycaslice;
+static const struct _boardcnf *board_cnf;
+static uint32_t ddr_phyvalid;
+static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
+static uint32_t ch_have_this_cs[CS_CNT] __aligned(64);
+static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT * 2U][9U];
+static uint32_t max_density;
+static uint32_t ddr0800_mul;
+static uint32_t ddr_mul;
+static uint32_t DDR_PHY_SLICE_REGSET_OFS;
+static uint32_t DDR_PHY_ADR_V_REGSET_OFS;
+static uint32_t DDR_PHY_ADR_I_REGSET_OFS;
+static uint32_t DDR_PHY_ADR_G_REGSET_OFS;
+static uint32_t DDR_PI_REGSET_OFS;
+static uint32_t DDR_PHY_SLICE_REGSET_SIZE;
+static uint32_t DDR_PHY_ADR_V_REGSET_SIZE;
+static uint32_t DDR_PHY_ADR_I_REGSET_SIZE;
+static uint32_t DDR_PHY_ADR_G_REGSET_SIZE;
+static uint32_t DDR_PI_REGSET_SIZE;
+static uint32_t DDR_PHY_SLICE_REGSET_NUM;
+static uint32_t DDR_PHY_ADR_V_REGSET_NUM;
+static uint32_t DDR_PHY_ADR_I_REGSET_NUM;
+static uint32_t DDR_PHY_ADR_G_REGSET_NUM;
+static uint32_t DDR_PI_REGSET_NUM;
+static uint32_t DDR_PHY_ADR_I_NUM;
+#define DDR_PHY_REGSET_MAX 128
+#define DDR_PI_REGSET_MAX 320
+static uint32_t _cnf_DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX];
+static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX];
+static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX];
+static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX];
+static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX];
+static uint32_t pll3_mode;
+static uint32_t loop_max;
+#ifdef DDR_BACKUPMODE
+uint32_t ddr_backup = DRAM_BOOT_STATUS_COLD;
+/* #define DDR_BACKUPMODE_HALF */ /* for Half channel(ch0,1 only) */
+#endif
+
+#ifdef DDR_QOS_INIT_SETTING /* only for non qos_init */
+#define OPERATING_FREQ (400U) /* Mhz */
+#define BASE_SUB_SLOT_NUM (0x6U)
+#define SUB_SLOT_CYCLE (0x7EU) /* 126 */
+#define QOSWT_WTSET0_CYCLE \
+ ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / \
+ OPERATING_FREQ) /* unit:ns */
+
+uint32_t get_refperiod(void)
+{
+ return QOSWT_WTSET0_CYCLE;
+}
+#else /* DDR_QOS_INIT_SETTING */
+extern uint32_t get_refperiod(void);
+#endif /* DDR_QOS_INIT_SETTING */
+
+#define _reg_PHY_RX_CAL_X_NUM 11U
+static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = {
+ _reg_PHY_RX_CAL_DQ0,
+ _reg_PHY_RX_CAL_DQ1,
+ _reg_PHY_RX_CAL_DQ2,
+ _reg_PHY_RX_CAL_DQ3,
+ _reg_PHY_RX_CAL_DQ4,
+ _reg_PHY_RX_CAL_DQ5,
+ _reg_PHY_RX_CAL_DQ6,
+ _reg_PHY_RX_CAL_DQ7,
+ _reg_PHY_RX_CAL_DM,
+ _reg_PHY_RX_CAL_DQS,
+ _reg_PHY_RX_CAL_FDBK
+};
+
+#define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10U
+static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY
+ [_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = {
+ _reg_PHY_CLK_WRDQ0_SLAVE_DELAY,
+ _reg_PHY_CLK_WRDQ1_SLAVE_DELAY,
+ _reg_PHY_CLK_WRDQ2_SLAVE_DELAY,
+ _reg_PHY_CLK_WRDQ3_SLAVE_DELAY,
+ _reg_PHY_CLK_WRDQ4_SLAVE_DELAY,
+ _reg_PHY_CLK_WRDQ5_SLAVE_DELAY,
+ _reg_PHY_CLK_WRDQ6_SLAVE_DELAY,
+ _reg_PHY_CLK_WRDQ7_SLAVE_DELAY,
+ _reg_PHY_CLK_WRDM_SLAVE_DELAY,
+ _reg_PHY_CLK_WRDQS_SLAVE_DELAY
+};
+
+#define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9U
+static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY
+ [_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = {
+ _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY
+};
+
+#define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9U
+static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY
+ [_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = {
+ _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY
+};
+
+#define _reg_PHY_PAD_TERM_X_NUM 8U
+static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = {
+ _reg_PHY_PAD_FDBK_TERM,
+ _reg_PHY_PAD_DATA_TERM,
+ _reg_PHY_PAD_DQS_TERM,
+ _reg_PHY_PAD_ADDR_TERM,
+ _reg_PHY_PAD_CLK_TERM,
+ _reg_PHY_PAD_CKE_TERM,
+ _reg_PHY_PAD_RST_TERM,
+ _reg_PHY_PAD_CS_TERM
+};
+
+#define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10U
+static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X
+ [_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = {
+ _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY,
+ _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY,
+ _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY,
+ _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY,
+ _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY,
+ _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY,
+
+ _reg_PHY_GRP_SLAVE_DELAY_0,
+ _reg_PHY_GRP_SLAVE_DELAY_1,
+ _reg_PHY_GRP_SLAVE_DELAY_2,
+ _reg_PHY_GRP_SLAVE_DELAY_3
+};
+
+/* Prototypes */
+static inline uint32_t vch_nxt(uint32_t pos);
+static void cpg_write_32(uint32_t a, uint32_t v);
+static void pll3_control(uint32_t high);
+static inline void dsb_sev(void);
+static void wait_dbcmd(void);
+static void send_dbcmd(uint32_t cmd);
+static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd);
+static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata);
+static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata);
+static inline uint32_t ddr_regdef(uint32_t _regdef);
+static inline uint32_t ddr_regdef_adr(uint32_t _regdef);
+static inline uint32_t ddr_regdef_lsb(uint32_t _regdef);
+static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
+ uint32_t val);
+static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef);
+static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val);
+static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val);
+static void ddr_setval_ach(uint32_t regdef, uint32_t val);
+static void ddr_setval_ach_as(uint32_t regdef, uint32_t val);
+static uint32_t ddr_getval(uint32_t ch, uint32_t regdef);
+static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p);
+static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p);
+static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size);
+static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val);
+static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef);
+static uint32_t ddrphy_regif_chk(void);
+static inline void ddrphy_regif_idle(void);
+static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps,
+ uint16_t cyc);
+static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv,
+ uint16_t *_js2);
+static int16_t _f_scale_adj(int16_t ps);
+static void ddrtbl_load(void);
+static void ddr_config_sub(void);
+static void ddr_config(void);
+static void dbsc_regset(void);
+static void dbsc_regset_post(void);
+static uint32_t dfi_init_start(void);
+static void change_lpddr4_en(uint32_t mode);
+static uint32_t set_term_code(void);
+static void ddr_register_set(void);
+static inline uint32_t wait_freqchgreq(uint32_t assert);
+static inline void set_freqchgack(uint32_t assert);
+static inline void set_dfifrequency(uint32_t freq);
+static uint32_t pll3_freq(uint32_t on);
+static void update_dly(void);
+static uint32_t pi_training_go(void);
+static uint32_t init_ddr(void);
+static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick);
+static uint32_t wdqdm_man1(void);
+static uint32_t wdqdm_man(void);
+static uint32_t rdqdm_man1(void);
+static uint32_t rdqdm_man(void);
+
+static int32_t _find_change(uint64_t val, uint32_t dir);
+static uint32_t _rx_offset_cal_updn(uint32_t code);
+static uint32_t rx_offset_cal(void);
+static uint32_t rx_offset_cal_hw(void);
+static void adjust_wpath_latency(void);
+
+struct ddrt_data {
+ int32_t init_temp; /* Initial Temperature (do) */
+ uint32_t init_cal[4U]; /* Initial io-code (4 is for G2H) */
+ uint32_t tcomp_cal[4U]; /* Temp. compensated io-code (4 is for G2H) */
+};
+
+static struct ddrt_data tcal;
+
+static void pvtcode_update(void);
+static void pvtcode_update2(void);
+static void ddr_padcal_tcompensate_getinit(uint32_t override);
+
+#ifndef DDR_FAST_INIT
+static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2U][9U];
+static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2U][9U];
+static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2U][9U];
+static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
+static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2U];
+static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
+static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
+
+static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9U];
+static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9U];
+static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9U];
+static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
+static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
+static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
+static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
+#endif/* DDR_FAST_INIT */
+
+/* macro for channel selection loop */
+static inline uint32_t vch_nxt(uint32_t pos)
+{
+ uint32_t posn;
+
+ for (posn = pos; posn < DRAM_CH_CNT; posn++) {
+ if ((ddr_phyvalid & (1U << posn)) != 0U) {
+ break;
+ }
+ }
+ return posn;
+}
+
+#define foreach_vch(ch) \
+for (ch = vch_nxt(0U); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1U))
+
+#define foreach_ech(ch) \
+for (ch = 0U; ch < DRAM_CH_CNT; ch++)
+
+/* Printing functions */
+#define MSG_LF(...)
+
+/* clock settings, reset control */
+static void cpg_write_32(uint32_t a, uint32_t v)
+{
+ mmio_write_32(CPG_CPGWPR, ~v);
+ mmio_write_32(a, v);
+}
+
+static void wait_for_pll3_status_bit_turned_on(void)
+{
+ uint32_t data_l;
+
+ do {
+ data_l = mmio_read_32(CPG_PLLECR);
+ } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
+ dsb_sev();
+}
+
+static void pll3_control(uint32_t high)
+{
+ uint32_t data_l, data_div, data_mul, tmp_div;
+
+ if (high != 0U) {
+ tmp_div = 3999U * brd_clkdiv * (brd_clkdiva + 1U) /
+ (brd_clk * ddr_mul) / 2U;
+ data_mul = ((ddr_mul * tmp_div) - 1U) << 24U;
+ pll3_mode = 1U;
+ loop_max = 2U;
+ } else {
+ tmp_div = 3999U * brd_clkdiv * (brd_clkdiva + 1U) /
+ (brd_clk * ddr0800_mul) / 2U;
+ data_mul = ((ddr0800_mul * tmp_div) - 1U) << 24U;
+ pll3_mode = 0U;
+ loop_max = 8U;
+ }
+
+ switch (tmp_div) {
+ case 1:
+ data_div = 0U;
+ break;
+ case 2:
+ case 3:
+ case 4:
+ data_div = tmp_div;
+ break;
+ default:
+ data_div = 6U;
+ data_mul = (data_mul * tmp_div) / 3U;
+ break;
+ }
+ data_mul = data_mul | (brd_clkdiva << 7);
+
+ /* PLL3 disable */
+ data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT;
+ cpg_write_32(CPG_PLLECR, data_l);
+ dsb_sev();
+
+ if (prr_product == PRR_PRODUCT_M3) {
+ /* PLL3 DIV resetting(Lowest value:3) */
+ data_l = 0x00030003U | (0xFF80FF80U & mmio_read_32(CPG_FRQCRD));
+ cpg_write_32(CPG_FRQCRD, data_l);
+ dsb_sev();
+
+ /* zb3 clk stop */
+ data_l = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR);
+ cpg_write_32(CPG_ZB3CKCR, data_l);
+ dsb_sev();
+
+ /* PLL3 enable */
+ data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
+ cpg_write_32(CPG_PLLECR, data_l);
+ dsb_sev();
+
+ wait_for_pll3_status_bit_turned_on();
+
+ /* PLL3 DIV resetting (Highest value:0) */
+ data_l = (0xFF80FF80U & mmio_read_32(CPG_FRQCRD));
+ cpg_write_32(CPG_FRQCRD, data_l);
+ dsb_sev();
+
+ /* DIV SET KICK */
+ data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+ cpg_write_32(CPG_FRQCRB, data_l);
+ dsb_sev();
+
+ /* PLL3 multiplier set */
+ cpg_write_32(CPG_PLL3CR, data_mul);
+ dsb_sev();
+
+ wait_for_pll3_status_bit_turned_on();
+
+ /* PLL3 DIV resetting(Target value) */
+ data_l = (data_div << 16U) | data_div |
+ (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80U);
+ cpg_write_32(CPG_FRQCRD, data_l);
+ dsb_sev();
+
+ /* DIV SET KICK */
+ data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+ cpg_write_32(CPG_FRQCRB, data_l);
+ dsb_sev();
+
+ wait_for_pll3_status_bit_turned_on();
+
+ /* zb3 clk start */
+ data_l = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR);
+ cpg_write_32(CPG_ZB3CKCR, data_l);
+ dsb_sev();
+ }
+}
+
+/* barrier */
+static inline void dsb_sev(void)
+{
+ __asm__ __volatile__("dsb sy");
+}
+
+/* DDR memory register access */
+static void wait_dbcmd(void)
+{
+ uint32_t data_l;
+ /* dummy read */
+ data_l = mmio_read_32(DBSC_DBCMD);
+ dsb_sev();
+ while (true) {
+ /* wait DBCMD 1=busy, 0=ready */
+ data_l = mmio_read_32(DBSC_DBWAIT);
+ dsb_sev();
+ if ((data_l & 0x00000001U) == 0x00U) {
+ break;
+ }
+ }
+}
+
+static void send_dbcmd(uint32_t cmd)
+{
+ /* dummy read */
+ wait_dbcmd();
+ mmio_write_32(DBSC_DBCMD, cmd);
+ dsb_sev();
+}
+
+static void dbwait_loop(uint32_t wait_loop)
+{
+ uint32_t i;
+
+ for (i = 0U; i < wait_loop; i++) {
+ wait_dbcmd();
+ }
+}
+
+/* DDRPHY register access (raw) */
+static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd)
+{
+ uint32_t val;
+ uint32_t loop;
+
+ val = 0U;
+ mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
+ dsb_sev();
+
+ while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
+ dsb_sev();
+ }
+ dsb_sev();
+
+ for (loop = 0U; loop < loop_max; loop++) {
+ val = mmio_read_32(DBSC_DBPDRGD(phyno));
+ dsb_sev();
+ }
+
+ return val;
+}
+
+static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata)
+{
+ uint32_t loop;
+
+ mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
+ dsb_sev();
+ for (loop = 0U; loop < loop_max; loop++) {
+ mmio_read_32(DBSC_DBPDRGA(phyno));
+ dsb_sev();
+ }
+ mmio_write_32(DBSC_DBPDRGD(phyno), regdata);
+ dsb_sev();
+
+ for (loop = 0U; loop < loop_max; loop++) {
+ mmio_read_32(DBSC_DBPDRGD(phyno));
+ dsb_sev();
+ }
+}
+
+static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata)
+{
+ uint32_t ch;
+ uint32_t loop;
+
+ foreach_vch(ch) {
+ mmio_write_32(DBSC_DBPDRGA(ch), regadd);
+ dsb_sev();
+ }
+
+ foreach_vch(ch) {
+ mmio_write_32(DBSC_DBPDRGD(ch), regdata);
+ dsb_sev();
+ }
+
+ for (loop = 0U; loop < loop_max; loop++) {
+ mmio_read_32(DBSC_DBPDRGD(0));
+ dsb_sev();
+ }
+}
+
+static inline void ddrphy_regif_idle(void)
+{
+ reg_ddrphy_read(0U, ddr_regdef_adr(_reg_PI_INT_STATUS));
+ dsb_sev();
+}
+
+/* DDRPHY register access (field modify) */
+static inline uint32_t ddr_regdef(uint32_t _regdef)
+{
+ return p_ddr_regdef_tbl[_regdef];
+}
+
+static inline uint32_t ddr_regdef_adr(uint32_t _regdef)
+{
+ return DDR_REGDEF_ADR(p_ddr_regdef_tbl[_regdef]);
+}
+
+static inline uint32_t ddr_regdef_lsb(uint32_t _regdef)
+{
+ return DDR_REGDEF_LSB(p_ddr_regdef_tbl[_regdef]);
+}
+
+static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
+ uint32_t val)
+{
+ uint32_t adr;
+ uint32_t lsb;
+ uint32_t len;
+ uint32_t msk;
+ uint32_t tmp;
+ uint32_t regdef;
+
+ regdef = ddr_regdef(_regdef);
+ adr = DDR_REGDEF_ADR(regdef) + 0x80U * slice;
+ len = DDR_REGDEF_LEN(regdef);
+ lsb = DDR_REGDEF_LSB(regdef);
+ if (len == 0x20U) {
+ msk = 0xffffffffU;
+ } else {
+ msk = ((1U << len) - 1U) << lsb;
+ }
+
+ tmp = reg_ddrphy_read(ch, adr);
+ tmp = (tmp & (~msk)) | ((val << lsb) & msk);
+ reg_ddrphy_write(ch, adr, tmp);
+}
+
+static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef)
+{
+ uint32_t adr;
+ uint32_t lsb;
+ uint32_t len;
+ uint32_t msk;
+ uint32_t tmp;
+ uint32_t regdef;
+
+ regdef = ddr_regdef(_regdef);
+ adr = DDR_REGDEF_ADR(regdef) + 0x80U * slice;
+ len = DDR_REGDEF_LEN(regdef);
+ lsb = DDR_REGDEF_LSB(regdef);
+ if (len == 0x20U) {
+ msk = 0xffffffffU;
+ } else {
+ msk = ((1U << len) - 1U);
+ }
+
+ tmp = reg_ddrphy_read(ch, adr);
+ tmp = (tmp >> lsb) & msk;
+
+ return tmp;
+}
+
+static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val)
+{
+ ddr_setval_s(ch, 0U, regdef, val);
+}
+
+static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val)
+{
+ uint32_t ch;
+
+ foreach_vch(ch) {
+ ddr_setval_s(ch, slice, regdef, val);
+ }
+}
+
+static void ddr_setval_ach(uint32_t regdef, uint32_t val)
+{
+ ddr_setval_ach_s(0U, regdef, val);
+}
+
+static void ddr_setval_ach_as(uint32_t regdef, uint32_t val)
+{
+ uint32_t slice;
+
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ ddr_setval_ach_s(slice, regdef, val);
+ }
+}
+
+static uint32_t ddr_getval(uint32_t ch, uint32_t regdef)
+{
+ return ddr_getval_s(ch, 0U, regdef);
+}
+
+static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p)
+{
+ uint32_t ch;
+
+ foreach_vch(ch) {
+ p[ch] = ddr_getval_s(ch, 0U, regdef);
+ }
+ return p[0U];
+}
+
+static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p)
+{
+ uint32_t ch, slice;
+ uint32_t *pp;
+
+ pp = p;
+ foreach_vch(ch) {
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ *pp++ = ddr_getval_s(ch, slice, regdef);
+ }
+ }
+ return p[0U];
+}
+
+/* handling functions for setting ddrphy value table */
+static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size)
+{
+ uint32_t i;
+
+ for (i = 0U; i < size; i++) {
+ to[i] = from[i];
+ }
+}
+
+static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val)
+{
+ uint32_t adr;
+ uint32_t lsb;
+ uint32_t len;
+ uint32_t msk;
+ uint32_t tmp;
+ uint32_t adrmsk;
+ uint32_t regdef;
+
+ regdef = ddr_regdef(_regdef);
+ adr = DDR_REGDEF_ADR(regdef);
+ len = DDR_REGDEF_LEN(regdef);
+ lsb = DDR_REGDEF_LSB(regdef);
+ if (len == 0x20U) {
+ msk = 0xffffffffU;
+ } else {
+ msk = ((1U << len) - 1U) << lsb;
+ }
+
+ if (adr < 0x400U) {
+ adrmsk = 0xffU;
+ } else {
+ adrmsk = 0x7fU;
+ }
+
+ tmp = tbl[adr & adrmsk];
+ tmp = (tmp & (~msk)) | ((val << lsb) & msk);
+ tbl[adr & adrmsk] = tmp;
+}
+
+static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef)
+{
+ uint32_t adr;
+ uint32_t lsb;
+ uint32_t len;
+ uint32_t msk;
+ uint32_t tmp;
+ uint32_t adrmsk;
+ uint32_t regdef;
+
+ regdef = ddr_regdef(_regdef);
+ adr = DDR_REGDEF_ADR(regdef);
+ len = DDR_REGDEF_LEN(regdef);
+ lsb = DDR_REGDEF_LSB(regdef);
+ if (len == 0x20U) {
+ msk = 0xffffffffU;
+ } else {
+ msk = ((1U << len) - 1U);
+ }
+
+ if (adr < 0x400U) {
+ adrmsk = 0xffU;
+ } else {
+ adrmsk = 0x7fU;
+ }
+
+ tmp = tbl[adr & adrmsk];
+ tmp = (tmp >> lsb) & msk;
+
+ return tmp;
+}
+
+/* DDRPHY register access handling */
+static uint32_t ddrphy_regif_chk(void)
+{
+ uint32_t tmp_ach[DRAM_CH_CNT];
+ uint32_t ch;
+ uint32_t err;
+ uint32_t PI_VERSION_CODE;
+
+ if (prr_product == PRR_PRODUCT_M3) {
+ PI_VERSION_CODE = 0x2041U; /* G2M */
+ }
+
+ ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach);
+ err = 0U;
+ foreach_vch(ch) {
+ if (tmp_ach[ch] != PI_VERSION_CODE) {
+ err = 1U;
+ }
+ }
+ return err;
+}
+
+/* functions and parameters for timing setting */
+struct _jedec_spec1 {
+ uint16_t fx3;
+ uint8_t rlwodbi;
+ uint8_t rlwdbi;
+ uint8_t WL;
+ uint8_t nwr;
+ uint8_t nrtp;
+ uint8_t odtlon;
+ uint8_t MR1;
+ uint8_t MR2;
+};
+
+#define JS1_USABLEC_SPEC_LO 2U
+#define JS1_USABLEC_SPEC_HI 5U
+#define JS1_FREQ_TBL_NUM 8
+#define JS1_MR1(f) (0x04U | ((f) << 4U))
+#define JS1_MR2(f) (0x00U | ((f) << 3U) | (f))
+static const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = {
+ /* 533.333Mbps */
+ { 800U, 6U, 6U, 4U, 6U, 8U, 0U, JS1_MR1(0U), JS1_MR2(0U) | 0x40U },
+ /* 1066.666Mbps */
+ { 1600U, 10U, 12U, 8U, 10U, 8U, 0U, JS1_MR1(1U), JS1_MR2(1U) | 0x40U },
+ /* 1600.000Mbps */
+ { 2400U, 14U, 16U, 12U, 16U, 8U, 6U, JS1_MR1(2U), JS1_MR2(2U) | 0x40U },
+ /* 2133.333Mbps */
+ { 3200U, 20U, 22U, 10U, 20U, 8U, 4U, JS1_MR1(3U), JS1_MR2(3U) },
+ /* 2666.666Mbps */
+ { 4000U, 24U, 28U, 12U, 24U, 10U, 4U, JS1_MR1(4U), JS1_MR2(4U) },
+ /* 3200.000Mbps */
+ { 4800U, 28U, 32U, 14U, 30U, 12U, 6U, JS1_MR1(5U), JS1_MR2(5U) },
+ /* 3733.333Mbps */
+ { 5600U, 32U, 36U, 16U, 34U, 14U, 6U, JS1_MR1(6U), JS1_MR2(6U) },
+ /* 4266.666Mbps */
+ { 6400U, 36U, 40U, 18U, 40U, 16U, 8U, JS1_MR1(7U), JS1_MR2(7U) }
+};
+
+struct _jedec_spec2 {
+ uint16_t ps;
+ uint16_t cyc;
+};
+
+#define js2_tsr 0
+#define js2_txp 1
+#define js2_trtp 2
+#define js2_trcd 3
+#define js2_trppb 4
+#define js2_trpab 5
+#define js2_tras 6
+#define js2_twr 7
+#define js2_twtr 8
+#define js2_trrd 9
+#define js2_tppd 10
+#define js2_tfaw 11
+#define js2_tdqsck 12
+#define js2_tckehcmd 13
+#define js2_tckelcmd 14
+#define js2_tckelpd 15
+#define js2_tmrr 16
+#define js2_tmrw 17
+#define js2_tmrd 18
+#define js2_tzqcalns 19
+#define js2_tzqlat 20
+#define js2_tiedly 21
+#define js2_tODTon_min 22
+#define JS2_TBLCNT 23
+
+#define js2_trcpb (JS2_TBLCNT)
+#define js2_trcab (JS2_TBLCNT + 1)
+#define js2_trfcab (JS2_TBLCNT + 2)
+#define JS2_CNT (JS2_TBLCNT + 3)
+
+#ifndef JS2_DERATE
+#define JS2_DERATE 0
+#endif
+static const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = {
+ {
+/* tSR */ { 15000, 3 },
+/* tXP */ { 7500, 3 },
+/* tRTP */ { 7500, 8 },
+/* tRCD */ { 18000, 4 },
+/* tRPpb */ { 18000, 3 },
+/* tRPab */ { 21000, 3 },
+/* tRAS */ { 42000, 3 },
+/* tWR */ { 18000, 4 },
+/* tWTR */ { 10000, 8 },
+/* tRRD */ { 10000, 4 },
+/* tPPD */ { 0, 0 },
+/* tFAW */ { 40000, 0 },
+/* tDQSCK */ { 3500, 0 },
+/* tCKEHCMD */ { 7500, 3 },
+/* tCKELCMD */ { 7500, 3 },
+/* tCKELPD */ { 7500, 3 },
+/* tMRR */ { 0, 8 },
+/* tMRW */ { 10000, 10 },
+/* tMRD */ { 14000, 10 },
+/* tZQCALns */ { 1000 * 10, 0 },
+/* tZQLAT */ { 30000, 10 },
+/* tIEdly */ { 12500, 0 },
+/* tODTon_min */{ 1500, 0 }
+ }, {
+/* tSR */ { 15000, 3 },
+/* tXP */ { 7500, 3 },
+/* tRTP */ { 7500, 8 },
+/* tRCD */ { 19875, 4 },
+/* tRPpb */ { 19875, 3 },
+/* tRPab */ { 22875, 3 },
+/* tRAS */ { 43875, 3 },
+/* tWR */ { 18000, 4 },
+/* tWTR */ { 10000, 8 },
+/* tRRD */ { 11875, 4 },
+/* tPPD */ { 0, 0 },
+/* tFAW */ { 40000, 0 },
+/* tDQSCK */ { 3600, 0 },
+/* tCKEHCMD */ { 7500, 3 },
+/* tCKELCMD */ { 7500, 3 },
+/* tCKELPD */ { 7500, 3 },
+/* tMRR */ { 0, 8 },
+/* tMRW */ { 10000, 10 },
+/* tMRD */ { 14000, 10 },
+/* tZQCALns */ { 1000 * 10, 0 },
+/* tZQLAT */ { 30000, 10 },
+/* tIEdly */ { 12500, 0 },
+/* tODTon_min */{ 1500, 0 }
+ }
+};
+
+static const uint16_t jedec_spec2_trfc_ab[7] = {
+ /* 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb(non), 32Gb(non) */
+ 130U, 180U, 180U, 280U, 280U, 560U, 560U
+};
+
+static uint32_t js1_ind;
+static uint16_t js2[JS2_CNT];
+static uint8_t RL;
+static uint8_t WL;
+
+static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps,
+ uint16_t cyc)
+{
+ uint16_t ret = cyc;
+ uint32_t tmp;
+ uint32_t div;
+
+ tmp = (((uint32_t)(ps) + 9U) / 10U) * _ddr_mbps;
+ div = tmp / (200000U * _ddr_mbpsdiv);
+ if (tmp != (div * 200000U * _ddr_mbpsdiv)) {
+ div = div + 1U;
+ }
+
+ if (div > cyc) {
+ ret = (uint16_t)div;
+ }
+
+ return ret;
+}
+
+static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv,
+ uint16_t *_js2)
+{
+ int i;
+
+ for (i = 0; i < JS2_TBLCNT; i++) {
+ _js2[i] = _f_scale(_ddr_mbps, _ddr_mbpsdiv,
+ jedec_spec2[JS2_DERATE][i].ps,
+ jedec_spec2[JS2_DERATE][i].cyc);
+ }
+
+ _js2[js2_trcpb] = _js2[js2_tras] + _js2[js2_trppb];
+ _js2[js2_trcab] = _js2[js2_tras] + _js2[js2_trpab];
+}
+
+/* scaler for DELAY value */
+static int16_t _f_scale_adj(int16_t ps)
+{
+ int32_t tmp;
+ /*
+ * tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000;
+ * = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125
+ * = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125
+ */
+ tmp = (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps /
+ (int32_t)ddr_mbpsdiv;
+ tmp = (int32_t)tmp / (int32_t)15625;
+
+ return (int16_t)tmp;
+}
+
+static const uint32_t reg_pi_mr1_data_fx_csx[2U][CSAB_CNT] = {
+ {
+ _reg_PI_MR1_DATA_F0_0,
+ _reg_PI_MR1_DATA_F0_1,
+ _reg_PI_MR1_DATA_F0_2,
+ _reg_PI_MR1_DATA_F0_3},
+ {
+ _reg_PI_MR1_DATA_F1_0,
+ _reg_PI_MR1_DATA_F1_1,
+ _reg_PI_MR1_DATA_F1_2,
+ _reg_PI_MR1_DATA_F1_3}
+};
+
+static const uint32_t reg_pi_mr2_data_fx_csx[2U][CSAB_CNT] = {
+ {
+ _reg_PI_MR2_DATA_F0_0,
+ _reg_PI_MR2_DATA_F0_1,
+ _reg_PI_MR2_DATA_F0_2,
+ _reg_PI_MR2_DATA_F0_3},
+ {
+ _reg_PI_MR2_DATA_F1_0,
+ _reg_PI_MR2_DATA_F1_1,
+ _reg_PI_MR2_DATA_F1_2,
+ _reg_PI_MR2_DATA_F1_3}
+};
+
+static const uint32_t reg_pi_mr3_data_fx_csx[2U][CSAB_CNT] = {
+ {
+ _reg_PI_MR3_DATA_F0_0,
+ _reg_PI_MR3_DATA_F0_1,
+ _reg_PI_MR3_DATA_F0_2,
+ _reg_PI_MR3_DATA_F0_3},
+ {
+ _reg_PI_MR3_DATA_F1_0,
+ _reg_PI_MR3_DATA_F1_1,
+ _reg_PI_MR3_DATA_F1_2,
+ _reg_PI_MR3_DATA_F1_3}
+};
+
+static const uint32_t reg_pi_mr11_data_fx_csx[2U][CSAB_CNT] = {
+ {
+ _reg_PI_MR11_DATA_F0_0,
+ _reg_PI_MR11_DATA_F0_1,
+ _reg_PI_MR11_DATA_F0_2,
+ _reg_PI_MR11_DATA_F0_3},
+ {
+ _reg_PI_MR11_DATA_F1_0,
+ _reg_PI_MR11_DATA_F1_1,
+ _reg_PI_MR11_DATA_F1_2,
+ _reg_PI_MR11_DATA_F1_3}
+};
+
+static const uint32_t reg_pi_mr12_data_fx_csx[2U][CSAB_CNT] = {
+ {
+ _reg_PI_MR12_DATA_F0_0,
+ _reg_PI_MR12_DATA_F0_1,
+ _reg_PI_MR12_DATA_F0_2,
+ _reg_PI_MR12_DATA_F0_3},
+ {
+ _reg_PI_MR12_DATA_F1_0,
+ _reg_PI_MR12_DATA_F1_1,
+ _reg_PI_MR12_DATA_F1_2,
+ _reg_PI_MR12_DATA_F1_3}
+};
+
+static const uint32_t reg_pi_mr14_data_fx_csx[2U][CSAB_CNT] = {
+ {
+ _reg_PI_MR14_DATA_F0_0,
+ _reg_PI_MR14_DATA_F0_1,
+ _reg_PI_MR14_DATA_F0_2,
+ _reg_PI_MR14_DATA_F0_3},
+ {
+ _reg_PI_MR14_DATA_F1_0,
+ _reg_PI_MR14_DATA_F1_1,
+ _reg_PI_MR14_DATA_F1_2,
+ _reg_PI_MR14_DATA_F1_3}
+};
+
+/*
+ * regif pll w/a ( REGIF G2M WA )
+ */
+static void regif_pll_wa(void)
+{
+ uint32_t ch;
+ uint32_t reg_ofs;
+
+ /* PLL setting for PHY : G2M */
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT),
+ (0x5064U <<
+ ddr_regdef_lsb(_reg_PHY_PLL_WAIT)));
+
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL),
+ (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_PLL_CTRL_TOP) << 16) |
+ ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_PLL_CTRL));
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA),
+ ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_PLL_CTRL_CA));
+
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL),
+ (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_LP4_BOOT_PLL_CTRL_CA) << 16) |
+ ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_LP4_BOOT_PLL_CTRL));
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_TOP_PLL_CTRL),
+ ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_LP4_BOOT_TOP_PLL_CTRL));
+
+ reg_ofs = ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS;
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS),
+ _cnf_DDR_PHY_ADR_G_REGSET[reg_ofs]);
+
+ /* protect register interface */
+ ddrphy_regif_idle();
+ pll3_control(0U);
+
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN),
+ (0x01U << ddr_regdef_lsb(_reg_PHY_DLL_RST_EN)));
+ ddrphy_regif_idle();
+
+ /*
+ * init start
+ * dbdficnt0:
+ * dfi_dram_clk_disable=1
+ * dfi_frequency = 0
+ * freq_ratio = 01 (2:1)
+ * init_start =0
+ */
+ foreach_vch(ch) {
+ mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10U);
+ }
+ dsb_sev();
+
+ /*
+ * dbdficnt0:
+ * dfi_dram_clk_disable=1
+ * dfi_frequency = 0
+ * freq_ratio = 01 (2:1)
+ * init_start =1
+ */
+ foreach_vch(ch) {
+ mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11U);
+ }
+ dsb_sev();
+
+ foreach_ech(ch) {
+ if ((board_cnf->phyvalid & BIT(ch)) != 0U) {
+ while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1fU) != 0x1fU) {
+ }
+ }
+ }
+ dsb_sev();
+}
+
+/* load table data into DDR registers */
+static void ddrtbl_load(void)
+{
+ uint32_t i;
+ uint32_t slice;
+ uint32_t csab;
+ uint32_t adr;
+ uint32_t data_l;
+ uint32_t tmp[3];
+ uint16_t dataS;
+
+ /*
+ * TIMING REGISTERS
+ * search jedec_spec1 index
+ */
+ for (i = JS1_USABLEC_SPEC_LO; i < (uint32_t)JS1_FREQ_TBL_NUM - 1U; i++) {
+ if ((js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U) != 0U) {
+ break;
+ }
+ }
+ if (i > JS1_USABLEC_SPEC_HI) {
+ js1_ind = JS1_USABLEC_SPEC_HI;
+ } else {
+ js1_ind = i;
+ }
+
+ if (board_cnf->dbi_en != 0U) {
+ RL = js1[js1_ind].rlwdbi;
+ } else {
+ RL = js1[js1_ind].rlwodbi;
+ }
+
+ WL = js1[js1_ind].WL;
+
+ /* calculate jedec_spec2 */
+ _f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2);
+
+ /* PREPARE TBL */
+ if (prr_product == PRR_PRODUCT_M3) {
+ /* G2M */
+ _tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
+ DDR_PHY_SLICE_REGSET_G2M, DDR_PHY_SLICE_REGSET_NUM_G2M);
+ _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET,
+ DDR_PHY_ADR_V_REGSET_G2M, DDR_PHY_ADR_V_REGSET_NUM_G2M);
+ _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET,
+ DDR_PHY_ADR_I_REGSET_G2M, DDR_PHY_ADR_I_REGSET_NUM_G2M);
+ _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET,
+ DDR_PHY_ADR_G_REGSET_G2M, DDR_PHY_ADR_G_REGSET_NUM_G2M);
+ _tblcopy(_cnf_DDR_PI_REGSET,
+ DDR_PI_REGSET_G2M, DDR_PI_REGSET_NUM_G2M);
+
+ DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_G2M;
+ DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_G2M;
+ DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_G2M;
+ DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_G2M;
+ DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_G2M;
+ DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_G2M;
+ DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_G2M;
+ DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_G2M;
+ DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_G2M;
+ DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_G2M;
+ DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_G2M;
+ DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_G2M;
+ DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_G2M;
+ DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_G2M;
+ DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_G2M;
+
+ DDR_PHY_ADR_I_NUM = 2U;
+ }
+
+ /* on fly gate adjust */
+ if ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10)) {
+ ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_ON_FLY_GATE_ADJUST_EN, 0x00);
+ }
+
+ /* Adjust PI parameters */
+#ifdef _def_LPDDR4_ODT
+ for (i = 0U; i < 2U; i++) {
+ for (csab = 0U; csab < CSAB_CNT; csab++) {
+ ddrtbl_setval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr11_data_fx_csx[i][csab],
+ _def_LPDDR4_ODT);
+ }
+ }
+#endif /* _def_LPDDR4_ODT */
+
+#ifdef _def_LPDDR4_VREFCA
+ for (i = 0U; i < 2U; i++) {
+ for (csab = 0U; csab < CSAB_CNT; csab++) {
+ ddrtbl_setval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr12_data_fx_csx[i][csab],
+ _def_LPDDR4_VREFCA);
+ }
+ }
+#endif /* _def_LPDDR4_VREFCA */
+
+ if ((js2[js2_tiedly]) >= 0x0eU) {
+ dataS = 0x0eU;
+ } else {
+ dataS = js2[js2_tiedly];
+ }
+
+ ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS);
+ ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY,
+ (dataS - 2U));
+ ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS);
+
+ if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD) != 0U) {
+ data_l = WL - 1U;
+ } else {
+ data_l = WL;
+ }
+ ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, data_l - 2U);
+ ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, data_l);
+
+ if (board_cnf->dbi_en != 0U) {
+ ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE,
+ 0x01U);
+ ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_WDQLVL_DATADM_MASK, 0x000U);
+ } else {
+ ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE,
+ 0x00U);
+ ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_WDQLVL_DATADM_MASK, 0x100U);
+ }
+
+ tmp[0] = js1[js1_ind].MR1;
+ tmp[1] = js1[js1_ind].MR2;
+ data_l = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0);
+ if (board_cnf->dbi_en != 0U) {
+ tmp[2] = data_l | 0xc0U;
+ } else {
+ tmp[2] = data_l & (~0xc0U);
+ }
+
+ for (i = 0U; i < 2U; i++) {
+ for (csab = 0U; csab < CSAB_CNT; csab++) {
+ ddrtbl_setval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr1_data_fx_csx[i][csab], tmp[0]);
+ ddrtbl_setval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr2_data_fx_csx[i][csab], tmp[1]);
+ ddrtbl_setval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr3_data_fx_csx[i][csab], tmp[2]);
+ }
+ }
+
+ /* DDRPHY INT START */
+ regif_pll_wa();
+ dbwait_loop(5U);
+
+ /* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
+ BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
+ ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01U);
+
+ /* SET DATA SLICE TABLE */
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ adr =
+ DDR_PHY_SLICE_REGSET_OFS +
+ DDR_PHY_SLICE_REGSET_SIZE * slice;
+ for (i = 0U; i < DDR_PHY_SLICE_REGSET_NUM; i++) {
+ reg_ddrphy_write_a(adr + i,
+ _cnf_DDR_PHY_SLICE_REGSET[i]);
+ }
+ }
+
+ /* SET ADR SLICE TABLE */
+ adr = DDR_PHY_ADR_V_REGSET_OFS;
+ for (i = 0U; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
+ reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]);
+ }
+
+ if ((prr_product == PRR_PRODUCT_M3) &&
+ ((0x00ffffffU & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40U))
+ != 0x00U)) {
+ adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE;
+ for (i = 0U; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
+ reg_ddrphy_write_a(adr + i,
+ _cnf_DDR_PHY_ADR_V_REGSET[i]);
+ }
+ ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_ADR_DISABLE, 0x02);
+ DDR_PHY_ADR_I_NUM -= 1U;
+ ddr_phycaslice = 1U;
+
+#ifndef _def_LPDDR4_ODT
+ for (i = 0U; i < 2U; i++) {
+ for (csab = 0U; csab < CSAB_CNT; csab++) {
+ ddrtbl_setval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr11_data_fx_csx[i][csab],
+ 0x66);
+ }
+ }
+#endif/* _def_LPDDR4_ODT */
+ } else {
+ ddr_phycaslice = 0U;
+ }
+
+ if (DDR_PHY_ADR_I_NUM > 0U) {
+ for (slice = 0U; slice < DDR_PHY_ADR_I_NUM; slice++) {
+ adr =
+ DDR_PHY_ADR_I_REGSET_OFS +
+ DDR_PHY_ADR_I_REGSET_SIZE * slice;
+ for (i = 0U; i < DDR_PHY_ADR_I_REGSET_NUM; i++) {
+ reg_ddrphy_write_a(adr + i,
+ _cnf_DDR_PHY_ADR_I_REGSET
+ [i]);
+ }
+ }
+ }
+
+ /* SET ADRCTRL SLICE TABLE */
+ adr = DDR_PHY_ADR_G_REGSET_OFS;
+ for (i = 0U; i < DDR_PHY_ADR_G_REGSET_NUM; i++) {
+ reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]);
+ }
+
+ /* SET PI REGISTERS */
+ adr = DDR_PI_REGSET_OFS;
+ for (i = 0U; i < DDR_PI_REGSET_NUM; i++) {
+ reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]);
+ }
+}
+
+/* CONFIGURE DDR REGISTERS */
+static void ddr_config_sub(void)
+{
+ const uint32_t _par_CALVL_DEVICE_MAP = 1U;
+ uint8_t high_byte[SLICE_CNT];
+ uint32_t ch, slice;
+ uint32_t data_l;
+ uint32_t tmp;
+ uint32_t i;
+
+ foreach_vch(ch) {
+ /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ high_byte[slice] =
+ (board_cnf->ch[ch].dqs_swap >> (4U * slice)) % 2U;
+ ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0,
+ board_cnf->ch[ch].dq_swap[slice]);
+ ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1,
+ board_cnf->ch[ch].dm_swap[slice]);
+ if (high_byte[slice] != 0U) {
+ /* HIGHER 16 BYTE */
+ ddr_setval_s(ch, slice,
+ _reg_PHY_CALVL_VREF_DRIVING_SLICE,
+ 0x00);
+ } else {
+ /* LOWER 16 BYTE */
+ ddr_setval_s(ch, slice,
+ _reg_PHY_CALVL_VREF_DRIVING_SLICE,
+ 0x01);
+ }
+ }
+
+ /* BOARD SETTINGS (CA,ADDR_SEL) */
+ data_l = (0x00ffffffU & (uint32_t)(board_cnf->ch[ch].ca_swap)) |
+ 0x00888888U;
+
+ /* --- ADR_CALVL_SWIZZLE --- */
+ if (prr_product == PRR_PRODUCT_M3) {
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l);
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0,
+ 0x00000000);
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l);
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1,
+ 0x00000000);
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP,
+ _par_CALVL_DEVICE_MAP);
+ } else {
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l);
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000);
+ ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP,
+ _par_CALVL_DEVICE_MAP);
+ }
+
+ /* --- ADR_ADDR_SEL --- */
+ data_l = 0U;
+ tmp = board_cnf->ch[ch].ca_swap;
+ for (i = 0U; i < 6U; i++) {
+ data_l |= ((tmp & 0x0fU) << (i * 5U));
+ tmp = tmp >> 4;
+ }
+ ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, data_l);
+ if (ddr_phycaslice == 1U) {
+ /* ----------- adr slice2 swap ----------- */
+ tmp = (uint32_t)((board_cnf->ch[ch].ca_swap) >> 40);
+ data_l = (tmp & 0x00ffffffU) | 0x00888888U;
+
+ /* --- ADR_CALVL_SWIZZLE --- */
+ if (prr_product == PRR_PRODUCT_M3) {
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_SWIZZLE0_0,
+ data_l);
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_SWIZZLE1_0,
+ 0x00000000);
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_SWIZZLE0_1,
+ data_l);
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_SWIZZLE1_1,
+ 0x00000000);
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_DEVICE_MAP,
+ _par_CALVL_DEVICE_MAP);
+ } else {
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_SWIZZLE0,
+ data_l);
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_SWIZZLE1,
+ 0x00000000);
+ ddr_setval_s(ch, 2,
+ _reg_PHY_CALVL_DEVICE_MAP,
+ _par_CALVL_DEVICE_MAP);
+ }
+
+ /* --- ADR_ADDR_SEL --- */
+ data_l = 0U;
+ for (i = 0U; i < 6U; i++) {
+ data_l |= ((tmp & 0x0fU) << (i * 5U));
+ tmp = tmp >> 4U;
+ }
+
+ ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l);
+ }
+
+ /* BOARD SETTINGS (BYTE_ORDER_SEL) */
+ if (prr_product == PRR_PRODUCT_M3) {
+ /* --- DATA_BYTE_SWAP --- */
+ data_l = 0U;
+ tmp = board_cnf->ch[ch].dqs_swap;
+ for (i = 0U; i < 4U; i++) {
+ data_l |= ((tmp & 0x03U) << (i * 2U));
+ tmp = tmp >> 4U;
+ }
+ } else {
+ /* --- DATA_BYTE_SWAP --- */
+ data_l = board_cnf->ch[ch].dqs_swap;
+ ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01);
+ ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0,
+ (data_l) & 0x0fU);
+ ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1,
+ (data_l >> 4U * 1U) & 0x0fU);
+ ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2,
+ (data_l >> 4U * 2U) & 0x0fU);
+ ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3,
+ (data_l >> 4U * 3U) & 0x0fU);
+
+ ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00U);
+ }
+ ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, data_l);
+ }
+}
+
+static void ddr_config(void)
+{
+ uint32_t num_cacs_dly = _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM;
+ uint32_t reg_ofs, dly;
+ uint32_t ch, slice;
+ uint32_t data_l;
+ uint32_t tmp;
+ uint32_t i;
+ int8_t _adj;
+ int16_t adj;
+ uint32_t dq;
+ union {
+ uint32_t ui32[4];
+ uint8_t ui8[16];
+ } patt;
+ uint16_t patm;
+
+ /* configure ddrphy registers */
+ ddr_config_sub();
+
+ /* WDQ_USER_PATT */
+ foreach_vch(ch) {
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ patm = 0U;
+ for (i = 0U; i < 16U; i++) {
+ tmp = board_cnf->ch[ch].wdqlvl_patt[i];
+ patt.ui8[i] = tmp & 0xffU;
+ if ((tmp & 0x100U) != 0U) {
+ patm |= (1U << (uint16_t)i);
+ }
+ }
+ ddr_setval_s(ch, slice, _reg_PHY_USER_PATT0,
+ patt.ui32[0]);
+ ddr_setval_s(ch, slice, _reg_PHY_USER_PATT1,
+ patt.ui32[1]);
+ ddr_setval_s(ch, slice, _reg_PHY_USER_PATT2,
+ patt.ui32[2]);
+ ddr_setval_s(ch, slice, _reg_PHY_USER_PATT3,
+ patt.ui32[3]);
+ ddr_setval_s(ch, slice, _reg_PHY_USER_PATT4, patm);
+ }
+ }
+
+ /* CACS DLY */
+ data_l = board_cnf->cacs_dly + (uint32_t)_f_scale_adj(board_cnf->cacs_dly_adj);
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 0x00U);
+ foreach_vch(ch) {
+ for (i = 0U; i < num_cacs_dly - 4U; i++) {
+ adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
+ dly = _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i];
+ ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, dly,
+ data_l + (uint32_t)adj);
+ reg_ofs = ddr_regdef_adr(dly) - DDR_PHY_ADR_V_REGSET_OFS;
+ reg_ddrphy_write(ch, ddr_regdef_adr(dly),
+ _cnf_DDR_PHY_ADR_V_REGSET[reg_ofs]);
+ }
+
+ for (i = num_cacs_dly - 4U; i < num_cacs_dly; i++) {
+ adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
+ dly = _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i];
+ ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, dly,
+ data_l + (uint32_t)adj);
+ reg_ofs = ddr_regdef_adr(dly) - DDR_PHY_ADR_G_REGSET_OFS;
+ reg_ddrphy_write(ch, ddr_regdef_adr(dly),
+ _cnf_DDR_PHY_ADR_G_REGSET[reg_ofs]);
+ }
+
+ if (ddr_phycaslice == 1U) {
+ for (i = 0U; i < 6U; i++) {
+ adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i + num_cacs_dly]);
+ dly = _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i];
+ ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, dly,
+ data_l + (uint32_t)adj);
+ reg_ofs = ddr_regdef_adr(dly) - DDR_PHY_ADR_V_REGSET_OFS;
+ reg_ddrphy_write(ch, ddr_regdef_adr(dly) + 0x0100U,
+ _cnf_DDR_PHY_ADR_V_REGSET[reg_ofs]);
+ }
+ }
+ }
+
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
+ BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
+
+ /* WDQDM DLY */
+ data_l = board_cnf->dqdm_dly_w;
+ foreach_vch(ch) {
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ for (i = 0U; i <= 8U; i++) {
+ dq = slice * 8U + (uint32_t)i;
+ if (i == 8U) {
+ _adj = board_cnf->ch[ch].dm_adj_w[slice];
+ } else {
+ _adj = board_cnf->ch[ch].dq_adj_w[dq];
+ }
+ adj = _f_scale_adj(_adj);
+ ddr_setval_s(ch, slice,
+ _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
+ data_l + (uint32_t)adj);
+ }
+ }
+ }
+
+ /* RDQDM DLY */
+ data_l = board_cnf->dqdm_dly_r;
+ foreach_vch(ch) {
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ for (i = 0U; i <= 8U; i++) {
+ dq = slice * 8U + (uint32_t)i;
+ if (i == 8U) {
+ _adj = board_cnf->ch[ch].dm_adj_r[slice];
+ } else {
+ _adj = board_cnf->ch[ch].dq_adj_r[dq];
+ }
+ adj = _f_scale_adj(_adj);
+ dly = _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i];
+ ddr_setval_s(ch, slice, dly, data_l + (uint32_t)adj);
+ dly = _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i];
+ ddr_setval_s(ch, slice, dly, data_l + (uint32_t)adj);
+ }
+ }
+ }
+}
+
+/* DBSC register setting functions */
+static void dbsc_regset_pre(void)
+{
+ uint32_t ch, csab;
+ uint32_t data_l;
+
+ /* PRIMARY SETTINGS */
+ /* LPDDR4, BL=16, DFI interface */
+ mmio_write_32(DBSC_DBKIND, 0x0000000aU);
+ mmio_write_32(DBSC_DBBL, 0x00000002U);
+ mmio_write_32(DBSC_DBPHYCONF0, 0x00000001U);
+
+ /* FREQRATIO=2 */
+ mmio_write_32(DBSC_DBSYSCONF1, 0x00000002U);
+
+ /*
+ * DRAM SIZE REGISTER:
+ * set all ranks as density=0(4Gb) for PHY initialization
+ */
+ foreach_vch(ch) {
+ for (csab = 0U; csab < 4U; csab++) {
+ mmio_write_32(DBSC_DBMEMCONF(ch, csab),
+ DBMEMCONF_REGD(0U));
+ }
+ }
+
+ if (prr_product == PRR_PRODUCT_M3) {
+ data_l = 0xe4e4e4e4U;
+ foreach_ech(ch) {
+ if ((ddr_phyvalid & (1U << ch)) != 0U) {
+ data_l = (data_l & (~(0x000000FFU << (ch * 8U))))
+ | (((board_cnf->ch[ch].dqs_swap & 0x0003U)
+ | ((board_cnf->ch[ch].dqs_swap & 0x0030U) >> 2U)
+ | ((board_cnf->ch[ch].dqs_swap & 0x0300U) >> 4U)
+ | ((board_cnf->ch[ch].dqs_swap & 0x3000U) >> 6U))
+ << (ch * 8U));
+ }
+ }
+ mmio_write_32(DBSC_DBBSWAP, data_l);
+ }
+}
+
+static void dbsc_regset(void)
+{
+ int32_t i;
+ uint32_t ch;
+ uint32_t data_l;
+ uint32_t data_l2;
+ uint32_t wdql;
+ uint32_t dqenltncy;
+ uint32_t dql;
+ uint32_t dqienltncy;
+ uint32_t wrcslat;
+ uint32_t wrcsgap;
+ uint32_t rdcslat;
+ uint32_t rdcsgap;
+ uint32_t scfctst0_act_act;
+ uint32_t scfctst0_rda_act;
+ uint32_t scfctst0_wra_act;
+ uint32_t scfctst0_pre_act;
+ uint32_t scfctst1_rd_wr;
+ uint32_t scfctst1_wr_rd;
+ uint32_t scfctst1_act_rd_wr;
+ uint32_t scfctst1_asyncofs;
+ uint32_t dbschhrw1_sctrfcab;
+
+ /* RFC */
+ js2[js2_trfcab] =
+ _f_scale(ddr_mbps, ddr_mbpsdiv,
+ jedec_spec2_trfc_ab[max_density] * 1000U, 0U);
+ /* DBTR0.CL : RL */
+ mmio_write_32(DBSC_DBTR(0), RL);
+
+ /* DBTR1.CWL : WL */
+ mmio_write_32(DBSC_DBTR(1), WL);
+
+ /* DBTR2.AL : 0 */
+ mmio_write_32(DBSC_DBTR(2), 0U);
+
+ /* DBTR3.TRCD: tRCD */
+ mmio_write_32(DBSC_DBTR(3), js2[js2_trcd]);
+
+ /* DBTR4.TRPA,TRP: tRPab,tRPpb */
+ mmio_write_32(DBSC_DBTR(4), (js2[js2_trpab] << 16) | js2[js2_trppb]);
+
+ /* DBTR5.TRC : use tRCpb */
+ mmio_write_32(DBSC_DBTR(5), js2[js2_trcpb]);
+
+ /* DBTR6.TRAS : tRAS */
+ mmio_write_32(DBSC_DBTR(6), js2[js2_tras]);
+
+ /* DBTR7.TRRD : tRRD */
+ mmio_write_32(DBSC_DBTR(7), (js2[js2_trrd] << 16) | js2[js2_trrd]);
+
+ /* DBTR8.TFAW : tFAW */
+ mmio_write_32(DBSC_DBTR(8), js2[js2_tfaw]);
+
+ /* DBTR9.TRDPR : tRTP */
+ mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]);
+
+ /* DBTR10.TWR : nWR */
+ mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr);
+
+ /*
+ * DBTR11.TRDWR : RL + BL / 2 + Rounddown(tRPST) + PHY_ODTLoff -
+ * odtlon + tDQSCK - tODTon,min +
+ * PCB delay (out+in) + tPHY_ODToff
+ */
+ mmio_write_32(DBSC_DBTR(11),
+ RL + (16U / 2U) + 1U + 2U - js1[js1_ind].odtlon +
+ js2[js2_tdqsck] - js2[js2_tODTon_min] +
+ _f_scale(ddr_mbps, ddr_mbpsdiv, 1300, 0));
+
+ /* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */
+ data_l = WL + 1U + (16U / 2U) + js2[js2_twtr];
+ mmio_write_32(DBSC_DBTR(12), (data_l << 16) | data_l);
+
+ /* DBTR13.TRFCAB : tRFCab */
+ mmio_write_32(DBSC_DBTR(13), js2[js2_trfcab]);
+
+ /* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */
+ mmio_write_32(DBSC_DBTR(14),
+ (js2[js2_tckehcmd] << 16) | (js2[js2_tckehcmd]));
+
+ /* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */
+ mmio_write_32(DBSC_DBTR(15), (js2[js2_tsr] << 16) | (js2[js2_tckelpd]));
+
+ /* DBTR16 */
+ /* WDQL : tphy_wrlat + tphy_wrdata */
+ wdql = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1);
+ /* DQENLTNCY : tphy_wrlat = WL-2 : PHY_WRITE_PATH_LAT_ADD == 0
+ * tphy_wrlat = WL-3 : PHY_WRITE_PATH_LAT_ADD != 0
+ */
+ dqenltncy = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1);
+ /* DQL : tphy_rdlat + trdata_en */
+ /* it is not important for dbsc */
+ dql = RL + 16U;
+ /* DQIENLTNCY : trdata_en */
+ dqienltncy = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1) - 1U;
+ mmio_write_32(DBSC_DBTR(16),
+ (dqienltncy << 24) | (dql << 16) | (dqenltncy << 8) | wdql);
+
+ /* DBTR24 */
+ /* WRCSLAT = WRLAT -5 */
+ wrcslat = wdql - 5U;
+ /* WRCSGAP = 5 */
+ wrcsgap = 5U;
+ /* RDCSLAT = RDLAT_ADJ +2 */
+ rdcslat = dqienltncy;
+ if (prr_product != PRR_PRODUCT_M3) {
+ rdcslat += 2U;
+ }
+ /* RDCSGAP = 6 */
+ rdcsgap = 6U;
+ if (prr_product == PRR_PRODUCT_M3) {
+ rdcsgap = 4U;
+ }
+ mmio_write_32(DBSC_DBTR(24),
+ (rdcsgap << 24) | (rdcslat << 16) | (wrcsgap << 8) | wrcslat);
+
+ /* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0) */
+ mmio_write_32(DBSC_DBTR(17),
+ (js2[js2_tmrr] << 24) | (js2[js2_tmrd] << 16));
+
+ /* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */
+ mmio_write_32(DBSC_DBTR(18), 0);
+
+ /* DBTR19.TZQCL, TZQCS : do not use in LPDDR4 */
+ mmio_write_32(DBSC_DBTR(19), 0);
+
+ /* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */
+ data_l = js2[js2_trfcab] + js2[js2_tckehcmd];
+ mmio_write_32(DBSC_DBTR(20), (data_l << 16) | data_l);
+
+ /* DBTR21.TCCD */
+ /* DBTR23.TCCD */
+ if (ddr_tccd == 8U) {
+ data_l = 8U;
+ mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
+ mmio_write_32(DBSC_DBTR(23), 0x00000002);
+ } else if (ddr_tccd <= 11U) {
+ data_l = 11U;
+ mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
+ mmio_write_32(DBSC_DBTR(23), 0x00000000);
+ } else {
+ data_l = ddr_tccd;
+ mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
+ mmio_write_32(DBSC_DBTR(23), 0x00000000);
+ }
+
+ /* DBTR22.ZQLAT : */
+ data_l = js2[js2_tzqcalns] * 100U; /* 1000 * 1000 ps */
+ data_l = (data_l << 16U) | (js2[js2_tzqlat] + 24U + 20U);
+ mmio_write_32(DBSC_DBTR(22), data_l);
+
+ /* DBTR25 : do not use in LPDDR4 */
+ mmio_write_32(DBSC_DBTR(25), 0U);
+
+ /*
+ * DBRNK :
+ * DBSC_DBRNK2 rkrr
+ * DBSC_DBRNK3 rkrw
+ * DBSC_DBRNK4 rkwr
+ * DBSC_DBRNK5 rkww
+ */
+#define _par_DBRNK_VAL (0x7007U)
+
+ for (i = 0; i < 4; i++) {
+ data_l = (_par_DBRNK_VAL >> ((uint32_t)i * 4U)) & 0x0fU;
+ data_l2 = 0U;
+ foreach_vch(ch) {
+ data_l2 = data_l2 | (data_l << (4U * ch));
+ }
+ mmio_write_32(DBSC_DBRNK(2 + i), data_l2);
+ }
+ mmio_write_32(DBSC_DBADJ0, 0x00000000U);
+
+ /* timing registers for scheduler */
+ /* SCFCTST0 */
+ /* SCFCTST0 ACT-ACT */
+ scfctst0_act_act = js2[js2_trcpb] * 800UL * ddr_mbpsdiv / ddr_mbps;
+ /* SCFCTST0 RDA-ACT */
+ scfctst0_rda_act = ((16U / 2U) + js2[js2_trtp] - 8U +
+ js2[js2_trppb]) * 800UL * ddr_mbpsdiv / ddr_mbps;
+ /* SCFCTST0 WRA-ACT */
+ scfctst0_wra_act = (WL + 1U + (16U / 2U) +
+ js1[js1_ind].nwr) * 800UL * ddr_mbpsdiv / ddr_mbps;
+ /* SCFCTST0 PRE-ACT */
+ scfctst0_pre_act = js2[js2_trppb];
+ mmio_write_32(DBSC_SCFCTST0,
+ (scfctst0_act_act << 24) | (scfctst0_rda_act << 16) |
+ (scfctst0_wra_act << 8) | scfctst0_pre_act);
+
+ /* SCFCTST1 */
+ /* SCFCTST1 RD-WR */
+ scfctst1_rd_wr = (mmio_read_32(DBSC_DBTR(11)) & 0xffU) * 800UL * ddr_mbpsdiv /
+ ddr_mbps;
+ /* SCFCTST1 WR-RD */
+ scfctst1_wr_rd = (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800UL * ddr_mbpsdiv /
+ ddr_mbps;
+ /* SCFCTST1 ACT-RD/WR */
+ scfctst1_act_rd_wr = js2[js2_trcd] * 800UL * ddr_mbpsdiv / ddr_mbps;
+ /* SCFCTST1 ASYNCOFS */
+ scfctst1_asyncofs = 12U;
+ mmio_write_32(DBSC_SCFCTST1,
+ (scfctst1_rd_wr << 24) | (scfctst1_wr_rd << 16) |
+ (scfctst1_act_rd_wr << 8) | scfctst1_asyncofs);
+
+ /* DBSCHRW1 */
+ /* DBSCHRW1 SCTRFCAB */
+ dbschhrw1_sctrfcab = js2[js2_trfcab] * 800UL * ddr_mbpsdiv / ddr_mbps;
+ data_l = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000U) >> 16) +
+ (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFFU) +
+ (0x28U * 2U)) * 400U * 2U * ddr_mbpsdiv / ddr_mbps + 7U;
+ if (dbschhrw1_sctrfcab < data_l) {
+ dbschhrw1_sctrfcab = data_l;
+ }
+
+ if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) {
+ mmio_write_32(DBSC_DBSCHRW1, dbschhrw1_sctrfcab +
+ ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFFU) *
+ 400U * 2U * ddr_mbpsdiv + (ddr_mbps - 1U)) / ddr_mbps - 3U);
+ } else {
+ mmio_write_32(DBSC_DBSCHRW1, dbschhrw1_sctrfcab +
+ ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFFU) *
+ 400U * 2U * ddr_mbpsdiv + (ddr_mbps - 1U)) / ddr_mbps);
+ }
+
+ /* QOS and CAM */
+#ifdef DDR_QOS_INIT_SETTING /* only for non qos_init */
+ /* wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) */
+ mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218U);
+ /* 0(fillunit),8(dirtymax),4(dirtymin) */
+ mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4U);
+ /* stop_tolerance */
+ mmio_write_32(DBSC_DBSCHRW0, 0x22421111U);
+ /* rd-wr/wr-rd toggle priority */
+ mmio_write_32(DBSC_SCFCTST2, 0x012F1123U);
+ mmio_write_32(DBSC_DBSCHSZ0, 0x00000001U);
+ mmio_write_32(DBSC_DBSCHCNT0, 0x000F0037U);
+
+ /* QoS Settings */
+ mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
+ mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
+ mmio_write_32(DBSC_DBSCHQOS02, 0x00000000U);
+ mmio_write_32(DBSC_DBSCHQOS03, 0x00000000U);
+ mmio_write_32(DBSC_DBSCHQOS40, 0x00000300U);
+ mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
+ mmio_write_32(DBSC_DBSCHQOS42, 0x00000200U);
+ mmio_write_32(DBSC_DBSCHQOS43, 0x00000100U);
+ mmio_write_32(DBSC_DBSCHQOS90, 0x00000100U);
+ mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
+ mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
+ mmio_write_32(DBSC_DBSCHQOS93, 0x00000040U);
+ mmio_write_32(DBSC_DBSCHQOS120, 0x00000040U);
+ mmio_write_32(DBSC_DBSCHQOS121, 0x00000030U);
+ mmio_write_32(DBSC_DBSCHQOS122, 0x00000020U);
+ mmio_write_32(DBSC_DBSCHQOS123, 0x00000010U);
+ mmio_write_32(DBSC_DBSCHQOS130, 0x00000100U);
+ mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
+ mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
+ mmio_write_32(DBSC_DBSCHQOS133, 0x00000040U);
+ mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
+ mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
+ mmio_write_32(DBSC_DBSCHQOS142, 0x00000080U);
+ mmio_write_32(DBSC_DBSCHQOS143, 0x00000040U);
+ mmio_write_32(DBSC_DBSCHQOS150, 0x00000040U);
+ mmio_write_32(DBSC_DBSCHQOS151, 0x00000030U);
+ mmio_write_32(DBSC_DBSCHQOS152, 0x00000020U);
+ mmio_write_32(DBSC_DBSCHQOS153, 0x00000010U);
+
+ mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* DDR_QOS_INIT_SETTING */
+
+ /* resrdis */
+ mmio_write_32(DBSC_DBBCAMDIS, 0x00000001U);
+}
+
+static void dbsc_regset_post(void)
+{
+ uint32_t slice, rdlat_max, rdlat_min;
+ uint32_t ch, cs;
+ uint32_t data_l;
+ uint32_t srx;
+
+ rdlat_max = 0U;
+ rdlat_min = 0xffffU;
+ foreach_vch(ch) {
+ for (cs = 0U; cs < CS_CNT; cs++) {
+ if ((ch_have_this_cs[cs] & (1U << ch)) != 0U) {
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ ddr_setval_s(ch, slice,
+ _reg_PHY_PER_CS_TRAINING_INDEX,
+ cs);
+ data_l = ddr_getval_s(ch, slice,
+ _reg_PHY_RDDQS_LATENCY_ADJUST);
+ if (data_l > rdlat_max) {
+ rdlat_max = data_l;
+ }
+ if (data_l < rdlat_min) {
+ rdlat_min = data_l;
+ }
+ }
+ }
+ }
+ }
+
+ mmio_write_32(DBSC_DBTR(24),
+ ((rdlat_max + 2U) << 24) +
+ ((rdlat_max + 2U) << 16) +
+ mmio_read_32(DBSC_DBTR(24)));
+
+ /* set ddr density information */
+ foreach_ech(ch) {
+ for (cs = 0U; cs < CS_CNT; cs++) {
+ if (ddr_density[ch][cs] == 0xffU) {
+ mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00U);
+ } else {
+ mmio_write_32(DBSC_DBMEMCONF(ch, cs),
+ DBMEMCONF_REGD(ddr_density[ch]
+ [cs]));
+ }
+ }
+ mmio_write_32(DBSC_DBMEMCONF(ch, 2), 0x00000000U);
+ mmio_write_32(DBSC_DBMEMCONF(ch, 3), 0x00000000U);
+ }
+
+ mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010U);
+
+ /* set DBI */
+ if (board_cnf->dbi_en != 0U) {
+ mmio_write_32(DBSC_DBDBICNT, 0x00000003U);
+ }
+
+ /* set REFCYCLE */
+ data_l = (get_refperiod()) * ddr_mbps / 2000U / ddr_mbpsdiv;
+ mmio_write_32(DBSC_DBRFCNF1, 0x00080000U | (data_l & 0x0000ffffU));
+ mmio_write_32(DBSC_DBRFCNF2, 0x00010000U | DBSC_REFINTS);
+
+#if RCAR_REWT_TRAINING != 0
+ /* Periodic-WriteDQ Training seeting */
+ if ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut == PRR_PRODUCT_10)) {
+ /* G2M Ver.1.0 not support */
+ } else {
+ /* G2M Ver.1.1 or later */
+ mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000U);
+
+ ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04U);
+ ddr_setval_ach_as(_reg_PHY_WDQLVL_QTR_DLY_STEP, 0x0FU);
+ ddr_setval_ach_as(_reg_PHY_WDQLVL_DLY_STEP, 0x50U);
+ ddr_setval_ach_as(_reg_PHY_WDQLVL_DQDM_SLV_DLY_START, 0x0300U);
+
+ ddr_setval_ach(_reg_PI_WDQLVL_CS_MAP,
+ ddrtbl_getval(_cnf_DDR_PI_REGSET,
+ _reg_PI_WDQLVL_CS_MAP));
+ ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1fU);
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00U);
+ ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01U);
+ ddr_setval_ach(_reg_PI_TREF_F0, 0x0000U);
+ ddr_setval_ach(_reg_PI_TREF_F1, 0x0000U);
+ ddr_setval_ach(_reg_PI_TREF_F2, 0x0000U);
+
+ if (prr_product == PRR_PRODUCT_M3) {
+ ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02U);
+ } else {
+ ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02U);
+ }
+ ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01U);
+
+ /* DFI_PHYMSTR_ACK , WTmode setting */
+ /* DFI_PHYMSTR_ACK: WTmode =b'01 */
+ mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011U);
+ }
+#endif /* RCAR_REWT_TRAINING */
+ /* periodic dram zqcal enable */
+ mmio_write_32(DBSC_DBCALCNF, 0x01000010U);
+
+ /* periodic phy ctrl update enable */
+ if ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut < PRR_PRODUCT_30)) {
+ /* non : G2M Ver.1.x not support */
+ } else {
+ mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001U);
+ }
+
+#ifdef DDR_BACKUPMODE
+ /* SRX */
+ srx = 0x0A840001U; /* for All channels */
+ if (ddr_backup == DRAM_BOOT_STATUS_WARM) {
+#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0, 1 only) */
+ NOTICE("BL2: [DEBUG_MESS] DDR_BACKUPMODE_HALF\n");
+ srx = 0x0A040001U;
+#endif /* DDR_BACKUPMODE_HALF */
+ send_dbcmd(srx);
+ }
+#endif /* DDR_BACKUPMODE */
+
+ /* set Auto Refresh */
+ mmio_write_32(DBSC_DBRFEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != 0
+ /* Periodic WriteDQ Traning */
+ if ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut == PRR_PRODUCT_10)) {
+ /* non : G2M Ver.1.0 not support */
+ } else {
+ /* G2M Ver.1.1 or later */
+ ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100U);
+ }
+#endif /* RCAR_REWT_TRAINING */
+
+ /* dram access enable */
+ mmio_write_32(DBSC_DBACEN, 0x00000001U);
+
+ MSG_LF(__func__ "(done)");
+}
+
+/* DFI_INIT_START */
+static uint32_t dfi_init_start(void)
+{
+ uint32_t ch;
+ uint32_t phytrainingok;
+ uint32_t retry;
+ uint32_t data_l;
+ uint32_t ret = 0U;
+ const uint32_t RETRY_MAX = 0x10000U;
+
+ ddr_setval_ach_as(_reg_PHY_DLL_RST_EN, 0x02U);
+ dsb_sev();
+ ddrphy_regif_idle();
+
+ /* dll_rst negate */
+ foreach_vch(ch) {
+ mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01U);
+ }
+ dsb_sev();
+
+ /* wait init_complete */
+ phytrainingok = 0U;
+ retry = 0U;
+ while (retry++ < RETRY_MAX) {
+ foreach_vch(ch) {
+ data_l = mmio_read_32(DBSC_DBDFISTAT(ch));
+ if (data_l & 0x00000001U) {
+ phytrainingok |= (1U << ch);
+ }
+ }
+ dsb_sev();
+ if (phytrainingok == ddr_phyvalid) {
+ break;
+ }
+ if (retry % 256U == 0U) {
+ ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01U);
+ }
+ }
+
+ /* all ch ok? */
+ if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) {
+ ret = 0xffU;
+ goto done;
+ }
+
+ /*
+ * dbdficnt0:
+ * dfi_dram_clk_disable=0
+ * dfi_frequency = 0
+ * freq_ratio = 01 (2:1)
+ * init_start =0
+ */
+ foreach_vch(ch) {
+ mmio_write_32(DBSC_DBDFICNT(ch), 0x00000010U);
+ }
+ dsb_sev();
+done:
+ return ret;
+}
+
+/* drivability setting : CMOS MODE ON/OFF */
+static void change_lpddr4_en(uint32_t mode)
+{
+ uint32_t ch;
+ uint32_t i;
+ uint32_t data_l;
+ const uint32_t _reg_PHY_PAD_DRIVE_X[3] = {
+ _reg_PHY_PAD_ADDR_DRIVE,
+ _reg_PHY_PAD_CLK_DRIVE,
+ _reg_PHY_PAD_CS_DRIVE
+ };
+
+ foreach_vch(ch) {
+ for (i = 0U; i < 3U; i++) {
+ data_l = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]);
+ if (mode != 0U) {
+ data_l |= (1U << 14);
+ } else {
+ data_l &= ~(1U << 14);
+ }
+ ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], data_l);
+ }
+ }
+}
+
+/* drivability setting */
+static uint32_t set_term_code(void)
+{
+ uint32_t i;
+ uint32_t ch, index;
+ uint32_t data_l;
+ uint32_t chip_id[2];
+ uint32_t term_code;
+ uint32_t override;
+
+ term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_PAD_DATA_TERM);
+ override = 0U;
+ for (i = 0U; i < 2U; i++) {
+ chip_id[i] = mmio_read_32(LIFEC_CHIPID(i));
+ }
+
+ index = 0U;
+ while (true) {
+ if (termcode_by_sample[index][0] == 0xffffffff) {
+ break;
+ }
+ if ((termcode_by_sample[index][0] == chip_id[0]) &&
+ (termcode_by_sample[index][1] == chip_id[1])) {
+ term_code = termcode_by_sample[index][2];
+ override = 1;
+ break;
+ }
+ index++;
+ }
+
+ if (override != 0U) {
+ for (index = 0U; index < _reg_PHY_PAD_TERM_X_NUM; index++) {
+ data_l =
+ ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_PAD_TERM_X[index]);
+ data_l = (data_l & 0xfffe0000U) | term_code;
+ ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], data_l);
+ }
+ } else if ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut == PRR_PRODUCT_10)) {
+ /* non */
+ } else {
+ ddr_setval_ach(_reg_PHY_PAD_TERM_X[0],
+ (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_PAD_TERM_X[0]) & 0xFFFE0000U));
+ ddr_setval_ach(_reg_PHY_CAL_CLEAR_0, 0x01U);
+ ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01U);
+ foreach_vch(ch) {
+ do {
+ data_l =
+ ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0);
+ } while (!(data_l & 0x00800000U));
+ }
+
+ /* G2M Ver.1.1 or later */
+ foreach_vch(ch) {
+ for (index = 0U; index < _reg_PHY_PAD_TERM_X_NUM;
+ index++) {
+ data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[index]);
+ ddr_setval(ch, _reg_PHY_PAD_TERM_X[index],
+ (data_l & 0xFFFE0FFFU) | 0x00015000U);
+ }
+ }
+ }
+
+ ddr_padcal_tcompensate_getinit(override);
+
+ return 0U;
+}
+
+/* DDR mode register setting */
+static void ddr_register_set(void)
+{
+ int32_t fspwp;
+ uint32_t tmp;
+
+ for (fspwp = 1; fspwp >= 0; fspwp--) {
+ /*MR13, fspwp */
+ send_dbcmd(0x0e840d08U | ((2U - fspwp) << 6));
+
+ tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr1_data_fx_csx[fspwp][0]);
+ send_dbcmd(0x0e840100U | tmp);
+
+ tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr2_data_fx_csx[fspwp][0]);
+ send_dbcmd(0x0e840200U | tmp);
+
+ tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr3_data_fx_csx[fspwp][0]);
+ send_dbcmd(0x0e840300U | tmp);
+
+ tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr11_data_fx_csx[fspwp][0]);
+ send_dbcmd(0x0e840b00U | tmp);
+
+ tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr12_data_fx_csx[fspwp][0]);
+ send_dbcmd(0x0e840c00U | tmp);
+
+ tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr14_data_fx_csx[fspwp][0]);
+ send_dbcmd(0x0e840e00U | tmp);
+ /* MR22 */
+ send_dbcmd(0x0e841616U);
+
+ /* ZQCAL start */
+ send_dbcmd(0x0d84004FU);
+
+ /* ZQLAT */
+ send_dbcmd(0x0d840051U);
+ }
+
+ /* MR13, fspwp */
+ send_dbcmd(0x0e840d08U);
+}
+
+/* Training handshake functions */
+static inline uint32_t wait_freqchgreq(uint32_t assert)
+{
+ uint32_t data_l;
+ uint32_t count;
+ uint32_t ch;
+
+ count = 100000U;
+
+ if (assert != 0U) {
+ do {
+ data_l = 1U;
+ foreach_vch(ch) {
+ data_l &= mmio_read_32(DBSC_DBPDSTAT(ch));
+ }
+ count = count - 1U;
+ } while (((data_l & 0x01U) != 0x01U) && (count != 0U));
+ } else {
+ do {
+ data_l = 0U;
+ foreach_vch(ch) {
+ data_l |= mmio_read_32(DBSC_DBPDSTAT(ch));
+ }
+ count = count - 1U;
+ } while (((data_l & 0x01U) != 0x00U) && (count != 0U));
+ }
+
+ return (count == 0U);
+}
+
+static inline void set_freqchgack(uint32_t assert)
+{
+ uint32_t ch;
+ uint32_t data_l;
+
+ if (assert != 0U) {
+ data_l = 0x0CF20000U;
+ } else {
+ data_l = 0x00000000U;
+ }
+
+ foreach_vch(ch) {
+ mmio_write_32(DBSC_DBPDCNT2(ch), data_l);
+ }
+}
+
+static inline void set_dfifrequency(uint32_t freq)
+{
+ uint32_t ch;
+
+ foreach_vch(ch) {
+ mmio_clrsetbits_32(DBSC_DBDFICNT(ch), 0x1fU << 24, freq << 24);
+ }
+ dsb_sev();
+}
+
+static uint32_t pll3_freq(uint32_t on)
+{
+ uint32_t timeout;
+
+ timeout = wait_freqchgreq(1U);
+
+ if (timeout != 0U) {
+ return 1U;
+ }
+
+ pll3_control(on);
+ set_dfifrequency(on);
+
+ set_freqchgack(1U);
+ timeout = wait_freqchgreq(0U);
+ set_freqchgack(0U);
+
+ if (timeout != 0U) {
+ FATAL_MSG("BL2: Time out[2]\n");
+ return 1U;
+ }
+
+ return 0U;
+}
+
+/* update dly */
+static void update_dly(void)
+{
+ ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01U);
+ ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01U);
+}
+
+/* training by pi */
+static uint32_t pi_training_go(void)
+{
+ uint32_t flag;
+ uint32_t data_l;
+ uint32_t retry;
+ const uint32_t RETRY_MAX = 4096U * 16U;
+ uint32_t ch;
+ uint32_t mst_ch;
+ uint32_t cur_frq;
+ uint32_t complete;
+ uint32_t frqchg_req;
+
+ /* pi_start */
+ ddr_setval_ach(_reg_PI_START, 0x01U);
+ foreach_vch(ch) {
+ ddr_getval(ch, _reg_PI_INT_STATUS);
+ }
+
+ /* set dfi_phymstr_ack = 1 */
+ mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001U);
+ dsb_sev();
+
+ /* wait pi_int_status[0] */
+ mst_ch = 0U;
+ flag = 0U;
+ complete = 0U;
+ cur_frq = 0U;
+ for (retry = 0U; retry < RETRY_MAX; retry++) {
+ frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01;
+
+ if (frqchg_req != 0U) {
+ if (cur_frq != 0U) {
+ /* Low frequency */
+ flag = pll3_freq(0U);
+ cur_frq = 0U;
+ } else {
+ /* High frequency */
+ flag = pll3_freq(1U);
+ cur_frq = 1U;
+ }
+ if (flag != 0U) {
+ break;
+ }
+ } else {
+ if (cur_frq != 0U) {
+ foreach_vch(ch) {
+ if ((complete & (1U << ch)) != 0U) {
+ continue;
+ }
+ data_l = ddr_getval(ch, _reg_PI_INT_STATUS);
+ if ((data_l & 0x01U) != 0U) {
+ complete |= (1U << ch);
+ }
+ }
+ if (complete == ddr_phyvalid) {
+ break;
+ }
+ }
+ }
+ }
+ foreach_vch(ch) {
+ /* dummy read */
+ data_l = ddr_getval_s(ch, 0U, _reg_PHY_CAL_RESULT2_OBS_0);
+ data_l = ddr_getval(ch, _reg_PI_INT_STATUS);
+ ddr_setval(ch, _reg_PI_INT_ACK, data_l);
+ }
+ if (ddrphy_regif_chk() != 0U) {
+ complete = 0xfdU;
+ }
+ return complete;
+}
+
+/* Initialize DDR */
+static uint32_t init_ddr(void)
+{
+ uint32_t i;
+ uint32_t data_l;
+ uint32_t phytrainingok;
+ uint32_t ch, slice;
+ uint32_t index;
+ uint32_t err;
+ int16_t adj;
+
+ MSG_LF(__func__ ":0\n");
+
+ /* unlock phy */
+ /* Unlock DDRPHY register(AGAIN) */
+ foreach_vch(ch) {
+ mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55AU);
+ }
+ dsb_sev();
+
+ reg_ddrphy_write_a(0x00001010U, 0x00000001U);
+ /* DBSC register pre-setting */
+ dbsc_regset_pre();
+
+ /* load ddrphy registers */
+ ddrtbl_load();
+
+ /* configure ddrphy registers */
+ ddr_config();
+
+ /* dfi_reset assert */
+ foreach_vch(ch) {
+ mmio_write_32(DBSC_DBPDCNT0(ch), 0x01U);
+ }
+ dsb_sev();
+
+ /* dbsc register set */
+ dbsc_regset();
+ MSG_LF(__func__ ":1\n");
+
+ /* dfi_reset negate */
+ foreach_vch(ch) {
+ mmio_write_32(DBSC_DBPDCNT0(ch), 0x00U);
+ }
+ dsb_sev();
+
+ /* dfi_init_start (start ddrphy) */
+ err = dfi_init_start();
+ if (err != 0U) {
+ return INITDRAM_ERR_I;
+ }
+ MSG_LF(__func__ ":2\n");
+
+ /* ddr backupmode end */
+#ifdef DDR_BACKUPMODE
+ if (ddr_backup != 0U) {
+ NOTICE("BL2: [WARM_BOOT]\n");
+ } else {
+ NOTICE("BL2: [COLD_BOOT]\n");
+ }
+#endif
+ MSG_LF(__func__ ":3\n");
+
+ /* override term code after dfi_init_complete */
+ err = set_term_code();
+ if (err != 0U) {
+ return INITDRAM_ERR_I;
+ }
+ MSG_LF(__func__ ":4\n");
+
+ /* rx offset calibration */
+ if (prr_cut > PRR_PRODUCT_11) {
+ err = rx_offset_cal_hw();
+ } else {
+ err = rx_offset_cal();
+ }
+ if (err != 0U) {
+ return INITDRAM_ERR_O;
+ }
+ MSG_LF(__func__ ":5\n");
+
+ /* Dummy PDE */
+ send_dbcmd(0x08840000U);
+
+ /* PDX */
+ send_dbcmd(0x08840001U);
+
+ /* check register i/f is alive */
+ err = ddrphy_regif_chk();
+ if (err != 0U) {
+ return INITDRAM_ERR_O;
+ }
+ MSG_LF(__func__ ":6\n");
+
+ /* phy initialize end */
+
+ /* setup DDR mode registers */
+ /* CMOS MODE */
+ change_lpddr4_en(0);
+
+ /* MRS */
+ ddr_register_set();
+
+ /* Thermal sensor setting */
+ /* THCTR Bit6: PONM=0 , Bit0: THSST=1 */
+ data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBFU) | 0x00000001U;
+ mmio_write_32(THS1_THCTR, data_l);
+
+ /* LPDDR4 MODE */
+ change_lpddr4_en(1);
+
+ MSG_LF(__func__ ":7\n");
+
+ /* mask CS_MAP if RANKx is not found */
+ foreach_vch(ch) {
+ data_l = ddr_getval(ch, _reg_PI_CS_MAP);
+ if ((ch_have_this_cs[1] & (1U << ch)) == 0U) {
+ data_l = data_l & 0x05U;
+ }
+ ddr_setval(ch, _reg_PI_CS_MAP, data_l);
+ }
+
+ /* exec pi_training */
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
+ BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
+ ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00U);
+
+ foreach_vch(ch) {
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ ddr_setval_s(ch, slice,
+ _reg_PHY_PER_CS_TRAINING_EN,
+ ((ch_have_this_cs[1]) >> ch) & 0x01U);
+ }
+ }
+
+ phytrainingok = pi_training_go();
+
+ if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) {
+ return INITDRAM_ERR_T | phytrainingok;
+ }
+
+ MSG_LF(__func__ ":8\n");
+
+ /* CACS DLY ADJUST */
+ data_l = board_cnf->cacs_dly + (uint32_t)_f_scale_adj(board_cnf->cacs_dly_adj);
+ foreach_vch(ch) {
+ for (i = 0U; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
+ adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
+ ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
+ data_l + (uint32_t)adj);
+ }
+
+ if (ddr_phycaslice == 1U) {
+ for (i = 0U; i < 6U; i++) {
+ index = i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM;
+ adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[index]);
+ ddr_setval_s(ch, 2U,
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
+ data_l + (uint32_t)adj);
+ }
+ }
+ }
+
+ update_dly();
+ MSG_LF(__func__ ":9\n");
+
+ /* Adjust write path latency */
+ if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD) != 0U) {
+ adjust_wpath_latency();
+ }
+
+ /* RDQLVL Training */
+ if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0U) {
+ ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01U);
+ }
+
+ err = rdqdm_man();
+
+ if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0U) {
+ ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00U);
+ }
+
+ if (err != 0U) {
+ return INITDRAM_ERR_T;
+ }
+ update_dly();
+ MSG_LF(__func__ ":10\n");
+
+ /* WDQLVL Training */
+ err = wdqdm_man();
+ if (err != 0U) {
+ return INITDRAM_ERR_T;
+ }
+ update_dly();
+ MSG_LF(__func__ ":11\n");
+
+ dbsc_regset_post();
+ MSG_LF(__func__ ":12\n");
+
+ return phytrainingok;
+}
+
+/* SW LEVELING COMMON */
+static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick)
+{
+ const uint32_t RETRY_MAX = 0x1000U;
+ uint32_t ch, data_l;
+ uint32_t waiting;
+ uint32_t retry;
+ uint32_t err = 0U;
+
+ /* set EXIT -> OP_DONE is cleared */
+ ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01);
+
+ /* kick */
+ foreach_vch(ch) {
+ if ((ch_have_this_cs[ddr_csn % 2U] & (1U << ch)) != 0U) {
+ ddr_setval(ch, reg_cs, ddr_csn);
+ ddr_setval(ch, reg_kick, 0x01U);
+ }
+ }
+ foreach_vch(ch) {
+ /*PREPARE ADDR REGISTER (for SWLVL_OP_DONE) */
+ ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
+ }
+ waiting = ch_have_this_cs[ddr_csn % 2U];
+ dsb_sev();
+ retry = RETRY_MAX;
+ do {
+ foreach_vch(ch) {
+ if ((waiting & (1U << ch)) == 0U) {
+ continue;
+ }
+ data_l = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
+ if ((data_l & 0x01U) != 0U) {
+ waiting &= ~(1U << ch);
+ }
+ }
+ retry--;
+ } while ((waiting != 0U) && (retry > 0U));
+ if (retry == 0U) {
+ err = 1U;
+ }
+
+ dsb_sev();
+ /* set EXIT -> OP_DONE is cleared */
+ ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01U);
+ dsb_sev();
+
+ return err;
+}
+
+/* WDQ TRAINING */
+#ifndef DDR_FAST_INIT
+static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
+{
+ uint32_t cs, slice;
+ uint32_t data_l;
+ int32_t i, k;
+
+ /* clr of training results buffer */
+ cs = ddr_csn % 2U;
+ data_l = board_cnf->dqdm_dly_w;
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+ if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) {
+ continue;
+ }
+
+ for (i = 0; i <= 8; i++) {
+ if ((ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) != 0U) {
+ wdqdm_dly[ch][cs][slice][i] =
+ wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
+ } else {
+ wdqdm_dly[ch][cs][slice][i] = data_l;
+ }
+ wdqdm_le[ch][cs][slice][i] = 0U;
+ wdqdm_te[ch][cs][slice][i] = 0U;
+ }
+ wdqdm_st[ch][cs][slice] = 0U;
+ wdqdm_win[ch][cs][slice] = 0U;
+ }
+}
+
+static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
+{
+ const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0U;
+ uint32_t cs, slice;
+ uint32_t data_l;
+ int32_t min_win;
+ int32_t i, k;
+ uint32_t err;
+ int32_t win;
+ int8_t _adj;
+ int16_t adj;
+ uint32_t dq;
+
+ /* analysis of training results */
+ err = 0U;
+ for (slice = 0U; slice < SLICE_CNT; slice += 1U) {
+ k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+ if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) {
+ continue;
+ }
+
+ cs = ddr_csn % 2U;
+ ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
+ for (i = 0; i < 9; i++) {
+ dq = slice * 8U + i;
+ if (i == 8) {
+ _adj = board_cnf->ch[ch].dm_adj_w[slice];
+ } else {
+ _adj = board_cnf->ch[ch].dq_adj_w[dq];
+ }
+ adj = _f_scale_adj(_adj);
+
+ data_l =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj;
+ ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
+ data_l);
+ wdqdm_dly[ch][cs][slice][i] = data_l;
+ }
+ ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00);
+ data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS);
+ wdqdm_st[ch][cs][slice] = data_l;
+ min_win = INT_LEAST32_MAX;
+ for (i = 0; i <= 8; i++) {
+ ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT,
+ i);
+
+ data_l =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS);
+ wdqdm_te[ch][cs][slice][i] = data_l;
+ data_l =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS);
+ wdqdm_le[ch][cs][slice][i] = data_l;
+ win = (int32_t)wdqdm_te[ch][cs][slice][i] -
+ wdqdm_le[ch][cs][slice][i];
+ if (min_win > win) {
+ min_win = win;
+ }
+ if (data_l >= _par_WDQLVL_RETRY_THRES) {
+ err = 2;
+ }
+ }
+ wdqdm_win[ch][cs][slice] = min_win;
+ ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
+ ((ch_have_this_cs[1]) >> ch) & 0x01);
+ }
+ return err;
+}
+#endif/* DDR_FAST_INIT */
+
+static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore)
+{
+ uint32_t tgt_cs, src_cs;
+ uint32_t ch, slice;
+ uint32_t tmp_r;
+ uint32_t i;
+
+ /* copy of training results */
+ foreach_vch(ch) {
+ for (tgt_cs = 0U; tgt_cs < CS_CNT; tgt_cs++) {
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ ddr_setval_s(ch, slice,
+ _reg_PHY_PER_CS_TRAINING_INDEX,
+ tgt_cs);
+ src_cs = ddr_csn % 2U;
+ if ((ch_have_this_cs[1] & (1U << ch)) == 0U) {
+ src_cs = 0U;
+ }
+ for (i = 0U; i <= 4U; i += 4U) {
+ if (restore != 0U) {
+ tmp_r = rdqdm_dly[ch][tgt_cs][slice][i];
+ } else {
+ tmp_r = rdqdm_dly[ch][src_cs][slice][i];
+ }
+
+ ddr_setval_s(ch, slice,
+ _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i],
+ tmp_r);
+ }
+ }
+ }
+ }
+}
+
+static uint32_t wdqdm_man1(void)
+{
+ uint32_t mr14_csab0_bak[DRAM_CH_CNT];
+ uint32_t ch, cs, ddr_csn;
+ uint32_t data_l;
+ uint32_t err = 0U;
+#ifndef DDR_FAST_INIT
+ uint32_t err_flg = 0U;
+#endif/* DDR_FAST_INIT */
+
+ /* CLEAR PREV RESULT */
+ for (cs = 0U; cs < CS_CNT; cs++) {
+ ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs);
+ ddr_setval_ach_as(_reg_PHY_WDQLVL_CLR_PREV_RESULTS, 0x01U);
+ }
+ ddrphy_regif_idle();
+
+ for (ddr_csn = 0U; ddr_csn < CSAB_CNT; ddr_csn++) {
+ if (((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut == PRR_PRODUCT_10))) {
+ wdqdm_cp(ddr_csn, 0U);
+ }
+
+ foreach_vch(ch) {
+ data_l = ddr_getval(ch, reg_pi_mr14_data_fx_csx[1][ddr_csn]);
+ ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], data_l);
+ }
+
+ /* KICK WDQLVL */
+ err = swlvl1(ddr_csn, _reg_PI_WDQLVL_CS, _reg_PI_WDQLVL_REQ);
+ if (err != 0U) {
+ goto err_exit;
+ }
+
+ if (ddr_csn == 0U) {
+ foreach_vch(ch) {
+ mr14_csab0_bak[ch] = ddr_getval(ch,
+ reg_pi_mr14_data_fx_csx[1][0]);
+ }
+ } else {
+ foreach_vch(ch) {
+ ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0],
+ mr14_csab0_bak[ch]);
+ }
+ }
+#ifndef DDR_FAST_INIT
+ foreach_vch(ch) {
+ if ((ch_have_this_cs[ddr_csn % 2U] & (1U << ch)) == 0U) {
+ wdqdm_clr1(ch, ddr_csn);
+ continue;
+ }
+ err = wdqdm_ana1(ch, ddr_csn);
+ if (err != 0U) {
+ err_flg |= (1U << (ddr_csn * 4U + ch));
+ }
+ ddrphy_regif_idle();
+ }
+#endif/* DDR_FAST_INIT */
+ }
+err_exit:
+#ifndef DDR_FAST_INIT
+ err |= err_flg;
+#endif/* DDR_FAST_INIT */
+
+ return err;
+}
+
+static uint32_t wdqdm_man(void)
+{
+ uint32_t datal, ch, ddr_csn, mr14_bkup[4][4];
+ const uint32_t retry_max = 0x10U;
+ uint32_t err, retry_cnt;
+
+ datal = RL + js2[js2_tdqsck] + (16U / 2U) + 1U - WL + 2U + 2U + 19U;
+ if ((mmio_read_32(DBSC_DBTR(11)) & 0xFF) > datal) {
+ datal = mmio_read_32(DBSC_DBTR(11)) & 0xFF;
+ }
+ ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, datal);
+
+ ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR,
+ (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
+
+ ddr_setval_ach(_reg_PI_TRFC_F0, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
+ ddr_setval_ach(_reg_PI_TRFC_F1, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
+
+ retry_cnt = 0U;
+ err = 0U;
+ do {
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01);
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x01);
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0C);
+ dsb_sev();
+ err = wdqdm_man1();
+ foreach_vch(ch) {
+ for (ddr_csn = 0U; ddr_csn < CSAB_CNT; ddr_csn++) {
+ mr14_bkup[ch][ddr_csn] =
+ ddr_getval(ch, reg_pi_mr14_data_fx_csx
+ [1][ddr_csn]);
+ dsb_sev();
+ }
+ }
+
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x04);
+
+ pvtcode_update();
+ err = wdqdm_man1();
+ foreach_vch(ch) {
+ for (ddr_csn = 0U; ddr_csn < CSAB_CNT; ddr_csn++) {
+ mr14_bkup[ch][ddr_csn] =
+ (mr14_bkup[ch][ddr_csn] +
+ ddr_getval(ch, reg_pi_mr14_data_fx_csx
+ [1][ddr_csn])) / 2U;
+ ddr_setval(ch,
+ reg_pi_mr14_data_fx_csx[1]
+ [ddr_csn],
+ mr14_bkup[ch][ddr_csn]);
+ }
+ }
+
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x0U);
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0U);
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_START_POINT, 0x0U);
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT, 0x0U);
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE, 0x0U);
+
+ pvtcode_update2();
+ err = wdqdm_man1();
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x0U);
+
+ } while ((err != 0U) && (++retry_cnt < retry_max));
+
+ if (prr_product == PRR_PRODUCT_M3 && prr_cut <= PRR_PRODUCT_10) {
+ wdqdm_cp(0U, 1U);
+ }
+
+ return (retry_cnt >= retry_max);
+}
+
+/* RDQ TRAINING */
+#ifndef DDR_FAST_INIT
+static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
+{
+ uint32_t cs, slice;
+ uint32_t data_l;
+ int32_t i, k;
+
+ /* clr of training results buffer */
+ cs = ddr_csn % 2U;
+ data_l = board_cnf->dqdm_dly_r;
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+ if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) {
+ continue;
+ }
+
+ for (i = 0; i <= 8; i++) {
+ if ((ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) != 0U) {
+ rdqdm_dly[ch][cs][slice][i] =
+ rdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
+ rdqdm_dly[ch][cs][slice + SLICE_CNT][i] =
+ rdqdm_dly[ch][CS_CNT - 1 - cs][slice + SLICE_CNT][i];
+ } else {
+ rdqdm_dly[ch][cs][slice][i] = data_l;
+ rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l;
+ }
+ rdqdm_le[ch][cs][slice][i] = 0U;
+ rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0U;
+ rdqdm_te[ch][cs][slice][i] = 0U;
+ rdqdm_te[ch][cs][slice + SLICE_CNT][i] = 0U;
+ rdqdm_nw[ch][cs][slice][i] = 0U;
+ rdqdm_nw[ch][cs][slice + SLICE_CNT][i] = 0U;
+ }
+ rdqdm_st[ch][cs][slice] = 0U;
+ rdqdm_win[ch][cs][slice] = 0U;
+ }
+}
+
+static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
+{
+ uint32_t rdq_status_obs_select;
+ uint32_t cs, slice;
+ uint32_t data_l;
+ uint32_t err;
+ uint32_t dq;
+ int32_t min_win;
+ int8_t _adj;
+ int16_t adj;
+ int32_t min_win;
+ int32_t win;
+ int32_t i, k;
+
+ /* analysis of training results */
+ err = 0U;
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+ if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) {
+ continue;
+ }
+
+ cs = ddr_csn % 2U;
+ ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
+ ddrphy_regif_idle();
+
+ ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX);
+ ddrphy_regif_idle();
+
+ for (i = 0; i <= 8; i++) {
+ dq = slice * 8 + i;
+ if (i == 8) {
+ _adj = board_cnf->ch[ch].dm_adj_r[slice];
+ } else {
+ _adj = board_cnf->ch[ch].dq_adj_r[dq];
+ }
+
+ adj = _f_scale_adj(_adj);
+
+ data_l = ddr_getval_s(ch, slice,
+ _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
+ ddr_setval_s(ch, slice,
+ _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i],
+ data_l);
+ rdqdm_dly[ch][cs][slice][i] = data_l;
+
+ data_l = ddr_getval_s(ch, slice,
+ _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
+ ddr_setval_s(ch, slice,
+ _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i],
+ data_l);
+ rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l;
+ }
+ min_win = INT_LEAST32_MAX;
+ for (i = 0; i <= 8; i++) {
+ data_l =
+ ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS);
+ rdqdm_st[ch][cs][slice] = data_l;
+ rdqdm_st[ch][cs][slice + SLICE_CNT] = data_l;
+ /* k : rise/fall */
+ for (k = 0; k < 2; k++) {
+ if (i == 8) {
+ rdq_status_obs_select = 16 + 8 * k;
+ } else {
+ rdq_status_obs_select = i + k * 8;
+ }
+ ddr_setval_s(ch, slice,
+ _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT,
+ rdq_status_obs_select);
+
+ data_l =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS);
+ rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] = data_l;
+
+ data_l =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS);
+ rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] = data_l;
+
+ data_l =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS);
+ rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] = data_l;
+
+ win =
+ (int32_t)rdqdm_te[ch][cs][slice +
+ SLICE_CNT *
+ k][i] -
+ rdqdm_le[ch][cs][slice + SLICE_CNT * k][i];
+ if (i != 8) {
+ if (min_win > win) {
+ min_win = win;
+ }
+ }
+ }
+ }
+ rdqdm_win[ch][cs][slice] = min_win;
+ if (min_win <= 0) {
+ err = 2;
+ }
+ }
+ return err;
+}
+#else /* DDR_FAST_INIT */
+static void rdqdm_man1_set(uint32_t ddr_csn, uint32_t ch, uint32_t slice)
+{
+ uint32_t i, adj, data_l;
+
+ for (i = 0U; i <= 8U; i++) {
+ if (i == 8U) {
+ adj = _f_scale_adj(board_cnf->ch[ch].dm_adj_r[slice]);
+ } else {
+ adj = _f_scale_adj(board_cnf->ch[ch].dq_adj_r[slice * 8U + i]);
+ }
+ ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn);
+ data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
+ ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], data_l);
+ rdqdm_dly[ch][ddr_csn][slice][i] = data_l;
+ rdqdm_dly[ch][ddr_csn | 1U][slice][i] = data_l;
+
+ data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
+ ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], data_l);
+ rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = data_l;
+ rdqdm_dly[ch][ddr_csn | 1U][slice + SLICE_CNT][i] = data_l;
+ }
+}
+#endif /* DDR_FAST_INIT */
+
+static uint32_t rdqdm_man1(void)
+{
+ uint32_t ch;
+ uint32_t ddr_csn;
+ uint32_t val;
+#ifdef DDR_FAST_INIT
+ uint32_t slice;
+#endif/* DDR_FAST_INIT */
+ uint32_t err;
+
+ /* manual execution of training */
+ err = 0U;
+
+ for (ddr_csn = 0U; ddr_csn < CSAB_CNT; ddr_csn++) {
+ /* KICK RDQLVL */
+ err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ);
+ if (err != 0U) {
+ goto err_exit;
+ }
+#ifndef DDR_FAST_INIT
+ foreach_vch(ch) {
+ if ((ch_have_this_cs[ddr_csn % 2] & (1U << ch)) == 0U) {
+ rdqdm_clr1(ch, ddr_csn);
+ ddrphy_regif_idle();
+ continue;
+ }
+ err = rdqdm_ana1(ch, ddr_csn);
+ ddrphy_regif_idle();
+ if (err != 0U) {
+ goto err_exit;
+ }
+ }
+#else/* DDR_FAST_INIT */
+ foreach_vch(ch) {
+ if ((ch_have_this_cs[ddr_csn] & (1U << ch)) != 0U) {
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ val = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS);
+ if (val != 0x0D00FFFFU) {
+ err = (1U << ch) | (0x10U << slice);
+ goto err_exit;
+ }
+ }
+ }
+ if ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut <= PRR_PRODUCT_10)) {
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ rdqdm_man1_set(ddr_csn, ch, slice);
+ }
+ }
+ }
+ ddrphy_regif_idle();
+
+#endif/* DDR_FAST_INIT */
+ }
+
+err_exit:
+ return err;
+}
+
+static uint32_t rdqdm_man(void)
+{
+ uint32_t err, retry_cnt;
+ const uint32_t retry_max = 0x01U;
+
+ ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE,
+ 0x00000004U | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_DQ_TSEL_ENABLE));
+ ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE,
+ 0x00000004U | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_DQS_TSEL_ENABLE));
+ ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT,
+ 0xFF0FFFFFU & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_DQ_TSEL_SELECT));
+ ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT,
+ 0xFF0FFFFFU & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_DQS_TSEL_SELECT));
+
+ retry_cnt = 0U;
+ do {
+ err = rdqdm_man1();
+ ddrphy_regif_idle();
+ } while ((err != 0U) && (++retry_cnt < retry_max));
+ ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE,
+ ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_DQ_TSEL_ENABLE));
+ ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE,
+ ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_DQS_TSEL_ENABLE));
+ ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT,
+ ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_DQ_TSEL_SELECT));
+ ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT,
+ ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_DQS_TSEL_SELECT));
+
+ return (retry_cnt >= retry_max);
+}
+
+/* rx offset calibration */
+static int32_t _find_change(uint64_t val, uint32_t dir)
+{
+ int32_t i;
+ uint32_t startval;
+ uint32_t curval;
+ const int32_t VAL_END = 0x3fU;
+
+ if (dir == 0U) {
+ startval = (val & 0x01U);
+ for (i = 1; i <= VAL_END; i++) {
+ curval = (val >> i) & 0x01U;
+ if (curval != startval) {
+ return i;
+ }
+ }
+ return VAL_END;
+ }
+
+ startval = (val >> dir) & 0x01U;
+ for (i = (int32_t)dir - 1; i >= 0; i--) {
+ curval = (val >> i) & 0x01U;
+ if (curval != startval) {
+ return i;
+ }
+ }
+
+ return 0;
+}
+
+static uint32_t _rx_offset_cal_updn(uint32_t code)
+{
+ const uint32_t CODE_MAX = 0x40U;
+ uint32_t tmp;
+
+ if (code == 0U) {
+ tmp = (1U << 6) | (CODE_MAX - 1U);
+ } else {
+ tmp = (code << 6) | (CODE_MAX - code);
+ }
+
+ return tmp;
+}
+
+static uint32_t rx_offset_cal(void)
+{
+ uint32_t index;
+ uint32_t code;
+ const uint32_t CODE_MAX = 0x40U;
+ const uint32_t CODE_STEP = 2U;
+ uint32_t ch, slice;
+ uint32_t tmp;
+ uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
+ uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM];
+ uint64_t tmpval;
+ int32_t lsb, msb;
+
+ ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01);
+ foreach_vch(ch) {
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ for (index = 0U; index < _reg_PHY_RX_CAL_X_NUM; index++) {
+ val[ch][slice][index] = 0U;
+ }
+ }
+ }
+
+ for (code = 0U; code < CODE_MAX / CODE_STEP; code++) {
+ tmp = _rx_offset_cal_updn(code * CODE_STEP);
+ for (index = 0U; index < _reg_PHY_RX_CAL_X_NUM; index++) {
+ ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp);
+ }
+ dsb_sev();
+ ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as);
+
+ foreach_vch(ch) {
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ tmp = tmp_ach_as[ch][slice];
+ for (index = 0U; index < _reg_PHY_RX_CAL_X_NUM;
+ index++) {
+ if ((tmp & (1U << index)) != 0U) {
+ val[ch][slice][index] |=
+ (1ULL << code);
+ } else {
+ val[ch][slice][index] &=
+ ~(1ULL << code);
+ }
+ }
+ }
+ }
+ }
+ foreach_vch(ch) {
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ for (index = 0U; index < _reg_PHY_RX_CAL_X_NUM;
+ index++) {
+ tmpval = val[ch][slice][index];
+ lsb = _find_change(tmpval, 0U);
+ msb = _find_change(tmpval,
+ (CODE_MAX / CODE_STEP) - 1U);
+ tmp = (lsb + msb) >> 1U;
+
+ tmp = _rx_offset_cal_updn(tmp * CODE_STEP);
+ ddr_setval_s(ch, slice,
+ _reg_PHY_RX_CAL_X[index], tmp);
+ }
+ }
+ }
+ ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00);
+
+ return 0U;
+}
+
+static uint32_t rx_offset_cal_hw(void)
+{
+ uint32_t ch, slice;
+ uint32_t retry;
+ uint32_t complete;
+ uint32_t tmp;
+ uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
+
+ ddr_setval_ach_as(_reg_PHY_RX_CAL_X[9], 0x00);
+ ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00);
+ ddr_setval_ach_as(_reg_PHY_RX_CAL_SAMPLE_WAIT, 0x0f);
+
+ retry = 0U;
+ while (retry < 4096U) {
+ if ((retry & 0xffU) == 0U) {
+ ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01);
+ }
+ foreach_vch(ch) {
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ tmp_ach_as[ch][slice] =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_RX_CAL_X[9]);
+ }
+ }
+
+ complete = 1U;
+ foreach_vch(ch) {
+ for (slice = 0U; slice < SLICE_CNT; slice++) {
+ tmp = tmp_ach_as[ch][slice];
+ tmp = (tmp & 0x3fU) + ((tmp >> 6) & 0x3fU);
+ if (tmp != 0x40U) {
+ complete = 0U;
+ }
+ }
+ }
+ if (complete != 0U) {
+ break;
+ }
+
+ retry++;
+ }
+
+ return (complete == 0U);
+}
+
+/* adjust wpath latency */
+static void adjust_wpath_latency(void)
+{
+ uint32_t ch, cs, slice;
+ uint32_t dly;
+ uint32_t wpath_add;
+ const uint32_t _par_EARLY_THRESHOLD_VAL = 0x180U;
+
+ foreach_vch(ch) {
+ for (slice = 0U; slice < SLICE_CNT; slice += 1U) {
+ for (cs = 0U; cs < CS_CNT; cs++) {
+ ddr_setval_s(ch, slice,
+ _reg_PHY_PER_CS_TRAINING_INDEX,
+ cs);
+ ddr_getval_s(ch, slice,
+ _reg_PHY_PER_CS_TRAINING_INDEX);
+ dly =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_CLK_WRDQS_SLAVE_DELAY);
+ if (dly <= _par_EARLY_THRESHOLD_VAL) {
+ continue;
+ }
+
+ wpath_add =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_WRITE_PATH_LAT_ADD);
+ ddr_setval_s(ch, slice,
+ _reg_PHY_WRITE_PATH_LAT_ADD,
+ wpath_add - 1U);
+ }
+ }
+ }
+}
+
+/* DDR Initialize entry */
+int32_t rzg_dram_init(void)
+{
+ uint32_t ch, cs;
+ uint32_t data_l;
+ uint32_t bus_mbps, bus_mbpsdiv;
+ uint32_t tmp_tccd;
+ uint32_t failcount;
+ uint32_t cnf_boardtype;
+ int32_t ret = INITDRAM_NG;
+
+ /* Thermal sensor setting */
+ data_l = mmio_read_32(CPG_MSTPSR5);
+ if ((data_l & BIT(22)) != 0U) { /* case THS/TSC Standby */
+ data_l &= ~BIT(22);
+ cpg_write_32(CPG_SMSTPCR5, data_l);
+ while ((mmio_read_32(CPG_MSTPSR5) & BIT(22)) != 0U) {
+ /* wait bit=0 */
+ }
+ }
+
+ /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */
+ data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE;
+ mmio_write_32(THS1_THCTR, data_l);
+
+ /* Judge product and cut */
+#ifdef RCAR_DDR_FIXED_LSI_TYPE
+#if (RCAR_LSI == RCAR_AUTO)
+ prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
+ prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
+#else /* RCAR_LSI */
+#ifndef RCAR_LSI_CUT
+ prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
+#endif /* RCAR_LSI_CUT */
+#endif /* RCAR_LSI */
+#else /* RCAR_DDR_FIXED_LSI_TYPE */
+ prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
+ prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
+#endif /* RCAR_DDR_FIXED_LSI_TYPE */
+
+ if (prr_product == PRR_PRODUCT_M3) {
+ p_ddr_regdef_tbl =
+ (const uint32_t *)&DDR_REGDEF_TBL[1][0];
+ } else {
+ FATAL_MSG("BL2: DDR:Unknown Product\n");
+ goto done;
+ }
+
+ if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) {
+ /* non : G2M Ver.1.x not support */
+ } else {
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00001234U);
+ }
+
+ /* Judge board type */
+ cnf_boardtype = boardcnf_get_brd_type(prr_product);
+ if (cnf_boardtype >= (uint32_t)BOARDNUM) {
+ FATAL_MSG("BL2: DDR:Unknown Board\n");
+ goto done;
+ }
+ board_cnf = (const struct _boardcnf *)&boardcnfs[cnf_boardtype];
+
+/* RCAR_DRAM_SPLIT_2CH (2U) */
+#if RCAR_DRAM_SPLIT == 2
+ ddr_phyvalid = board_cnf->phyvalid;
+#else /* RCAR_DRAM_SPLIT_2CH */
+ ddr_phyvalid = board_cnf->phyvalid;
+#endif /* RCAR_DRAM_SPLIT_2CH */
+
+ max_density = 0U;
+
+ for (cs = 0U; cs < CS_CNT; cs++) {
+ ch_have_this_cs[cs] = 0U;
+ }
+
+ foreach_ech(ch) {
+ for (cs = 0U; cs < CS_CNT; cs++) {
+ ddr_density[ch][cs] = 0xffU;
+ }
+ }
+
+ foreach_vch(ch) {
+ for (cs = 0U; cs < CS_CNT; cs++) {
+ data_l = board_cnf->ch[ch].ddr_density[cs];
+ ddr_density[ch][cs] = data_l;
+
+ if (data_l == 0xffU) {
+ continue;
+ }
+ if (data_l > max_density) {
+ max_density = data_l;
+ }
+ ch_have_this_cs[cs] |= (1U << ch);
+ }
+ }
+
+ /* Judge board clock frequency (in MHz) */
+ boardcnf_get_brd_clk(cnf_boardtype, &brd_clk, &brd_clkdiv);
+ if ((brd_clk / brd_clkdiv) > 25U) {
+ brd_clkdiva = 1U;
+ } else {
+ brd_clkdiva = 0U;
+ }
+
+ /* Judge ddr operating frequency clock(in Mbps) */
+ boardcnf_get_ddr_mbps(cnf_boardtype, &ddr_mbps, &ddr_mbpsdiv);
+
+ ddr0800_mul = CLK_DIV(800U, 2U, brd_clk, brd_clkdiv * (brd_clkdiva + 1U));
+
+ ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2U, brd_clk,
+ brd_clkdiv * (brd_clkdiva + 1U));
+
+ /* Adjust tccd */
+ data_l = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13;
+ bus_mbps = 0U;
+ bus_mbpsdiv = 0U;
+ switch (data_l) {
+ case 0:
+ bus_mbps = brd_clk * 0x60U * 2U;
+ bus_mbpsdiv = brd_clkdiv * 1U;
+ break;
+ case 1:
+ bus_mbps = brd_clk * 0x50U * 2U;
+ bus_mbpsdiv = brd_clkdiv * 1U;
+ break;
+ case 2:
+ bus_mbps = brd_clk * 0x40U * 2U;
+ bus_mbpsdiv = brd_clkdiv * 1U;
+ break;
+ case 3:
+ bus_mbps = brd_clk * 0x60U * 2U;
+ bus_mbpsdiv = brd_clkdiv * 2U;
+ break;
+ default:
+ bus_mbps = brd_clk * 0x60U * 2U;
+ bus_mbpsdiv = brd_clkdiv * 2U;
+ WARN("BL2: DDR using default values for adjusting tccd");
+ break;
+ }
+ tmp_tccd = CLK_DIV(ddr_mbps * 8U, ddr_mbpsdiv, bus_mbps, bus_mbpsdiv);
+ if (8U * ddr_mbps * bus_mbpsdiv != tmp_tccd * bus_mbps * ddr_mbpsdiv) {
+ tmp_tccd = tmp_tccd + 1U;
+ }
+
+ if (tmp_tccd < 8U) {
+ ddr_tccd = 8U;
+ } else {
+ ddr_tccd = tmp_tccd;
+ }
+
+ NOTICE("BL2: DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION);
+
+ MSG_LF("Start\n");
+
+ /* PLL Setting */
+ pll3_control(1U);
+
+ /* initialize DDR */
+ data_l = init_ddr();
+ if (data_l == ddr_phyvalid) {
+ failcount = 0U;
+ } else {
+ failcount = 1U;
+ }
+
+ foreach_vch(ch) {
+ mmio_write_32(DBSC_DBPDLK(ch), 0x00000000U);
+ }
+ if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) {
+ /* non : G2M Ver.1.x not support */
+ } else {
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
+ }
+
+ if (failcount == 0U) {
+ ret = INITDRAM_OK;
+ }
+
+done:
+ return ret;
+}
+
+static void pvtcode_update(void)
+{
+ uint32_t ch;
+ uint32_t data_l;
+ uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init;
+ int32_t pvtp_tmp, pvtn_tmp;
+
+ foreach_vch(ch) {
+ pvtn_init = (tcal.tcomp_cal[ch] & 0xFC0U) >> 6;
+ pvtp_init = (tcal.tcomp_cal[ch] & 0x03FU) >> 0;
+
+ if (8912U * pvtp_init > 44230U) {
+ pvtp_tmp = (5000U + 8912U * pvtp_init - 44230U) / 10000U;
+ } else {
+ pvtp_tmp =
+ -((-(5000 + 8912 * pvtp_init - 44230)) / 10000);
+ }
+ pvtn_tmp = (5000U + 5776U * (uint32_t)pvtn_init + 30280U) / 10000U;
+
+ pvtn[ch] = (uint32_t)pvtn_tmp + pvtn_init;
+ pvtp[ch] = (uint32_t)pvtp_tmp + pvtp_init;
+
+ if (pvtn[ch] > 63U) {
+ pvtn[ch] = 63U;
+ pvtp[ch] =
+ (pvtp_tmp) * (63 - 6 * pvtn_tmp -
+ pvtn_init) / (pvtn_tmp) +
+ 6 * pvtp_tmp + pvtp_init;
+ }
+
+ data_l = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000U;
+ reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
+ data_l | 0x00020000U);
+ reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
+ data_l);
+ reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
+ data_l);
+ reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
+ data_l);
+ reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
+ data_l);
+ }
+}
+
+static void pvtcode_update2(void)
+{
+ uint32_t ch;
+
+ foreach_vch(ch) {
+ reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
+ tcal.init_cal[ch] | 0x00020000U);
+ reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
+ tcal.init_cal[ch]);
+ reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
+ tcal.init_cal[ch]);
+ reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
+ tcal.init_cal[ch]);
+ reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
+ tcal.init_cal[ch]);
+ }
+}
+
+static void ddr_padcal_tcompensate_getinit(uint32_t override)
+{
+ uint32_t ch;
+ uint32_t data_l;
+ uint32_t pvtp, pvtn;
+
+ tcal.init_temp = 0;
+ for (ch = 0U; ch < 4U; ch++) {
+ tcal.init_cal[ch] = 0U;
+ tcal.tcomp_cal[ch] = 0U;
+ }
+
+ foreach_vch(ch) {
+ tcal.init_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]);
+ tcal.tcomp_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]);
+ }
+
+ if (override == 0U) {
+ data_l = mmio_read_32(THS1_TEMP);
+ if (data_l < 2800U) {
+ tcal.init_temp =
+ (143 * (int32_t)data_l - 359000) / 1000;
+ } else {
+ tcal.init_temp =
+ (121 * (int32_t)data_l - 296300) / 1000;
+ }
+
+ foreach_vch(ch) {
+ pvtp = (tcal.init_cal[ch] >> 0) & 0x000003FU;
+ pvtn = (tcal.init_cal[ch] >> 6) & 0x000003FU;
+ if ((int32_t)pvtp >
+ ((tcal.init_temp * 29 - 3625) / 1000)) {
+ pvtp = (int32_t)pvtp +
+ ((3625 - tcal.init_temp * 29) / 1000);
+ } else {
+ pvtp = 0U;
+ }
+
+ if ((int32_t)pvtn >
+ ((tcal.init_temp * 54 - 6750) / 1000)) {
+ pvtn = (int32_t)pvtn +
+ ((6750 - tcal.init_temp * 54) / 1000);
+ } else {
+ pvtn = 0U;
+ }
+
+ tcal.init_cal[ch] = 0x00015000U | (pvtn << 6) | pvtp;
+ }
+ tcal.init_temp = 125;
+ }
+}
+
+#ifndef DDR_QOS_INIT_SETTING
+/* For QoS init */
+uint8_t rzg_get_boardcnf_phyvalid(void)
+{
+ return ddr_phyvalid;
+}
+#endif /* DDR_QOS_INIT_SETTING */
diff --git a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_config.c b/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_config.c
new file mode 100644
index 0000000000..345ef24c35
--- /dev/null
+++ b/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_config.c
@@ -0,0 +1,277 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define BOARDNUM 2
+#define BOARD_JUDGE_AUTO
+
+#ifdef BOARD_JUDGE_AUTO
+static uint32_t _board_judge(uint32_t prr_product);
+
+static uint32_t boardcnf_get_brd_type(uint32_t prr_product)
+{
+ return _board_judge(prr_product);
+}
+#else /* BOARD_JUDGE_AUTO */
+static uint32_t boardcnf_get_brd_type(void)
+{
+ return 1U;
+}
+#endif /* BOARD_JUDGE_AUTO */
+
+#define DDR_FAST_INIT
+
+struct _boardcnf_ch {
+ uint8_t ddr_density[CS_CNT];
+ uint64_t ca_swap;
+ uint16_t dqs_swap;
+ uint32_t dq_swap[SLICE_CNT];
+ uint8_t dm_swap[SLICE_CNT];
+ uint16_t wdqlvl_patt[16];
+ int8_t cacs_adj[16];
+ int8_t dm_adj_w[SLICE_CNT];
+ int8_t dq_adj_w[SLICE_CNT * 8U];
+ int8_t dm_adj_r[SLICE_CNT];
+ int8_t dq_adj_r[SLICE_CNT * 8U];
+};
+
+struct _boardcnf {
+ uint8_t phyvalid;
+ uint8_t dbi_en;
+ uint16_t cacs_dly;
+ int16_t cacs_dly_adj;
+ uint16_t dqdm_dly_w;
+ uint16_t dqdm_dly_r;
+ struct _boardcnf_ch ch[DRAM_CH_CNT];
+};
+
+#define WDQLVL_PAT {\
+ 0x00AA,\
+ 0x0055,\
+ 0x00AA,\
+ 0x0155,\
+ 0x01CC,\
+ 0x0133,\
+ 0x00CC,\
+ 0x0033,\
+ 0x00F0,\
+ 0x010F,\
+ 0x01F0,\
+ 0x010F,\
+ 0x00F0,\
+ 0x00F0,\
+ 0x000F,\
+ 0x010F}
+
+static const struct _boardcnf boardcnfs[BOARDNUM] = {
+ {
+/* boardcnf[0] HopeRun HiHope RZ/G2M 16Gbit/1rank/2ch board with G2M SoC */
+ .phyvalid = 0x03,
+ .dbi_en = 0x01,
+ .cacs_dly = 0x02c0,
+ .cacs_dly_adj = 0,
+ .dqdm_dly_w = 0x0300,
+ .dqdm_dly_r = 0x00a0,
+ .ch = {
+ {
+ {0x04, 0xff},
+ 0x00345201U,
+ 0x3201,
+ {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+
+ {
+ {0x04, 0xff},
+ 0x00302154U,
+ 0x2310,
+ {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[1] HopeRun HiHope RZ/G2M 8Gbit/2rank/2ch board with G2M SoC */
+ {
+ 0x03,
+ 0x01,
+ 0x02c0,
+ 0,
+ 0x0300,
+ 0x00a0,
+ {
+ {
+ {0x02, 0x02},
+ 0x00345201U,
+ 0x3201,
+ {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0x02},
+ 0x00302154U,
+ 0x2310,
+ {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ }
+};
+
+void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div)
+{
+ uint32_t md;
+
+ md = (mmio_read_32(RST_MODEMR) >> 13) & 0x3U;
+ switch (md) {
+ case 0x0U:
+ *clk = 50U;
+ *div = 3U;
+ break;
+ case 0x1U:
+ *clk = 60U;
+ *div = 3U;
+ break;
+ case 0x2U:
+ *clk = 75U;
+ *div = 3U;
+ break;
+ case 0x3U:
+ *clk = 100U;
+ *div = 3U;
+ break;
+ default:
+ break;
+ }
+ (void)brd;
+}
+
+void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div)
+{
+ uint32_t md;
+
+ md = (mmio_read_32(RST_MODEMR) >> 17U) & 0x5U;
+ md = (md | (md >> 1U)) & 0x3U;
+ switch (md) {
+ case 0x0U:
+ *mbps = 3200U;
+ *div = 1U;
+ break;
+ case 0x1U:
+ *mbps = 2800U;
+ *div = 1U;
+ break;
+ case 0x2U:
+ *mbps = 2400U;
+ *div = 1U;
+ break;
+ case 0x3U:
+ *mbps = 1600U;
+ *div = 1U;
+ break;
+ default:
+ break;
+ }
+ (void)brd;
+}
+
+#define _def_REFPERIOD 1890
+
+#define M3_SAMPLE_TT_A84 0xB866CC10U, 0x3B250421U
+#define M3_SAMPLE_TT_A85 0xB866CC10U, 0x3AA50421U
+#define M3_SAMPLE_TT_A86 0xB866CC10U, 0x3AA48421U
+#define M3_SAMPLE_FF_B45 0xB866CC10U, 0x3AB00C21U
+#define M3_SAMPLE_FF_B49 0xB866CC10U, 0x39B10C21U
+#define M3_SAMPLE_FF_B56 0xB866CC10U, 0x3AAF8C21U
+#define M3_SAMPLE_SS_E24 0xB866CC10U, 0x3BA39421U
+#define M3_SAMPLE_SS_E28 0xB866CC10U, 0x3C231421U
+#define M3_SAMPLE_SS_E32 0xB866CC10U, 0x3C241421U
+
+static const uint32_t termcode_by_sample[20][3] = {
+ { M3_SAMPLE_TT_A84, 0x000158D5U },
+ { M3_SAMPLE_TT_A85, 0x00015955U },
+ { M3_SAMPLE_TT_A86, 0x00015955U },
+ { M3_SAMPLE_FF_B45, 0x00015690U },
+ { M3_SAMPLE_FF_B49, 0x00015753U },
+ { M3_SAMPLE_FF_B56, 0x00015793U },
+ { M3_SAMPLE_SS_E24, 0x00015996U },
+ { M3_SAMPLE_SS_E28, 0x000159D7U },
+ { M3_SAMPLE_SS_E32, 0x00015997U },
+ { 0xFFFFFFFFU, 0xFFFFFFFFU, 0x0001554FU}
+};
+
+#ifdef BOARD_JUDGE_AUTO
+/* Board detect function */
+#define GPIO_INDT5 0xE605500CU
+#define LPDDR4_2RANK (0x01U << 25U)
+
+static uint32_t _board_judge(uint32_t prr_product)
+{
+ uint32_t boardInfo;
+ uint32_t boardid = 1U;
+
+ if (prr_product == PRR_PRODUCT_M3) {
+ if ((mmio_read_32(PRR) & PRR_CUT_MASK) != RCAR_M3_CUT_VER11) {
+ boardInfo = mmio_read_32(GPIO_INDT5);
+ if ((boardInfo & LPDDR4_2RANK) == 0U) {
+ boardid = 0U;
+ }
+ }
+ }
+
+ return boardid;
+}
+#endif /* BOARD_JUDGE_AUTO */
diff --git a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_regdef.h
new file mode 100644
index 0000000000..9f1c9368be
--- /dev/null
+++ b/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_regdef.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RZG_BOOT_INIT_DRAM_REGDEF_H
+#define RZG_BOOT_INIT_DRAM_REGDEF_H
+
+#define RCAR_DDR_VERSION "rev.0.40"
+#define DRAM_CH_CNT 0x04U
+#define SLICE_CNT 0x04U
+#define CS_CNT 0x02U
+
+/* order : CS0A, CS0B, CS1A, CS1B */
+#define CSAB_CNT (CS_CNT * 2U)
+
+/* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */
+#define CHAB_CNT (DRAM_CH_CNT * 2)
+
+/* pll setting */
+#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
+#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
+
+/* for ddr density setting */
+#define DBMEMCONF_REG(d3, row, bank, col, dw) \
+ (((d3) << 30U) | ((row) << 24U) | ((bank) << 16U) | ((col) << 8U) | (dw))
+
+#define DBMEMCONF_REGD(density) \
+ (DBMEMCONF_REG((density) % 2U, ((density) + 1U) / \
+ 2U + (29U - 3U - 10U - 2U), 3U, 10U, 2U))
+
+#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
+
+/* refresh mode */
+#define DBSC_REFINTS (0x0U)
+
+/* system registers */
+#define CPG_FRQCRB (CPG_BASE + 0x0004U)
+
+#define CPG_PLLECR (CPG_BASE + 0x00D0U)
+#define CPG_MSTPSR5 (CPG_BASE + 0x003CU)
+#define CPG_SRCR4 (CPG_BASE + 0x00BCU)
+#define CPG_PLL3CR (CPG_BASE + 0x00DCU)
+#define CPG_ZB3CKCR (CPG_BASE + 0x0380U)
+#define CPG_FRQCRD (CPG_BASE + 0x00E4U)
+#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U)
+#define CPG_CPGWPR (CPG_BASE + 0x0900U)
+#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U)
+
+#define CPG_FRQCRB_KICK_BIT BIT(31)
+#define CPG_PLLECR_PLL3E_BIT BIT(3)
+#define CPG_PLLECR_PLL3ST_BIT BIT(11)
+#define CPG_ZB3CKCR_ZB3ST_BIT BIT(11)
+
+#define RST_BASE (0xE6160000U)
+#define RST_MODEMR (RST_BASE + 0x0060U)
+
+#define LIFEC_CHIPID(x) (0xE6110040U + 0x04U * (x))
+
+/* DBSC registers */
+#include "ddr_regs.h"
+
+#define DBSC_DBMONCONF4 0xE6793010U
+
+#define DBSC_PLL_LOCK(ch) (0xE6794054U + 0x100U * (ch))
+#define DBSC_PLL_LOCK_0 0xE6794054U
+#define DBSC_PLL_LOCK_1 0xE6794154U
+#define DBSC_PLL_LOCK_2 0xE6794254U
+#define DBSC_PLL_LOCK_3 0xE6794354U
+
+/* STAT registers */
+#define MSTAT_SL_INIT 0xE67E8000U
+#define MSTAT_REF_ARS 0xE67E8004U
+#define MSTATQ_STATQC 0xE67E8008U
+#define MSTATQ_WTENABLE 0xE67E8030U
+#define MSTATQ_WTREFRESH 0xE67E8034U
+#define MSTATQ_WTSETTING0 0xE67E8038U
+#define MSTATQ_WTSETTING1 0xE67E803CU
+
+#define QOS_BASE1 (0xE67F0000U)
+#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U)
+#define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U)
+#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U)
+#define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U)
+#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U)
+#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U)
+#define QOSCTRL_EC (QOS_BASE1 + 0x003CU)
+#define QOSCTRL_EMS (QOS_BASE1 + 0x0040U)
+#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U)
+#define QOSCTRL_BERR (QOS_BASE1 + 0x0054U)
+#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U)
+#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U)
+
+/* other module */
+#define THS1_THCTR 0xE6198020U
+#define THS1_TEMP 0xE6198028U
+
+#endif /* RZG_BOOT_INIT_DRAM_REGDEF_H */
diff --git a/drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk b/drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk
new file mode 100644
index 0000000000..c137f26240
--- /dev/null
+++ b/drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BL2_SOURCES += drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c
diff --git a/drivers/renesas/rzg/ddr/ddr_b/ddr_regdef.h b/drivers/renesas/rzg/ddr/ddr_b/ddr_regdef.h
new file mode 100644
index 0000000000..1da455f916
--- /dev/null
+++ b/drivers/renesas/rzg/ddr/ddr_b/ddr_regdef.h
@@ -0,0 +1,5891 @@
+/*
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RZG_DDR_REGDEF_H
+#define RZG_DDR_REGDEF_H
+
+#define _reg_PHY_DQ_DM_SWIZZLE0 0x00000000U
+#define _reg_PHY_DQ_DM_SWIZZLE1 0x00000001U
+#define _reg_PHY_CLK_WR_BYPASS_SLAVE_DELAY 0x00000002U
+#define _reg_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY 0x00000003U
+#define _reg_PHY_BYPASS_TWO_CYC_PREAMBLE 0x00000004U
+#define _reg_PHY_CLK_BYPASS_OVERRIDE 0x00000005U
+#define _reg_PHY_SW_WRDQ0_SHIFT 0x00000006U
+#define _reg_PHY_SW_WRDQ1_SHIFT 0x00000007U
+#define _reg_PHY_SW_WRDQ2_SHIFT 0x00000008U
+#define _reg_PHY_SW_WRDQ3_SHIFT 0x00000009U
+#define _reg_PHY_SW_WRDQ4_SHIFT 0x0000000aU
+#define _reg_PHY_SW_WRDQ5_SHIFT 0x0000000bU
+#define _reg_PHY_SW_WRDQ6_SHIFT 0x0000000cU
+#define _reg_PHY_SW_WRDQ7_SHIFT 0x0000000dU
+#define _reg_PHY_SW_WRDM_SHIFT 0x0000000eU
+#define _reg_PHY_SW_WRDQS_SHIFT 0x0000000fU
+#define _reg_PHY_DQ_TSEL_ENABLE 0x00000010U
+#define _reg_PHY_DQ_TSEL_SELECT 0x00000011U
+#define _reg_PHY_DQS_TSEL_ENABLE 0x00000012U
+#define _reg_PHY_DQS_TSEL_SELECT 0x00000013U
+#define _reg_PHY_TWO_CYC_PREAMBLE 0x00000014U
+#define _reg_PHY_DBI_MODE 0x00000015U
+#define _reg_PHY_PER_RANK_CS_MAP 0x00000016U
+#define _reg_PHY_PER_CS_TRAINING_MULTICAST_EN 0x00000017U
+#define _reg_PHY_PER_CS_TRAINING_INDEX 0x00000018U
+#define _reg_PHY_LP4_BOOT_RDDATA_EN_IE_DLY 0x00000019U
+#define _reg_PHY_LP4_BOOT_RDDATA_EN_DLY 0x0000001aU
+#define _reg_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY 0x0000001bU
+#define _reg_PHY_LP4_BOOT_RPTR_UPDATE 0x0000001cU
+#define _reg_PHY_LP4_BOOT_RDDQS_GATE_SLAVE_DELAY 0x0000001dU
+#define _reg_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST 0x0000001eU
+#define _reg_PHY_LP4_BOOT_WRPATH_GATE_DISABLE 0x0000001fU
+#define _reg_PHY_LP4_BOOT_RDDATA_EN_OE_DLY 0x00000020U
+#define _reg_PHY_LPBK_CONTROL 0x00000021U
+#define _reg_PHY_LPBK_DFX_TIMEOUT_EN 0x00000022U
+#define _reg_PHY_AUTO_TIMING_MARGIN_CONTROL 0x00000023U
+#define _reg_PHY_AUTO_TIMING_MARGIN_OBS 0x00000024U
+#define _reg_PHY_SLICE_PWR_RDC_DISABLE 0x00000025U
+#define _reg_PHY_PRBS_PATTERN_START 0x00000026U
+#define _reg_PHY_PRBS_PATTERN_MASK 0x00000027U
+#define _reg_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY 0x00000028U
+#define _reg_PHY_GATE_ERROR_DELAY_SELECT 0x00000029U
+#define _reg_SC_PHY_SNAP_OBS_REGS 0x0000002aU
+#define _reg_PHY_LPDDR 0x0000002bU
+#define _reg_PHY_LPDDR_TYPE 0x0000002cU
+#define _reg_PHY_GATE_SMPL1_SLAVE_DELAY 0x0000002dU
+#define _reg_PHY_GATE_SMPL2_SLAVE_DELAY 0x0000002eU
+#define _reg_ON_FLY_GATE_ADJUST_EN 0x0000002fU
+#define _reg_PHY_GATE_TRACKING_OBS 0x00000030U
+#define _reg_PHY_DFI40_POLARITY 0x00000031U
+#define _reg_PHY_LP4_PST_AMBLE 0x00000032U
+#define _reg_PHY_RDLVL_PATT8 0x00000033U
+#define _reg_PHY_RDLVL_PATT9 0x00000034U
+#define _reg_PHY_RDLVL_PATT10 0x00000035U
+#define _reg_PHY_RDLVL_PATT11 0x00000036U
+#define _reg_PHY_LP4_RDLVL_PATT8 0x00000037U
+#define _reg_PHY_LP4_RDLVL_PATT9 0x00000038U
+#define _reg_PHY_LP4_RDLVL_PATT10 0x00000039U
+#define _reg_PHY_LP4_RDLVL_PATT11 0x0000003aU
+#define _reg_PHY_SLAVE_LOOP_CNT_UPDATE 0x0000003bU
+#define _reg_PHY_SW_FIFO_PTR_RST_DISABLE 0x0000003cU
+#define _reg_PHY_MASTER_DLY_LOCK_OBS_SELECT 0x0000003dU
+#define _reg_PHY_RDDQ_ENC_OBS_SELECT 0x0000003eU
+#define _reg_PHY_RDDQS_DQ_ENC_OBS_SELECT 0x0000003fU
+#define _reg_PHY_WR_ENC_OBS_SELECT 0x00000040U
+#define _reg_PHY_WR_SHIFT_OBS_SELECT 0x00000041U
+#define _reg_PHY_FIFO_PTR_OBS_SELECT 0x00000042U
+#define _reg_PHY_LVL_DEBUG_MODE 0x00000043U
+#define _reg_SC_PHY_LVL_DEBUG_CONT 0x00000044U
+#define _reg_PHY_WRLVL_CAPTURE_CNT 0x00000045U
+#define _reg_PHY_WRLVL_UPDT_WAIT_CNT 0x00000046U
+#define _reg_PHY_WRLVL_DQ_MASK 0x00000047U
+#define _reg_PHY_GTLVL_CAPTURE_CNT 0x00000048U
+#define _reg_PHY_GTLVL_UPDT_WAIT_CNT 0x00000049U
+#define _reg_PHY_RDLVL_CAPTURE_CNT 0x0000004aU
+#define _reg_PHY_RDLVL_UPDT_WAIT_CNT 0x0000004bU
+#define _reg_PHY_RDLVL_OP_MODE 0x0000004cU
+#define _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT 0x0000004dU
+#define _reg_PHY_RDLVL_DATA_MASK 0x0000004eU
+#define _reg_PHY_RDLVL_DATA_SWIZZLE 0x0000004fU
+#define _reg_PHY_WDQLVL_BURST_CNT 0x00000050U
+#define _reg_PHY_WDQLVL_PATT 0x00000051U
+#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET 0x00000052U
+#define _reg_PHY_WDQLVL_UPDT_WAIT_CNT 0x00000053U
+#define _reg_PHY_WDQLVL_DQDM_OBS_SELECT 0x00000054U
+#define _reg_PHY_WDQLVL_QTR_DLY_STEP 0x00000055U
+#define _reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS 0x00000056U
+#define _reg_PHY_WDQLVL_CLR_PREV_RESULTS 0x00000057U
+#define _reg_PHY_WDQLVL_DATADM_MASK 0x00000058U
+#define _reg_PHY_USER_PATT0 0x00000059U
+#define _reg_PHY_USER_PATT1 0x0000005aU
+#define _reg_PHY_USER_PATT2 0x0000005bU
+#define _reg_PHY_USER_PATT3 0x0000005cU
+#define _reg_PHY_USER_PATT4 0x0000005dU
+#define _reg_PHY_DQ_SWIZZLING 0x0000005eU
+#define _reg_PHY_CALVL_VREF_DRIVING_SLICE 0x0000005fU
+#define _reg_SC_PHY_MANUAL_CLEAR 0x00000060U
+#define _reg_PHY_FIFO_PTR_OBS 0x00000061U
+#define _reg_PHY_LPBK_RESULT_OBS 0x00000062U
+#define _reg_PHY_LPBK_ERROR_COUNT_OBS 0x00000063U
+#define _reg_PHY_MASTER_DLY_LOCK_OBS 0x00000064U
+#define _reg_PHY_RDDQ_SLV_DLY_ENC_OBS 0x00000065U
+#define _reg_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS 0x00000066U
+#define _reg_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS 0x00000067U
+#define _reg_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS 0x00000068U
+#define _reg_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS 0x00000069U
+#define _reg_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS 0x0000006aU
+#define _reg_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS 0x0000006bU
+#define _reg_PHY_WR_ADDER_SLV_DLY_ENC_OBS 0x0000006cU
+#define _reg_PHY_WR_SHIFT_OBS 0x0000006dU
+#define _reg_PHY_WRLVL_HARD0_DELAY_OBS 0x0000006eU
+#define _reg_PHY_WRLVL_HARD1_DELAY_OBS 0x0000006fU
+#define _reg_PHY_WRLVL_STATUS_OBS 0x00000070U
+#define _reg_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS 0x00000071U
+#define _reg_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS 0x00000072U
+#define _reg_PHY_WRLVL_ERROR_OBS 0x00000073U
+#define _reg_PHY_GTLVL_HARD0_DELAY_OBS 0x00000074U
+#define _reg_PHY_GTLVL_HARD1_DELAY_OBS 0x00000075U
+#define _reg_PHY_GTLVL_STATUS_OBS 0x00000076U
+#define _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS 0x00000077U
+#define _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS 0x00000078U
+#define _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS 0x00000079U
+#define _reg_PHY_RDLVL_STATUS_OBS 0x0000007aU
+#define _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS 0x0000007bU
+#define _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS 0x0000007cU
+#define _reg_PHY_WDQLVL_STATUS_OBS 0x0000007dU
+#define _reg_PHY_DDL_MODE 0x0000007eU
+#define _reg_PHY_DDL_TEST_OBS 0x0000007fU
+#define _reg_PHY_DDL_TEST_MSTR_DLY_OBS 0x00000080U
+#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD 0x00000081U
+#define _reg_PHY_LP4_WDQS_OE_EXTEND 0x00000082U
+#define _reg_SC_PHY_RX_CAL_START 0x00000083U
+#define _reg_PHY_RX_CAL_OVERRIDE 0x00000084U
+#define _reg_PHY_RX_CAL_SAMPLE_WAIT 0x00000085U
+#define _reg_PHY_RX_CAL_DQ0 0x00000086U
+#define _reg_PHY_RX_CAL_DQ1 0x00000087U
+#define _reg_PHY_RX_CAL_DQ2 0x00000088U
+#define _reg_PHY_RX_CAL_DQ3 0x00000089U
+#define _reg_PHY_RX_CAL_DQ4 0x0000008aU
+#define _reg_PHY_RX_CAL_DQ5 0x0000008bU
+#define _reg_PHY_RX_CAL_DQ6 0x0000008cU
+#define _reg_PHY_RX_CAL_DQ7 0x0000008dU
+#define _reg_PHY_RX_CAL_DM 0x0000008eU
+#define _reg_PHY_RX_CAL_DQS 0x0000008fU
+#define _reg_PHY_RX_CAL_FDBK 0x00000090U
+#define _reg_PHY_RX_CAL_OBS 0x00000091U
+#define _reg_PHY_RX_CAL_LOCK_OBS 0x00000092U
+#define _reg_PHY_RX_CAL_DISABLE 0x00000093U
+#define _reg_PHY_CLK_WRDQ0_SLAVE_DELAY 0x00000094U
+#define _reg_PHY_CLK_WRDQ1_SLAVE_DELAY 0x00000095U
+#define _reg_PHY_CLK_WRDQ2_SLAVE_DELAY 0x00000096U
+#define _reg_PHY_CLK_WRDQ3_SLAVE_DELAY 0x00000097U
+#define _reg_PHY_CLK_WRDQ4_SLAVE_DELAY 0x00000098U
+#define _reg_PHY_CLK_WRDQ5_SLAVE_DELAY 0x00000099U
+#define _reg_PHY_CLK_WRDQ6_SLAVE_DELAY 0x0000009aU
+#define _reg_PHY_CLK_WRDQ7_SLAVE_DELAY 0x0000009bU
+#define _reg_PHY_CLK_WRDM_SLAVE_DELAY 0x0000009cU
+#define _reg_PHY_CLK_WRDQS_SLAVE_DELAY 0x0000009dU
+#define _reg_PHY_WRLVL_THRESHOLD_ADJUST 0x0000009eU
+#define _reg_PHY_RDDQ0_SLAVE_DELAY 0x0000009fU
+#define _reg_PHY_RDDQ1_SLAVE_DELAY 0x000000a0U
+#define _reg_PHY_RDDQ2_SLAVE_DELAY 0x000000a1U
+#define _reg_PHY_RDDQ3_SLAVE_DELAY 0x000000a2U
+#define _reg_PHY_RDDQ4_SLAVE_DELAY 0x000000a3U
+#define _reg_PHY_RDDQ5_SLAVE_DELAY 0x000000a4U
+#define _reg_PHY_RDDQ6_SLAVE_DELAY 0x000000a5U
+#define _reg_PHY_RDDQ7_SLAVE_DELAY 0x000000a6U
+#define _reg_PHY_RDDM_SLAVE_DELAY 0x000000a7U
+#define _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY 0x000000a8U
+#define _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY 0x000000a9U
+#define _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY 0x000000aaU
+#define _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY 0x000000abU
+#define _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY 0x000000acU
+#define _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY 0x000000adU
+#define _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY 0x000000aeU
+#define _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY 0x000000afU
+#define _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY 0x000000b0U
+#define _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY 0x000000b1U
+#define _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY 0x000000b2U
+#define _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY 0x000000b3U
+#define _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY 0x000000b4U
+#define _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY 0x000000b5U
+#define _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY 0x000000b6U
+#define _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY 0x000000b7U
+#define _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY 0x000000b8U
+#define _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY 0x000000b9U
+#define _reg_PHY_RDDQS_GATE_SLAVE_DELAY 0x000000baU
+#define _reg_PHY_RDDQS_LATENCY_ADJUST 0x000000bbU
+#define _reg_PHY_WRITE_PATH_LAT_ADD 0x000000bcU
+#define _reg_PHY_WRLVL_DELAY_EARLY_THRESHOLD 0x000000bdU
+#define _reg_PHY_WRLVL_DELAY_PERIOD_THRESHOLD 0x000000beU
+#define _reg_PHY_WRLVL_EARLY_FORCE_ZERO 0x000000bfU
+#define _reg_PHY_GTLVL_RDDQS_SLV_DLY_START 0x000000c0U
+#define _reg_PHY_GTLVL_LAT_ADJ_START 0x000000c1U
+#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_START 0x000000c2U
+#define _reg_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START 0x000000c3U
+#define _reg_PHY_FDBK_PWR_CTRL 0x000000c4U
+#define _reg_PHY_DQ_OE_TIMING 0x000000c5U
+#define _reg_PHY_DQ_TSEL_RD_TIMING 0x000000c6U
+#define _reg_PHY_DQ_TSEL_WR_TIMING 0x000000c7U
+#define _reg_PHY_DQS_OE_TIMING 0x000000c8U
+#define _reg_PHY_DQS_TSEL_RD_TIMING 0x000000c9U
+#define _reg_PHY_DQS_OE_RD_TIMING 0x000000caU
+#define _reg_PHY_DQS_TSEL_WR_TIMING 0x000000cbU
+#define _reg_PHY_PER_CS_TRAINING_EN 0x000000ccU
+#define _reg_PHY_DQ_IE_TIMING 0x000000cdU
+#define _reg_PHY_DQS_IE_TIMING 0x000000ceU
+#define _reg_PHY_RDDATA_EN_IE_DLY 0x000000cfU
+#define _reg_PHY_IE_MODE 0x000000d0U
+#define _reg_PHY_RDDATA_EN_DLY 0x000000d1U
+#define _reg_PHY_RDDATA_EN_TSEL_DLY 0x000000d2U
+#define _reg_PHY_RDDATA_EN_OE_DLY 0x000000d3U
+#define _reg_PHY_SW_MASTER_MODE 0x000000d4U
+#define _reg_PHY_MASTER_DELAY_START 0x000000d5U
+#define _reg_PHY_MASTER_DELAY_STEP 0x000000d6U
+#define _reg_PHY_MASTER_DELAY_WAIT 0x000000d7U
+#define _reg_PHY_MASTER_DELAY_HALF_MEASURE 0x000000d8U
+#define _reg_PHY_RPTR_UPDATE 0x000000d9U
+#define _reg_PHY_WRLVL_DLY_STEP 0x000000daU
+#define _reg_PHY_WRLVL_RESP_WAIT_CNT 0x000000dbU
+#define _reg_PHY_GTLVL_DLY_STEP 0x000000dcU
+#define _reg_PHY_GTLVL_RESP_WAIT_CNT 0x000000ddU
+#define _reg_PHY_GTLVL_BACK_STEP 0x000000deU
+#define _reg_PHY_GTLVL_FINAL_STEP 0x000000dfU
+#define _reg_PHY_WDQLVL_DLY_STEP 0x000000e0U
+#define _reg_PHY_TOGGLE_PRE_SUPPORT 0x000000e1U
+#define _reg_PHY_RDLVL_DLY_STEP 0x000000e2U
+#define _reg_PHY_WRPATH_GATE_DISABLE 0x000000e3U
+#define _reg_PHY_WRPATH_GATE_TIMING 0x000000e4U
+#define _reg_PHY_ADR0_SW_WRADDR_SHIFT 0x000000e5U
+#define _reg_PHY_ADR1_SW_WRADDR_SHIFT 0x000000e6U
+#define _reg_PHY_ADR2_SW_WRADDR_SHIFT 0x000000e7U
+#define _reg_PHY_ADR3_SW_WRADDR_SHIFT 0x000000e8U
+#define _reg_PHY_ADR4_SW_WRADDR_SHIFT 0x000000e9U
+#define _reg_PHY_ADR5_SW_WRADDR_SHIFT 0x000000eaU
+#define _reg_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY 0x000000ebU
+#define _reg_PHY_ADR_CLK_BYPASS_OVERRIDE 0x000000ecU
+#define _reg_SC_PHY_ADR_MANUAL_CLEAR 0x000000edU
+#define _reg_PHY_ADR_LPBK_RESULT_OBS 0x000000eeU
+#define _reg_PHY_ADR_LPBK_ERROR_COUNT_OBS 0x000000efU
+#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT 0x000000f0U
+#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS 0x000000f1U
+#define _reg_PHY_ADR_BASE_SLV_DLY_ENC_OBS 0x000000f2U
+#define _reg_PHY_ADR_ADDER_SLV_DLY_ENC_OBS 0x000000f3U
+#define _reg_PHY_ADR_SLAVE_LOOP_CNT_UPDATE 0x000000f4U
+#define _reg_PHY_ADR_SLV_DLY_ENC_OBS_SELECT 0x000000f5U
+#define _reg_SC_PHY_ADR_SNAP_OBS_REGS 0x000000f6U
+#define _reg_PHY_ADR_TSEL_ENABLE 0x000000f7U
+#define _reg_PHY_ADR_LPBK_CONTROL 0x000000f8U
+#define _reg_PHY_ADR_PRBS_PATTERN_START 0x000000f9U
+#define _reg_PHY_ADR_PRBS_PATTERN_MASK 0x000000faU
+#define _reg_PHY_ADR_PWR_RDC_DISABLE 0x000000fbU
+#define _reg_PHY_ADR_TYPE 0x000000fcU
+#define _reg_PHY_ADR_WRADDR_SHIFT_OBS 0x000000fdU
+#define _reg_PHY_ADR_IE_MODE 0x000000feU
+#define _reg_PHY_ADR_DDL_MODE 0x000000ffU
+#define _reg_PHY_ADR_DDL_TEST_OBS 0x00000100U
+#define _reg_PHY_ADR_DDL_TEST_MSTR_DLY_OBS 0x00000101U
+#define _reg_PHY_ADR_CALVL_START 0x00000102U
+#define _reg_PHY_ADR_CALVL_COARSE_DLY 0x00000103U
+#define _reg_PHY_ADR_CALVL_QTR 0x00000104U
+#define _reg_PHY_ADR_CALVL_SWIZZLE0 0x00000105U
+#define _reg_PHY_ADR_CALVL_SWIZZLE1 0x00000106U
+#define _reg_PHY_ADR_CALVL_SWIZZLE0_0 0x00000107U
+#define _reg_PHY_ADR_CALVL_SWIZZLE1_0 0x00000108U
+#define _reg_PHY_ADR_CALVL_SWIZZLE0_1 0x00000109U
+#define _reg_PHY_ADR_CALVL_SWIZZLE1_1 0x0000010aU
+#define _reg_PHY_ADR_CALVL_DEVICE_MAP 0x0000010bU
+#define _reg_PHY_ADR_CALVL_RANK_CTRL 0x0000010cU
+#define _reg_PHY_ADR_CALVL_NUM_PATTERNS 0x0000010dU
+#define _reg_PHY_ADR_CALVL_CAPTURE_CNT 0x0000010eU
+#define _reg_PHY_ADR_CALVL_RESP_WAIT_CNT 0x0000010fU
+#define _reg_PHY_ADR_CALVL_DEBUG_MODE 0x00000110U
+#define _reg_SC_PHY_ADR_CALVL_DEBUG_CONT 0x00000111U
+#define _reg_SC_PHY_ADR_CALVL_ERROR_CLR 0x00000112U
+#define _reg_PHY_ADR_CALVL_OBS_SELECT 0x00000113U
+#define _reg_PHY_ADR_CALVL_OBS0 0x00000114U
+#define _reg_PHY_ADR_CALVL_OBS1 0x00000115U
+#define _reg_PHY_ADR_CALVL_RESULT 0x00000116U
+#define _reg_PHY_ADR_CALVL_FG_0 0x00000117U
+#define _reg_PHY_ADR_CALVL_BG_0 0x00000118U
+#define _reg_PHY_ADR_CALVL_FG_1 0x00000119U
+#define _reg_PHY_ADR_CALVL_BG_1 0x0000011aU
+#define _reg_PHY_ADR_CALVL_FG_2 0x0000011bU
+#define _reg_PHY_ADR_CALVL_BG_2 0x0000011cU
+#define _reg_PHY_ADR_CALVL_FG_3 0x0000011dU
+#define _reg_PHY_ADR_CALVL_BG_3 0x0000011eU
+#define _reg_PHY_ADR_ADDR_SEL 0x0000011fU
+#define _reg_PHY_ADR_LP4_BOOT_SLV_DELAY 0x00000120U
+#define _reg_PHY_ADR_BIT_MASK 0x00000121U
+#define _reg_PHY_ADR_SEG_MASK 0x00000122U
+#define _reg_PHY_ADR_CALVL_TRAIN_MASK 0x00000123U
+#define _reg_PHY_ADR_CSLVL_TRAIN_MASK 0x00000124U
+#define _reg_PHY_ADR_SW_TXIO_CTRL 0x00000125U
+#define _reg_PHY_ADR_TSEL_SELECT 0x00000126U
+#define _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY 0x00000127U
+#define _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY 0x00000128U
+#define _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY 0x00000129U
+#define _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY 0x0000012aU
+#define _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY 0x0000012bU
+#define _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY 0x0000012cU
+#define _reg_PHY_ADR_SW_MASTER_MODE 0x0000012dU
+#define _reg_PHY_ADR_MASTER_DELAY_START 0x0000012eU
+#define _reg_PHY_ADR_MASTER_DELAY_STEP 0x0000012fU
+#define _reg_PHY_ADR_MASTER_DELAY_WAIT 0x00000130U
+#define _reg_PHY_ADR_MASTER_DELAY_HALF_MEASURE 0x00000131U
+#define _reg_PHY_ADR_CALVL_DLY_STEP 0x00000132U
+#define _reg_PHY_FREQ_SEL 0x00000133U
+#define _reg_PHY_FREQ_SEL_FROM_REGIF 0x00000134U
+#define _reg_PHY_FREQ_SEL_MULTICAST_EN 0x00000135U
+#define _reg_PHY_FREQ_SEL_INDEX 0x00000136U
+#define _reg_PHY_SW_GRP_SHIFT_0 0x00000137U
+#define _reg_PHY_SW_GRP_SHIFT_1 0x00000138U
+#define _reg_PHY_SW_GRP_SHIFT_2 0x00000139U
+#define _reg_PHY_SW_GRP_SHIFT_3 0x0000013aU
+#define _reg_PHY_GRP_BYPASS_SLAVE_DELAY 0x0000013bU
+#define _reg_PHY_SW_GRP_BYPASS_SHIFT 0x0000013cU
+#define _reg_PHY_GRP_BYPASS_OVERRIDE 0x0000013dU
+#define _reg_SC_PHY_MANUAL_UPDATE 0x0000013eU
+#define _reg_SC_PHY_MANUAL_UPDATE_PHYUPD_ENABLE 0x0000013fU
+#define _reg_PHY_LP4_BOOT_DISABLE 0x00000140U
+#define _reg_PHY_CSLVL_ENABLE 0x00000141U
+#define _reg_PHY_CSLVL_CS_MAP 0x00000142U
+#define _reg_PHY_CSLVL_START 0x00000143U
+#define _reg_PHY_CSLVL_QTR 0x00000144U
+#define _reg_PHY_CSLVL_COARSE_CHK 0x00000145U
+#define _reg_PHY_CSLVL_CAPTURE_CNT 0x00000146U
+#define _reg_PHY_CSLVL_COARSE_DLY 0x00000147U
+#define _reg_PHY_CSLVL_COARSE_CAPTURE_CNT 0x00000148U
+#define _reg_PHY_CSLVL_DEBUG_MODE 0x00000149U
+#define _reg_SC_PHY_CSLVL_DEBUG_CONT 0x0000014aU
+#define _reg_SC_PHY_CSLVL_ERROR_CLR 0x0000014bU
+#define _reg_PHY_CSLVL_OBS0 0x0000014cU
+#define _reg_PHY_CSLVL_OBS1 0x0000014dU
+#define _reg_PHY_CALVL_CS_MAP 0x0000014eU
+#define _reg_PHY_GRP_SLV_DLY_ENC_OBS_SELECT 0x0000014fU
+#define _reg_PHY_GRP_SHIFT_OBS_SELECT 0x00000150U
+#define _reg_PHY_GRP_SLV_DLY_ENC_OBS 0x00000151U
+#define _reg_PHY_GRP_SHIFT_OBS 0x00000152U
+#define _reg_PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE 0x00000153U
+#define _reg_PHY_ADRCTL_SNAP_OBS_REGS 0x00000154U
+#define _reg_PHY_DFI_PHYUPD_TYPE 0x00000155U
+#define _reg_PHY_ADRCTL_LPDDR 0x00000156U
+#define _reg_PHY_LP4_ACTIVE 0x00000157U
+#define _reg_PHY_LPDDR3_CS 0x00000158U
+#define _reg_PHY_CALVL_RESULT_MASK 0x00000159U
+#define _reg_SC_PHY_UPDATE_CLK_CAL_VALUES 0x0000015aU
+#define _reg_PHY_SW_TXIO_CTRL_0 0x0000015bU
+#define _reg_PHY_SW_TXIO_CTRL_1 0x0000015cU
+#define _reg_PHY_SW_TXIO_CTRL_2 0x0000015dU
+#define _reg_PHY_SW_TXIO_CTRL_3 0x0000015eU
+#define _reg_PHY_MEMCLK_SW_TXIO_CTRL 0x0000015fU
+#define _reg_PHY_CA_SW_TXPWR_CTRL 0x00000160U
+#define _reg_PHY_MEMCLK_SW_TXPWR_CTRL 0x00000161U
+#define _reg_PHY_USER_DEF_REG_AC_0 0x00000162U
+#define _reg_PHY_USER_DEF_REG_AC_1 0x00000163U
+#define _reg_PHY_USER_DEF_REG_AC_2 0x00000164U
+#define _reg_PHY_USER_DEF_REG_AC_3 0x00000165U
+#define _reg_PHY_UPDATE_CLK_CAL_VALUES 0x00000166U
+#define _reg_PHY_CONTINUOUS_CLK_CAL_UPDATE 0x00000167U
+#define _reg_PHY_PLL_CTRL 0x00000168U
+#define _reg_PHY_PLL_CTRL_TOP 0x00000169U
+#define _reg_PHY_PLL_CTRL_CA 0x0000016aU
+#define _reg_PHY_PLL_BYPASS 0x0000016bU
+#define _reg_PHY_LOW_FREQ_SEL 0x0000016cU
+#define _reg_PHY_PAD_VREF_CTRL_DQ_0 0x0000016dU
+#define _reg_PHY_PAD_VREF_CTRL_DQ_1 0x0000016eU
+#define _reg_PHY_PAD_VREF_CTRL_DQ_2 0x0000016fU
+#define _reg_PHY_PAD_VREF_CTRL_DQ_3 0x00000170U
+#define _reg_PHY_PAD_VREF_CTRL_AC 0x00000171U
+#define _reg_PHY_CSLVL_DLY_STEP 0x00000172U
+#define _reg_PHY_SET_DFI_INPUT_0 0x00000173U
+#define _reg_PHY_SET_DFI_INPUT_1 0x00000174U
+#define _reg_PHY_SET_DFI_INPUT_2 0x00000175U
+#define _reg_PHY_SET_DFI_INPUT_3 0x00000176U
+#define _reg_PHY_GRP_SLAVE_DELAY_0 0x00000177U
+#define _reg_PHY_GRP_SLAVE_DELAY_1 0x00000178U
+#define _reg_PHY_GRP_SLAVE_DELAY_2 0x00000179U
+#define _reg_PHY_GRP_SLAVE_DELAY_3 0x0000017aU
+#define _reg_PHY_CS_ACS_ALLOCATION_0 0x0000017bU
+#define _reg_PHY_CS_ACS_ALLOCATION_1 0x0000017cU
+#define _reg_PHY_CS_ACS_ALLOCATION_2 0x0000017dU
+#define _reg_PHY_CS_ACS_ALLOCATION_3 0x0000017eU
+#define _reg_PHY_LP4_BOOT_PLL_CTRL 0x0000017fU
+#define _reg_PHY_LP4_BOOT_PLL_CTRL_CA 0x00000180U
+#define _reg_PHY_LP4_BOOT_TOP_PLL_CTRL 0x00000181U
+#define _reg_PHY_PLL_CTRL_OVERRIDE 0x00000182U
+#define _reg_PHY_PLL_WAIT 0x00000183U
+#define _reg_PHY_PLL_WAIT_TOP 0x00000184U
+#define _reg_PHY_PLL_OBS_0 0x00000185U
+#define _reg_PHY_PLL_OBS_1 0x00000186U
+#define _reg_PHY_PLL_OBS_2 0x00000187U
+#define _reg_PHY_PLL_OBS_3 0x00000188U
+#define _reg_PHY_PLL_OBS_4 0x00000189U
+#define _reg_PHY_PLL_TESTOUT_SEL 0x0000018aU
+#define _reg_PHY_TCKSRE_WAIT 0x0000018bU
+#define _reg_PHY_LP4_BOOT_LOW_FREQ_SEL 0x0000018cU
+#define _reg_PHY_LP_WAKEUP 0x0000018dU
+#define _reg_PHY_LS_IDLE_EN 0x0000018eU
+#define _reg_PHY_LP_CTRLUPD_CNTR_CFG 0x0000018fU
+#define _reg_PHY_TDFI_PHY_WRDELAY 0x00000190U
+#define _reg_PHY_PAD_FDBK_DRIVE 0x00000191U
+#define _reg_PHY_PAD_DATA_DRIVE 0x00000192U
+#define _reg_PHY_PAD_DQS_DRIVE 0x00000193U
+#define _reg_PHY_PAD_ADDR_DRIVE 0x00000194U
+#define _reg_PHY_PAD_CLK_DRIVE 0x00000195U
+#define _reg_PHY_PAD_FDBK_TERM 0x00000196U
+#define _reg_PHY_PAD_DATA_TERM 0x00000197U
+#define _reg_PHY_PAD_DQS_TERM 0x00000198U
+#define _reg_PHY_PAD_ADDR_TERM 0x00000199U
+#define _reg_PHY_PAD_CLK_TERM 0x0000019aU
+#define _reg_PHY_PAD_CKE_DRIVE 0x0000019bU
+#define _reg_PHY_PAD_CKE_TERM 0x0000019cU
+#define _reg_PHY_PAD_RST_DRIVE 0x0000019dU
+#define _reg_PHY_PAD_RST_TERM 0x0000019eU
+#define _reg_PHY_PAD_CS_DRIVE 0x0000019fU
+#define _reg_PHY_PAD_CS_TERM 0x000001a0U
+#define _reg_PHY_PAD_ODT_DRIVE 0x000001a1U
+#define _reg_PHY_PAD_ODT_TERM 0x000001a2U
+#define _reg_PHY_ADRCTL_RX_CAL 0x000001a3U
+#define _reg_PHY_ADRCTL_LP3_RX_CAL 0x000001a4U
+#define _reg_PHY_TST_CLK_PAD_CTRL 0x000001a5U
+#define _reg_PHY_TST_CLK_PAD_CTRL2 0x000001a6U
+#define _reg_PHY_CAL_MODE_0 0x000001a7U
+#define _reg_PHY_CAL_CLEAR_0 0x000001a8U
+#define _reg_PHY_CAL_START_0 0x000001a9U
+#define _reg_PHY_CAL_INTERVAL_COUNT_0 0x000001aaU
+#define _reg_PHY_CAL_SAMPLE_WAIT_0 0x000001abU
+#define _reg_PHY_LP4_BOOT_CAL_CLK_SELECT_0 0x000001acU
+#define _reg_PHY_CAL_CLK_SELECT_0 0x000001adU
+#define _reg_PHY_CAL_RESULT_OBS_0 0x000001aeU
+#define _reg_PHY_CAL_RESULT2_OBS_0 0x000001afU
+#define _reg_PHY_CAL_CPTR_CNT_0 0x000001b0U
+#define _reg_PHY_CAL_SETTLING_PRD_0 0x000001b1U
+#define _reg_PHY_CAL_PU_FINE_ADJ_0 0x000001b2U
+#define _reg_PHY_CAL_PD_FINE_ADJ_0 0x000001b3U
+#define _reg_PHY_CAL_RCV_FINE_ADJ_0 0x000001b4U
+#define _reg_PHY_CAL_DBG_CFG_0 0x000001b5U
+#define _reg_SC_PHY_PAD_DBG_CONT_0 0x000001b6U
+#define _reg_PHY_CAL_RESULT3_OBS_0 0x000001b7U
+#define _reg_PHY_ADRCTL_PVT_MAP_0 0x000001b8U
+#define _reg_PHY_CAL_SLOPE_ADJ_0 0x000001b9U
+#define _reg_PHY_CAL_SLOPE_ADJ_PASS2_0 0x000001baU
+#define _reg_PHY_CAL_TWO_PASS_CFG_0 0x000001bbU
+#define _reg_PHY_CAL_SW_CAL_CFG_0 0x000001bcU
+#define _reg_PHY_CAL_RANGE_MIN_0 0x000001bdU
+#define _reg_PHY_CAL_RANGE_MAX_0 0x000001beU
+#define _reg_PHY_PAD_ATB_CTRL 0x000001bfU
+#define _reg_PHY_ADRCTL_MANUAL_UPDATE 0x000001c0U
+#define _reg_PHY_AC_LPBK_ERR_CLEAR 0x000001c1U
+#define _reg_PHY_AC_LPBK_OBS_SELECT 0x000001c2U
+#define _reg_PHY_AC_LPBK_ENABLE 0x000001c3U
+#define _reg_PHY_AC_LPBK_CONTROL 0x000001c4U
+#define _reg_PHY_AC_PRBS_PATTERN_START 0x000001c5U
+#define _reg_PHY_AC_PRBS_PATTERN_MASK 0x000001c6U
+#define _reg_PHY_AC_LPBK_RESULT_OBS 0x000001c7U
+#define _reg_PHY_AC_CLK_LPBK_OBS_SELECT 0x000001c8U
+#define _reg_PHY_AC_CLK_LPBK_ENABLE 0x000001c9U
+#define _reg_PHY_AC_CLK_LPBK_CONTROL 0x000001caU
+#define _reg_PHY_AC_CLK_LPBK_RESULT_OBS 0x000001cbU
+#define _reg_PHY_AC_PWR_RDC_DISABLE 0x000001ccU
+#define _reg_PHY_DATA_BYTE_ORDER_SEL 0x000001cdU
+#define _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH 0x000001ceU
+#define _reg_PHY_LPDDR4_CONNECT 0x000001cfU
+#define _reg_PHY_CALVL_DEVICE_MAP 0x000001d0U
+#define _reg_PHY_ADR_DISABLE 0x000001d1U
+#define _reg_PHY_ADRCTL_MSTR_DLY_ENC_SEL 0x000001d2U
+#define _reg_PHY_CS_DLY_UPT_PER_AC_SLICE 0x000001d3U
+#define _reg_PHY_DDL_AC_ENABLE 0x000001d4U
+#define _reg_PHY_DDL_AC_MODE 0x000001d5U
+#define _reg_PHY_PAD_BACKGROUND_CAL 0x000001d6U
+#define _reg_PHY_INIT_UPDATE_CONFIG 0x000001d7U
+#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD_AC 0x000001d8U
+#define _reg_PHY_DLL_RST_EN 0x000001d9U
+#define _reg_PHY_AC_INIT_COMPLETE_OBS 0x000001daU
+#define _reg_PHY_DS_INIT_COMPLETE_OBS 0x000001dbU
+#define _reg_PHY_UPDATE_MASK 0x000001dcU
+#define _reg_PHY_PLL_SWITCH_CNT 0x000001ddU
+#define _reg_PI_START 0x000001deU
+#define _reg_PI_DRAM_CLASS 0x000001dfU
+#define _reg_PI_VERSION 0x000001e0U
+#define _reg_PI_NORMAL_LVL_SEQ 0x000001e1U
+#define _reg_PI_INIT_LVL_EN 0x000001e2U
+#define _reg_PI_NOTCARE_PHYUPD 0x000001e3U
+#define _reg_PI_ONBUS_MBIST 0x000001e4U
+#define _reg_PI_TCMD_GAP 0x000001e5U
+#define _reg_PI_MASTER_ACK_DURATION_MIN 0x000001e6U
+#define _reg_PI_DFI_VERSION 0x000001e7U
+#define _reg_PI_TDFI_PHYMSTR_TYPE0 0x000001e8U
+#define _reg_PI_TDFI_PHYMSTR_TYPE1 0x000001e9U
+#define _reg_PI_TDFI_PHYMSTR_TYPE2 0x000001eaU
+#define _reg_PI_TDFI_PHYMSTR_TYPE3 0x000001ebU
+#define _reg_PI_DFI_PHYMSTR_TYPE 0x000001ecU
+#define _reg_PI_DFI_PHYMSTR_CS_STATE_R 0x000001edU
+#define _reg_PI_DFI_PHYMSTR_STATE_SEL_R 0x000001eeU
+#define _reg_PI_TDFI_PHYMSTR_MAX_F0 0x000001efU
+#define _reg_PI_TDFI_PHYMSTR_RESP_F0 0x000001f0U
+#define _reg_PI_TDFI_PHYMSTR_MAX_F1 0x000001f1U
+#define _reg_PI_TDFI_PHYMSTR_RESP_F1 0x000001f2U
+#define _reg_PI_TDFI_PHYMSTR_MAX_F2 0x000001f3U
+#define _reg_PI_TDFI_PHYMSTR_RESP_F2 0x000001f4U
+#define _reg_PI_TDFI_PHYUPD_RESP_F0 0x000001f5U
+#define _reg_PI_TDFI_PHYUPD_TYPE0_F0 0x000001f6U
+#define _reg_PI_TDFI_PHYUPD_TYPE1_F0 0x000001f7U
+#define _reg_PI_TDFI_PHYUPD_TYPE2_F0 0x000001f8U
+#define _reg_PI_TDFI_PHYUPD_TYPE3_F0 0x000001f9U
+#define _reg_PI_TDFI_PHYUPD_RESP_F1 0x000001faU
+#define _reg_PI_TDFI_PHYUPD_TYPE0_F1 0x000001fbU
+#define _reg_PI_TDFI_PHYUPD_TYPE1_F1 0x000001fcU
+#define _reg_PI_TDFI_PHYUPD_TYPE2_F1 0x000001fdU
+#define _reg_PI_TDFI_PHYUPD_TYPE3_F1 0x000001feU
+#define _reg_PI_TDFI_PHYUPD_RESP_F2 0x000001ffU
+#define _reg_PI_TDFI_PHYUPD_TYPE0_F2 0x00000200U
+#define _reg_PI_TDFI_PHYUPD_TYPE1_F2 0x00000201U
+#define _reg_PI_TDFI_PHYUPD_TYPE2_F2 0x00000202U
+#define _reg_PI_TDFI_PHYUPD_TYPE3_F2 0x00000203U
+#define _reg_PI_CONTROL_ERROR_STATUS 0x00000204U
+#define _reg_PI_EXIT_AFTER_INIT_CALVL 0x00000205U
+#define _reg_PI_FREQ_MAP 0x00000206U
+#define _reg_PI_INIT_WORK_FREQ 0x00000207U
+#define _reg_PI_INIT_DFS_CALVL_ONLY 0x00000208U
+#define _reg_PI_POWER_ON_SEQ_BYPASS_ARRAY 0x00000209U
+#define _reg_PI_POWER_ON_SEQ_END_ARRAY 0x0000020aU
+#define _reg_PI_SEQ1_PAT 0x0000020bU
+#define _reg_PI_SEQ1_PAT_MASK 0x0000020cU
+#define _reg_PI_SEQ2_PAT 0x0000020dU
+#define _reg_PI_SEQ2_PAT_MASK 0x0000020eU
+#define _reg_PI_SEQ3_PAT 0x0000020fU
+#define _reg_PI_SEQ3_PAT_MASK 0x00000210U
+#define _reg_PI_SEQ4_PAT 0x00000211U
+#define _reg_PI_SEQ4_PAT_MASK 0x00000212U
+#define _reg_PI_SEQ5_PAT 0x00000213U
+#define _reg_PI_SEQ5_PAT_MASK 0x00000214U
+#define _reg_PI_SEQ6_PAT 0x00000215U
+#define _reg_PI_SEQ6_PAT_MASK 0x00000216U
+#define _reg_PI_SEQ7_PAT 0x00000217U
+#define _reg_PI_SEQ7_PAT_MASK 0x00000218U
+#define _reg_PI_SEQ8_PAT 0x00000219U
+#define _reg_PI_SEQ8_PAT_MASK 0x0000021aU
+#define _reg_PI_WDT_DISABLE 0x0000021bU
+#define _reg_PI_SW_RST_N 0x0000021cU
+#define _reg_RESERVED_R0 0x0000021dU
+#define _reg_PI_CS_MAP 0x0000021eU
+#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F0 0x0000021fU
+#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F1 0x00000220U
+#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F2 0x00000221U
+#define _reg_PI_TMRR 0x00000222U
+#define _reg_PI_WRLAT_F0 0x00000223U
+#define _reg_PI_ADDITIVE_LAT_F0 0x00000224U
+#define _reg_PI_CASLAT_LIN_F0 0x00000225U
+#define _reg_PI_WRLAT_F1 0x00000226U
+#define _reg_PI_ADDITIVE_LAT_F1 0x00000227U
+#define _reg_PI_CASLAT_LIN_F1 0x00000228U
+#define _reg_PI_WRLAT_F2 0x00000229U
+#define _reg_PI_ADDITIVE_LAT_F2 0x0000022aU
+#define _reg_PI_CASLAT_LIN_F2 0x0000022bU
+#define _reg_PI_PREAMBLE_SUPPORT 0x0000022cU
+#define _reg_PI_AREFRESH 0x0000022dU
+#define _reg_PI_MCAREF_FORWARD_ONLY 0x0000022eU
+#define _reg_PI_TRFC_F0 0x0000022fU
+#define _reg_PI_TREF_F0 0x00000230U
+#define _reg_PI_TRFC_F1 0x00000231U
+#define _reg_PI_TREF_F1 0x00000232U
+#define _reg_PI_TRFC_F2 0x00000233U
+#define _reg_PI_TREF_F2 0x00000234U
+#define _reg_RESERVED_H3VER2 0x00000235U
+#define _reg_PI_TREF_INTERVAL 0x00000236U
+#define _reg_PI_FREQ_CHANGE_REG_COPY 0x00000237U
+#define _reg_PI_FREQ_SEL_FROM_REGIF 0x00000238U
+#define _reg_PI_SWLVL_LOAD 0x00000239U
+#define _reg_PI_SWLVL_OP_DONE 0x0000023aU
+#define _reg_PI_SW_WRLVL_RESP_0 0x0000023bU
+#define _reg_PI_SW_WRLVL_RESP_1 0x0000023cU
+#define _reg_PI_SW_WRLVL_RESP_2 0x0000023dU
+#define _reg_PI_SW_WRLVL_RESP_3 0x0000023eU
+#define _reg_PI_SW_RDLVL_RESP_0 0x0000023fU
+#define _reg_PI_SW_RDLVL_RESP_1 0x00000240U
+#define _reg_PI_SW_RDLVL_RESP_2 0x00000241U
+#define _reg_PI_SW_RDLVL_RESP_3 0x00000242U
+#define _reg_PI_SW_CALVL_RESP_0 0x00000243U
+#define _reg_PI_SW_LEVELING_MODE 0x00000244U
+#define _reg_PI_SWLVL_START 0x00000245U
+#define _reg_PI_SWLVL_EXIT 0x00000246U
+#define _reg_PI_SWLVL_WR_SLICE_0 0x00000247U
+#define _reg_PI_SWLVL_RD_SLICE_0 0x00000248U
+#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_0 0x00000249U
+#define _reg_PI_SW_WDQLVL_RESP_0 0x0000024aU
+#define _reg_PI_SWLVL_WR_SLICE_1 0x0000024bU
+#define _reg_PI_SWLVL_RD_SLICE_1 0x0000024cU
+#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_1 0x0000024dU
+#define _reg_PI_SW_WDQLVL_RESP_1 0x0000024eU
+#define _reg_PI_SWLVL_WR_SLICE_2 0x0000024fU
+#define _reg_PI_SWLVL_RD_SLICE_2 0x00000250U
+#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_2 0x00000251U
+#define _reg_PI_SW_WDQLVL_RESP_2 0x00000252U
+#define _reg_PI_SWLVL_WR_SLICE_3 0x00000253U
+#define _reg_PI_SWLVL_RD_SLICE_3 0x00000254U
+#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_3 0x00000255U
+#define _reg_PI_SW_WDQLVL_RESP_3 0x00000256U
+#define _reg_PI_SW_WDQLVL_VREF 0x00000257U
+#define _reg_PI_SWLVL_SM2_START 0x00000258U
+#define _reg_PI_SWLVL_SM2_WR 0x00000259U
+#define _reg_PI_SWLVL_SM2_RD 0x0000025aU
+#define _reg_PI_SEQUENTIAL_LVL_REQ 0x0000025bU
+#define _reg_PI_DFS_PERIOD_EN 0x0000025cU
+#define _reg_PI_SRE_PERIOD_EN 0x0000025dU
+#define _reg_PI_DFI40_POLARITY 0x0000025eU
+#define _reg_PI_16BIT_DRAM_CONNECT 0x0000025fU
+#define _reg_PI_TDFI_CTRL_DELAY_F0 0x00000260U
+#define _reg_PI_TDFI_CTRL_DELAY_F1 0x00000261U
+#define _reg_PI_TDFI_CTRL_DELAY_F2 0x00000262U
+#define _reg_PI_WRLVL_REQ 0x00000263U
+#define _reg_PI_WRLVL_CS 0x00000264U
+#define _reg_PI_WLDQSEN 0x00000265U
+#define _reg_PI_WLMRD 0x00000266U
+#define _reg_PI_WRLVL_EN_F0 0x00000267U
+#define _reg_PI_WRLVL_EN_F1 0x00000268U
+#define _reg_PI_WRLVL_EN_F2 0x00000269U
+#define _reg_PI_WRLVL_EN 0x0000026aU
+#define _reg_PI_WRLVL_INTERVAL 0x0000026bU
+#define _reg_PI_WRLVL_PERIODIC 0x0000026cU
+#define _reg_PI_WRLVL_ON_SREF_EXIT 0x0000026dU
+#define _reg_PI_WRLVL_DISABLE_DFS 0x0000026eU
+#define _reg_PI_WRLVL_RESP_MASK 0x0000026fU
+#define _reg_PI_WRLVL_ROTATE 0x00000270U
+#define _reg_PI_WRLVL_CS_MAP 0x00000271U
+#define _reg_PI_WRLVL_ERROR_STATUS 0x00000272U
+#define _reg_PI_TDFI_WRLVL_EN 0x00000273U
+#define _reg_PI_TDFI_WRLVL_WW_F0 0x00000274U
+#define _reg_PI_TDFI_WRLVL_WW_F1 0x00000275U
+#define _reg_PI_TDFI_WRLVL_WW_F2 0x00000276U
+#define _reg_PI_TDFI_WRLVL_WW 0x00000277U
+#define _reg_PI_TDFI_WRLVL_RESP 0x00000278U
+#define _reg_PI_TDFI_WRLVL_MAX 0x00000279U
+#define _reg_PI_WRLVL_STROBE_NUM 0x0000027aU
+#define _reg_PI_WRLVL_MRR_DQ_RETURN_HIZ 0x0000027bU
+#define _reg_PI_WRLVL_EN_DEASSERT_2_MRR 0x0000027cU
+#define _reg_PI_TODTL_2CMD_F0 0x0000027dU
+#define _reg_PI_ODT_EN_F0 0x0000027eU
+#define _reg_PI_TODTL_2CMD_F1 0x0000027fU
+#define _reg_PI_ODT_EN_F1 0x00000280U
+#define _reg_PI_TODTL_2CMD_F2 0x00000281U
+#define _reg_PI_ODT_EN_F2 0x00000282U
+#define _reg_PI_TODTH_WR 0x00000283U
+#define _reg_PI_TODTH_RD 0x00000284U
+#define _reg_PI_ODT_RD_MAP_CS0 0x00000285U
+#define _reg_PI_ODT_WR_MAP_CS0 0x00000286U
+#define _reg_PI_ODT_RD_MAP_CS1 0x00000287U
+#define _reg_PI_ODT_WR_MAP_CS1 0x00000288U
+#define _reg_PI_ODT_RD_MAP_CS2 0x00000289U
+#define _reg_PI_ODT_WR_MAP_CS2 0x0000028aU
+#define _reg_PI_ODT_RD_MAP_CS3 0x0000028bU
+#define _reg_PI_ODT_WR_MAP_CS3 0x0000028cU
+#define _reg_PI_EN_ODT_ASSERT_EXCEPT_RD 0x0000028dU
+#define _reg_PI_ODTLON_F0 0x0000028eU
+#define _reg_PI_TODTON_MIN_F0 0x0000028fU
+#define _reg_PI_ODTLON_F1 0x00000290U
+#define _reg_PI_TODTON_MIN_F1 0x00000291U
+#define _reg_PI_ODTLON_F2 0x00000292U
+#define _reg_PI_TODTON_MIN_F2 0x00000293U
+#define _reg_PI_WR_TO_ODTH_F0 0x00000294U
+#define _reg_PI_WR_TO_ODTH_F1 0x00000295U
+#define _reg_PI_WR_TO_ODTH_F2 0x00000296U
+#define _reg_PI_RD_TO_ODTH_F0 0x00000297U
+#define _reg_PI_RD_TO_ODTH_F1 0x00000298U
+#define _reg_PI_RD_TO_ODTH_F2 0x00000299U
+#define _reg_PI_ADDRESS_MIRRORING 0x0000029aU
+#define _reg_PI_RDLVL_REQ 0x0000029bU
+#define _reg_PI_RDLVL_GATE_REQ 0x0000029cU
+#define _reg_PI_RDLVL_CS 0x0000029dU
+#define _reg_PI_RDLVL_PAT_0 0x0000029eU
+#define _reg_PI_RDLVL_PAT_1 0x0000029fU
+#define _reg_PI_RDLVL_PAT_2 0x000002a0U
+#define _reg_PI_RDLVL_PAT_3 0x000002a1U
+#define _reg_PI_RDLVL_PAT_4 0x000002a2U
+#define _reg_PI_RDLVL_PAT_5 0x000002a3U
+#define _reg_PI_RDLVL_PAT_6 0x000002a4U
+#define _reg_PI_RDLVL_PAT_7 0x000002a5U
+#define _reg_PI_RDLVL_SEQ_EN 0x000002a6U
+#define _reg_PI_RDLVL_GATE_SEQ_EN 0x000002a7U
+#define _reg_PI_RDLVL_PERIODIC 0x000002a8U
+#define _reg_PI_RDLVL_ON_SREF_EXIT 0x000002a9U
+#define _reg_PI_RDLVL_DISABLE_DFS 0x000002aaU
+#define _reg_PI_RDLVL_GATE_PERIODIC 0x000002abU
+#define _reg_PI_RDLVL_GATE_ON_SREF_EXIT 0x000002acU
+#define _reg_PI_RDLVL_GATE_DISABLE_DFS 0x000002adU
+#define _reg_RESERVED_R1 0x000002aeU
+#define _reg_PI_RDLVL_ROTATE 0x000002afU
+#define _reg_PI_RDLVL_GATE_ROTATE 0x000002b0U
+#define _reg_PI_RDLVL_CS_MAP 0x000002b1U
+#define _reg_PI_RDLVL_GATE_CS_MAP 0x000002b2U
+#define _reg_PI_TDFI_RDLVL_RR 0x000002b3U
+#define _reg_PI_TDFI_RDLVL_RESP 0x000002b4U
+#define _reg_PI_RDLVL_RESP_MASK 0x000002b5U
+#define _reg_PI_TDFI_RDLVL_EN 0x000002b6U
+#define _reg_PI_RDLVL_EN_F0 0x000002b7U
+#define _reg_PI_RDLVL_GATE_EN_F0 0x000002b8U
+#define _reg_PI_RDLVL_EN_F1 0x000002b9U
+#define _reg_PI_RDLVL_GATE_EN_F1 0x000002baU
+#define _reg_PI_RDLVL_EN_F2 0x000002bbU
+#define _reg_PI_RDLVL_GATE_EN_F2 0x000002bcU
+#define _reg_PI_RDLVL_EN 0x000002bdU
+#define _reg_PI_RDLVL_GATE_EN 0x000002beU
+#define _reg_PI_TDFI_RDLVL_MAX 0x000002bfU
+#define _reg_PI_RDLVL_ERROR_STATUS 0x000002c0U
+#define _reg_PI_RDLVL_INTERVAL 0x000002c1U
+#define _reg_PI_RDLVL_GATE_INTERVAL 0x000002c2U
+#define _reg_PI_RDLVL_PATTERN_START 0x000002c3U
+#define _reg_PI_RDLVL_PATTERN_NUM 0x000002c4U
+#define _reg_PI_RDLVL_STROBE_NUM 0x000002c5U
+#define _reg_PI_RDLVL_GATE_STROBE_NUM 0x000002c6U
+#define _reg_PI_LPDDR4_RDLVL_PATTERN_8 0x000002c7U
+#define _reg_PI_LPDDR4_RDLVL_PATTERN_9 0x000002c8U
+#define _reg_PI_LPDDR4_RDLVL_PATTERN_10 0x000002c9U
+#define _reg_PI_LPDDR4_RDLVL_PATTERN_11 0x000002caU
+#define _reg_PI_RD_PREAMBLE_TRAINING_EN 0x000002cbU
+#define _reg_PI_REG_DIMM_ENABLE 0x000002ccU
+#define _reg_PI_RDLAT_ADJ_F0 0x000002cdU
+#define _reg_PI_RDLAT_ADJ_F1 0x000002ceU
+#define _reg_PI_RDLAT_ADJ_F2 0x000002cfU
+#define _reg_PI_TDFI_RDDATA_EN 0x000002d0U
+#define _reg_PI_WRLAT_ADJ_F0 0x000002d1U
+#define _reg_PI_WRLAT_ADJ_F1 0x000002d2U
+#define _reg_PI_WRLAT_ADJ_F2 0x000002d3U
+#define _reg_PI_TDFI_PHY_WRLAT 0x000002d4U
+#define _reg_PI_TDFI_WRCSLAT_F0 0x000002d5U
+#define _reg_PI_TDFI_WRCSLAT_F1 0x000002d6U
+#define _reg_PI_TDFI_WRCSLAT_F2 0x000002d7U
+#define _reg_PI_TDFI_RDCSLAT_F0 0x000002d8U
+#define _reg_PI_TDFI_RDCSLAT_F1 0x000002d9U
+#define _reg_PI_TDFI_RDCSLAT_F2 0x000002daU
+#define _reg_PI_TDFI_PHY_WRDATA_F0 0x000002dbU
+#define _reg_PI_TDFI_PHY_WRDATA_F1 0x000002dcU
+#define _reg_PI_TDFI_PHY_WRDATA_F2 0x000002ddU
+#define _reg_PI_TDFI_PHY_WRDATA 0x000002deU
+#define _reg_PI_CALVL_REQ 0x000002dfU
+#define _reg_PI_CALVL_CS 0x000002e0U
+#define _reg_RESERVED_R2 0x000002e1U
+#define _reg_RESERVED_R3 0x000002e2U
+#define _reg_PI_CALVL_SEQ_EN 0x000002e3U
+#define _reg_PI_CALVL_PERIODIC 0x000002e4U
+#define _reg_PI_CALVL_ON_SREF_EXIT 0x000002e5U
+#define _reg_PI_CALVL_DISABLE_DFS 0x000002e6U
+#define _reg_PI_CALVL_ROTATE 0x000002e7U
+#define _reg_PI_CALVL_CS_MAP 0x000002e8U
+#define _reg_PI_TDFI_CALVL_EN 0x000002e9U
+#define _reg_PI_TDFI_CALVL_CC_F0 0x000002eaU
+#define _reg_PI_TDFI_CALVL_CAPTURE_F0 0x000002ebU
+#define _reg_PI_TDFI_CALVL_CC_F1 0x000002ecU
+#define _reg_PI_TDFI_CALVL_CAPTURE_F1 0x000002edU
+#define _reg_PI_TDFI_CALVL_CC_F2 0x000002eeU
+#define _reg_PI_TDFI_CALVL_CAPTURE_F2 0x000002efU
+#define _reg_PI_TDFI_CALVL_RESP 0x000002f0U
+#define _reg_PI_TDFI_CALVL_MAX 0x000002f1U
+#define _reg_PI_CALVL_RESP_MASK 0x000002f2U
+#define _reg_PI_CALVL_EN_F0 0x000002f3U
+#define _reg_PI_CALVL_EN_F1 0x000002f4U
+#define _reg_PI_CALVL_EN_F2 0x000002f5U
+#define _reg_PI_CALVL_EN 0x000002f6U
+#define _reg_PI_CALVL_ERROR_STATUS 0x000002f7U
+#define _reg_PI_CALVL_INTERVAL 0x000002f8U
+#define _reg_PI_TCACKEL 0x000002f9U
+#define _reg_PI_TCAMRD 0x000002faU
+#define _reg_PI_TCACKEH 0x000002fbU
+#define _reg_PI_TMRZ_F0 0x000002fcU
+#define _reg_PI_TCAENT_F0 0x000002fdU
+#define _reg_PI_TMRZ_F1 0x000002feU
+#define _reg_PI_TCAENT_F1 0x000002ffU
+#define _reg_PI_TMRZ_F2 0x00000300U
+#define _reg_PI_TCAENT_F2 0x00000301U
+#define _reg_PI_TCAEXT 0x00000302U
+#define _reg_PI_CA_TRAIN_VREF_EN 0x00000303U
+#define _reg_PI_TDFI_CACSCA_F0 0x00000304U
+#define _reg_PI_TDFI_CASEL_F0 0x00000305U
+#define _reg_PI_TVREF_SHORT_F0 0x00000306U
+#define _reg_PI_TVREF_LONG_F0 0x00000307U
+#define _reg_PI_TDFI_CACSCA_F1 0x00000308U
+#define _reg_PI_TDFI_CASEL_F1 0x00000309U
+#define _reg_PI_TVREF_SHORT_F1 0x0000030aU
+#define _reg_PI_TVREF_LONG_F1 0x0000030bU
+#define _reg_PI_TDFI_CACSCA_F2 0x0000030cU
+#define _reg_PI_TDFI_CASEL_F2 0x0000030dU
+#define _reg_PI_TVREF_SHORT_F2 0x0000030eU
+#define _reg_PI_TVREF_LONG_F2 0x0000030fU
+#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F0 0x00000310U
+#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F0 0x00000311U
+#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F1 0x00000312U
+#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F1 0x00000313U
+#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F2 0x00000314U
+#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F2 0x00000315U
+#define _reg_PI_CALVL_VREF_INITIAL_START_POINT 0x00000316U
+#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT 0x00000317U
+#define _reg_PI_CALVL_VREF_INITIAL_STEPSIZE 0x00000318U
+#define _reg_PI_CALVL_VREF_NORMAL_STEPSIZE 0x00000319U
+#define _reg_PI_CALVL_VREF_DELTA_F0 0x0000031aU
+#define _reg_PI_CALVL_VREF_DELTA_F1 0x0000031bU
+#define _reg_PI_CALVL_VREF_DELTA_F2 0x0000031cU
+#define _reg_PI_CALVL_VREF_DELTA 0x0000031dU
+#define _reg_PI_TDFI_INIT_START_MIN 0x0000031eU
+#define _reg_PI_TDFI_INIT_COMPLETE_MIN 0x0000031fU
+#define _reg_PI_TDFI_CALVL_STROBE_F0 0x00000320U
+#define _reg_PI_TXP_F0 0x00000321U
+#define _reg_PI_TMRWCKEL_F0 0x00000322U
+#define _reg_PI_TCKELCK_F0 0x00000323U
+#define _reg_PI_TDFI_CALVL_STROBE_F1 0x00000324U
+#define _reg_PI_TXP_F1 0x00000325U
+#define _reg_PI_TMRWCKEL_F1 0x00000326U
+#define _reg_PI_TCKELCK_F1 0x00000327U
+#define _reg_PI_TDFI_CALVL_STROBE_F2 0x00000328U
+#define _reg_PI_TXP_F2 0x00000329U
+#define _reg_PI_TMRWCKEL_F2 0x0000032aU
+#define _reg_PI_TCKELCK_F2 0x0000032bU
+#define _reg_PI_TCKCKEH 0x0000032cU
+#define _reg_PI_CALVL_STROBE_NUM 0x0000032dU
+#define _reg_PI_SW_CA_TRAIN_VREF 0x0000032eU
+#define _reg_PI_TDFI_INIT_START_F0 0x0000032fU
+#define _reg_PI_TDFI_INIT_COMPLETE_F0 0x00000330U
+#define _reg_PI_TDFI_INIT_START_F1 0x00000331U
+#define _reg_PI_TDFI_INIT_COMPLETE_F1 0x00000332U
+#define _reg_PI_TDFI_INIT_START_F2 0x00000333U
+#define _reg_PI_TDFI_INIT_COMPLETE_F2 0x00000334U
+#define _reg_PI_CLKDISABLE_2_INIT_START 0x00000335U
+#define _reg_PI_INIT_STARTORCOMPLETE_2_CLKDISABLE 0x00000336U
+#define _reg_PI_DRAM_CLK_DISABLE_DEASSERT_SEL 0x00000337U
+#define _reg_PI_REFRESH_BETWEEN_SEGMENT_DISABLE 0x00000338U
+#define _reg_PI_TCKEHDQS_F0 0x00000339U
+#define _reg_PI_TCKEHDQS_F1 0x0000033aU
+#define _reg_PI_TCKEHDQS_F2 0x0000033bU
+#define _reg_PI_MC_DFS_PI_SET_VREF_ENABLE 0x0000033cU
+#define _reg_PI_WDQLVL_VREF_EN 0x0000033dU
+#define _reg_PI_WDQLVL_BST_NUM 0x0000033eU
+#define _reg_PI_TDFI_WDQLVL_WR_F0 0x0000033fU
+#define _reg_PI_TDFI_WDQLVL_WR_F1 0x00000340U
+#define _reg_PI_TDFI_WDQLVL_WR_F2 0x00000341U
+#define _reg_PI_TDFI_WDQLVL_WR 0x00000342U
+#define _reg_PI_TDFI_WDQLVL_RW 0x00000343U
+#define _reg_PI_WDQLVL_RESP_MASK 0x00000344U
+#define _reg_PI_WDQLVL_ROTATE 0x00000345U
+#define _reg_PI_WDQLVL_CS_MAP 0x00000346U
+#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F0 0x00000347U
+#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 0x00000348U
+#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1 0x00000349U
+#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 0x0000034aU
+#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F2 0x0000034bU
+#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 0x0000034cU
+#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT 0x0000034dU
+#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT 0x0000034eU
+#define _reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE 0x0000034fU
+#define _reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE 0x00000350U
+#define _reg_PI_WDQLVL_VREF_DELTA_F0 0x00000351U
+#define _reg_PI_WDQLVL_VREF_DELTA_F1 0x00000352U
+#define _reg_PI_WDQLVL_VREF_DELTA_F2 0x00000353U
+#define _reg_PI_WDQLVL_VREF_DELTA 0x00000354U
+#define _reg_PI_WDQLVL_PERIODIC 0x00000355U
+#define _reg_PI_WDQLVL_REQ 0x00000356U
+#define _reg_PI_WDQLVL_CS 0x00000357U
+#define _reg_PI_TDFI_WDQLVL_EN 0x00000358U
+#define _reg_PI_TDFI_WDQLVL_RESP 0x00000359U
+#define _reg_PI_TDFI_WDQLVL_MAX 0x0000035aU
+#define _reg_PI_WDQLVL_INTERVAL 0x0000035bU
+#define _reg_PI_WDQLVL_EN_F0 0x0000035cU
+#define _reg_PI_WDQLVL_EN_F1 0x0000035dU
+#define _reg_PI_WDQLVL_EN_F2 0x0000035eU
+#define _reg_PI_WDQLVL_EN 0x0000035fU
+#define _reg_PI_WDQLVL_ON_SREF_EXIT 0x00000360U
+#define _reg_PI_WDQLVL_DISABLE_DFS 0x00000361U
+#define _reg_PI_WDQLVL_ERROR_STATUS 0x00000362U
+#define _reg_PI_MR1_DATA_F0_0 0x00000363U
+#define _reg_PI_MR2_DATA_F0_0 0x00000364U
+#define _reg_PI_MR3_DATA_F0_0 0x00000365U
+#define _reg_PI_MR11_DATA_F0_0 0x00000366U
+#define _reg_PI_MR12_DATA_F0_0 0x00000367U
+#define _reg_PI_MR14_DATA_F0_0 0x00000368U
+#define _reg_PI_MR22_DATA_F0_0 0x00000369U
+#define _reg_PI_MR1_DATA_F1_0 0x0000036aU
+#define _reg_PI_MR2_DATA_F1_0 0x0000036bU
+#define _reg_PI_MR3_DATA_F1_0 0x0000036cU
+#define _reg_PI_MR11_DATA_F1_0 0x0000036dU
+#define _reg_PI_MR12_DATA_F1_0 0x0000036eU
+#define _reg_PI_MR14_DATA_F1_0 0x0000036fU
+#define _reg_PI_MR22_DATA_F1_0 0x00000370U
+#define _reg_PI_MR1_DATA_F2_0 0x00000371U
+#define _reg_PI_MR2_DATA_F2_0 0x00000372U
+#define _reg_PI_MR3_DATA_F2_0 0x00000373U
+#define _reg_PI_MR11_DATA_F2_0 0x00000374U
+#define _reg_PI_MR12_DATA_F2_0 0x00000375U
+#define _reg_PI_MR14_DATA_F2_0 0x00000376U
+#define _reg_PI_MR22_DATA_F2_0 0x00000377U
+#define _reg_PI_MR13_DATA_0 0x00000378U
+#define _reg_PI_MR1_DATA_F0_1 0x00000379U
+#define _reg_PI_MR2_DATA_F0_1 0x0000037aU
+#define _reg_PI_MR3_DATA_F0_1 0x0000037bU
+#define _reg_PI_MR11_DATA_F0_1 0x0000037cU
+#define _reg_PI_MR12_DATA_F0_1 0x0000037dU
+#define _reg_PI_MR14_DATA_F0_1 0x0000037eU
+#define _reg_PI_MR22_DATA_F0_1 0x0000037fU
+#define _reg_PI_MR1_DATA_F1_1 0x00000380U
+#define _reg_PI_MR2_DATA_F1_1 0x00000381U
+#define _reg_PI_MR3_DATA_F1_1 0x00000382U
+#define _reg_PI_MR11_DATA_F1_1 0x00000383U
+#define _reg_PI_MR12_DATA_F1_1 0x00000384U
+#define _reg_PI_MR14_DATA_F1_1 0x00000385U
+#define _reg_PI_MR22_DATA_F1_1 0x00000386U
+#define _reg_PI_MR1_DATA_F2_1 0x00000387U
+#define _reg_PI_MR2_DATA_F2_1 0x00000388U
+#define _reg_PI_MR3_DATA_F2_1 0x00000389U
+#define _reg_PI_MR11_DATA_F2_1 0x0000038aU
+#define _reg_PI_MR12_DATA_F2_1 0x0000038bU
+#define _reg_PI_MR14_DATA_F2_1 0x0000038cU
+#define _reg_PI_MR22_DATA_F2_1 0x0000038dU
+#define _reg_PI_MR13_DATA_1 0x0000038eU
+#define _reg_PI_MR1_DATA_F0_2 0x0000038fU
+#define _reg_PI_MR2_DATA_F0_2 0x00000390U
+#define _reg_PI_MR3_DATA_F0_2 0x00000391U
+#define _reg_PI_MR11_DATA_F0_2 0x00000392U
+#define _reg_PI_MR12_DATA_F0_2 0x00000393U
+#define _reg_PI_MR14_DATA_F0_2 0x00000394U
+#define _reg_PI_MR22_DATA_F0_2 0x00000395U
+#define _reg_PI_MR1_DATA_F1_2 0x00000396U
+#define _reg_PI_MR2_DATA_F1_2 0x00000397U
+#define _reg_PI_MR3_DATA_F1_2 0x00000398U
+#define _reg_PI_MR11_DATA_F1_2 0x00000399U
+#define _reg_PI_MR12_DATA_F1_2 0x0000039aU
+#define _reg_PI_MR14_DATA_F1_2 0x0000039bU
+#define _reg_PI_MR22_DATA_F1_2 0x0000039cU
+#define _reg_PI_MR1_DATA_F2_2 0x0000039dU
+#define _reg_PI_MR2_DATA_F2_2 0x0000039eU
+#define _reg_PI_MR3_DATA_F2_2 0x0000039fU
+#define _reg_PI_MR11_DATA_F2_2 0x000003a0U
+#define _reg_PI_MR12_DATA_F2_2 0x000003a1U
+#define _reg_PI_MR14_DATA_F2_2 0x000003a2U
+#define _reg_PI_MR22_DATA_F2_2 0x000003a3U
+#define _reg_PI_MR13_DATA_2 0x000003a4U
+#define _reg_PI_MR1_DATA_F0_3 0x000003a5U
+#define _reg_PI_MR2_DATA_F0_3 0x000003a6U
+#define _reg_PI_MR3_DATA_F0_3 0x000003a7U
+#define _reg_PI_MR11_DATA_F0_3 0x000003a8U
+#define _reg_PI_MR12_DATA_F0_3 0x000003a9U
+#define _reg_PI_MR14_DATA_F0_3 0x000003aaU
+#define _reg_PI_MR22_DATA_F0_3 0x000003abU
+#define _reg_PI_MR1_DATA_F1_3 0x000003acU
+#define _reg_PI_MR2_DATA_F1_3 0x000003adU
+#define _reg_PI_MR3_DATA_F1_3 0x000003aeU
+#define _reg_PI_MR11_DATA_F1_3 0x000003afU
+#define _reg_PI_MR12_DATA_F1_3 0x000003b0U
+#define _reg_PI_MR14_DATA_F1_3 0x000003b1U
+#define _reg_PI_MR22_DATA_F1_3 0x000003b2U
+#define _reg_PI_MR1_DATA_F2_3 0x000003b3U
+#define _reg_PI_MR2_DATA_F2_3 0x000003b4U
+#define _reg_PI_MR3_DATA_F2_3 0x000003b5U
+#define _reg_PI_MR11_DATA_F2_3 0x000003b6U
+#define _reg_PI_MR12_DATA_F2_3 0x000003b7U
+#define _reg_PI_MR14_DATA_F2_3 0x000003b8U
+#define _reg_PI_MR22_DATA_F2_3 0x000003b9U
+#define _reg_PI_MR13_DATA_3 0x000003baU
+#define _reg_PI_BANK_DIFF 0x000003bbU
+#define _reg_PI_ROW_DIFF 0x000003bcU
+#define _reg_PI_TFC_F0 0x000003bdU
+#define _reg_PI_TFC_F1 0x000003beU
+#define _reg_PI_TFC_F2 0x000003bfU
+#define _reg_PI_TCCD 0x000003c0U
+#define _reg_PI_TRTP_F0 0x000003c1U
+#define _reg_PI_TRP_F0 0x000003c2U
+#define _reg_PI_TRCD_F0 0x000003c3U
+#define _reg_PI_TWTR_F0 0x000003c4U
+#define _reg_PI_TWR_F0 0x000003c5U
+#define _reg_PI_TRAS_MAX_F0 0x000003c6U
+#define _reg_PI_TRAS_MIN_F0 0x000003c7U
+#define _reg_PI_TDQSCK_MAX_F0 0x000003c8U
+#define _reg_PI_TCCDMW_F0 0x000003c9U
+#define _reg_PI_TSR_F0 0x000003caU
+#define _reg_PI_TMRD_F0 0x000003cbU
+#define _reg_PI_TMRW_F0 0x000003ccU
+#define _reg_PI_TMOD_F0 0x000003cdU
+#define _reg_PI_TRTP_F1 0x000003ceU
+#define _reg_PI_TRP_F1 0x000003cfU
+#define _reg_PI_TRCD_F1 0x000003d0U
+#define _reg_PI_TWTR_F1 0x000003d1U
+#define _reg_PI_TWR_F1 0x000003d2U
+#define _reg_PI_TRAS_MAX_F1 0x000003d3U
+#define _reg_PI_TRAS_MIN_F1 0x000003d4U
+#define _reg_PI_TDQSCK_MAX_F1 0x000003d5U
+#define _reg_PI_TCCDMW_F1 0x000003d6U
+#define _reg_PI_TSR_F1 0x000003d7U
+#define _reg_PI_TMRD_F1 0x000003d8U
+#define _reg_PI_TMRW_F1 0x000003d9U
+#define _reg_PI_TMOD_F1 0x000003daU
+#define _reg_PI_TRTP_F2 0x000003dbU
+#define _reg_PI_TRP_F2 0x000003dcU
+#define _reg_PI_TRCD_F2 0x000003ddU
+#define _reg_PI_TWTR_F2 0x000003deU
+#define _reg_PI_TWR_F2 0x000003dfU
+#define _reg_PI_TRAS_MAX_F2 0x000003e0U
+#define _reg_PI_TRAS_MIN_F2 0x000003e1U
+#define _reg_PI_TDQSCK_MAX_F2 0x000003e2U
+#define _reg_PI_TCCDMW_F2 0x000003e3U
+#define _reg_PI_TSR_F2 0x000003e4U
+#define _reg_PI_TMRD_F2 0x000003e5U
+#define _reg_PI_TMRW_F2 0x000003e6U
+#define _reg_PI_TMOD_F2 0x000003e7U
+#define _reg_RESERVED_R4 0x000003e8U
+#define _reg_RESERVED_R5 0x000003e9U
+#define _reg_RESERVED_R6 0x000003eaU
+#define _reg_RESERVED_R7 0x000003ebU
+#define _reg_RESERVED_R8 0x000003ecU
+#define _reg_RESERVED_R9 0x000003edU
+#define _reg_RESERVED_R10 0x000003eeU
+#define _reg_RESERVED_R11 0x000003efU
+#define _reg_RESERVED_R12 0x000003f0U
+#define _reg_RESERVED_R13 0x000003f1U
+#define _reg_RESERVED_R14 0x000003f2U
+#define _reg_RESERVED_R15 0x000003f3U
+#define _reg_RESERVED_R16 0x000003f4U
+#define _reg_RESERVED_R17 0x000003f5U
+#define _reg_RESERVED_R18 0x000003f6U
+#define _reg_RESERVED_R19 0x000003f7U
+#define _reg_RESERVED_R20 0x000003f8U
+#define _reg_RESERVED_R21 0x000003f9U
+#define _reg_RESERVED_R22 0x000003faU
+#define _reg_RESERVED_R23 0x000003fbU
+#define _reg_PI_INT_STATUS 0x000003fcU
+#define _reg_PI_INT_ACK 0x000003fdU
+#define _reg_PI_INT_MASK 0x000003feU
+#define _reg_PI_BIST_EXP_DATA_P0 0x000003ffU
+#define _reg_PI_BIST_EXP_DATA_P1 0x00000400U
+#define _reg_PI_BIST_EXP_DATA_P2 0x00000401U
+#define _reg_PI_BIST_EXP_DATA_P3 0x00000402U
+#define _reg_PI_BIST_FAIL_DATA_P0 0x00000403U
+#define _reg_PI_BIST_FAIL_DATA_P1 0x00000404U
+#define _reg_PI_BIST_FAIL_DATA_P2 0x00000405U
+#define _reg_PI_BIST_FAIL_DATA_P3 0x00000406U
+#define _reg_PI_BIST_FAIL_ADDR_P0 0x00000407U
+#define _reg_PI_BIST_FAIL_ADDR_P1 0x00000408U
+#define _reg_PI_BSTLEN 0x00000409U
+#define _reg_PI_LONG_COUNT_MASK 0x0000040aU
+#define _reg_PI_CMD_SWAP_EN 0x0000040bU
+#define _reg_PI_CKE_MUX_0 0x0000040cU
+#define _reg_PI_CKE_MUX_1 0x0000040dU
+#define _reg_PI_CKE_MUX_2 0x0000040eU
+#define _reg_PI_CKE_MUX_3 0x0000040fU
+#define _reg_PI_CS_MUX_0 0x00000410U
+#define _reg_PI_CS_MUX_1 0x00000411U
+#define _reg_PI_CS_MUX_2 0x00000412U
+#define _reg_PI_CS_MUX_3 0x00000413U
+#define _reg_PI_RAS_N_MUX 0x00000414U
+#define _reg_PI_CAS_N_MUX 0x00000415U
+#define _reg_PI_WE_N_MUX 0x00000416U
+#define _reg_PI_BANK_MUX_0 0x00000417U
+#define _reg_PI_BANK_MUX_1 0x00000418U
+#define _reg_PI_BANK_MUX_2 0x00000419U
+#define _reg_PI_ODT_MUX_0 0x0000041aU
+#define _reg_PI_ODT_MUX_1 0x0000041bU
+#define _reg_PI_ODT_MUX_2 0x0000041cU
+#define _reg_PI_ODT_MUX_3 0x0000041dU
+#define _reg_PI_RESET_N_MUX_0 0x0000041eU
+#define _reg_PI_RESET_N_MUX_1 0x0000041fU
+#define _reg_PI_RESET_N_MUX_2 0x00000420U
+#define _reg_PI_RESET_N_MUX_3 0x00000421U
+#define _reg_PI_DATA_BYTE_SWAP_EN 0x00000422U
+#define _reg_PI_DATA_BYTE_SWAP_SLICE0 0x00000423U
+#define _reg_PI_DATA_BYTE_SWAP_SLICE1 0x00000424U
+#define _reg_PI_DATA_BYTE_SWAP_SLICE2 0x00000425U
+#define _reg_PI_DATA_BYTE_SWAP_SLICE3 0x00000426U
+#define _reg_PI_CTRLUPD_REQ_PER_AREF_EN 0x00000427U
+#define _reg_PI_TDFI_CTRLUPD_MIN 0x00000428U
+#define _reg_PI_TDFI_CTRLUPD_MAX_F0 0x00000429U
+#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F0 0x0000042aU
+#define _reg_PI_TDFI_CTRLUPD_MAX_F1 0x0000042bU
+#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F1 0x0000042cU
+#define _reg_PI_TDFI_CTRLUPD_MAX_F2 0x0000042dU
+#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F2 0x0000042eU
+#define _reg_PI_UPDATE_ERROR_STATUS 0x0000042fU
+#define _reg_PI_BIST_GO 0x00000430U
+#define _reg_PI_BIST_RESULT 0x00000431U
+#define _reg_PI_ADDR_SPACE 0x00000432U
+#define _reg_PI_BIST_DATA_CHECK 0x00000433U
+#define _reg_PI_BIST_ADDR_CHECK 0x00000434U
+#define _reg_PI_BIST_START_ADDRESS_P0 0x00000435U
+#define _reg_PI_BIST_START_ADDRESS_P1 0x00000436U
+#define _reg_PI_BIST_DATA_MASK_P0 0x00000437U
+#define _reg_PI_BIST_DATA_MASK_P1 0x00000438U
+#define _reg_PI_BIST_ERR_COUNT 0x00000439U
+#define _reg_PI_BIST_ERR_STOP 0x0000043aU
+#define _reg_PI_BIST_ADDR_MASK_0_P0 0x0000043bU
+#define _reg_PI_BIST_ADDR_MASK_0_P1 0x0000043cU
+#define _reg_PI_BIST_ADDR_MASK_1_P0 0x0000043dU
+#define _reg_PI_BIST_ADDR_MASK_1_P1 0x0000043eU
+#define _reg_PI_BIST_ADDR_MASK_2_P0 0x0000043fU
+#define _reg_PI_BIST_ADDR_MASK_2_P1 0x00000440U
+#define _reg_PI_BIST_ADDR_MASK_3_P0 0x00000441U
+#define _reg_PI_BIST_ADDR_MASK_3_P1 0x00000442U
+#define _reg_PI_BIST_ADDR_MASK_4_P0 0x00000443U
+#define _reg_PI_BIST_ADDR_MASK_4_P1 0x00000444U
+#define _reg_PI_BIST_ADDR_MASK_5_P0 0x00000445U
+#define _reg_PI_BIST_ADDR_MASK_5_P1 0x00000446U
+#define _reg_PI_BIST_ADDR_MASK_6_P0 0x00000447U
+#define _reg_PI_BIST_ADDR_MASK_6_P1 0x00000448U
+#define _reg_PI_BIST_ADDR_MASK_7_P0 0x00000449U
+#define _reg_PI_BIST_ADDR_MASK_7_P1 0x0000044aU
+#define _reg_PI_BIST_ADDR_MASK_8_P0 0x0000044bU
+#define _reg_PI_BIST_ADDR_MASK_8_P1 0x0000044cU
+#define _reg_PI_BIST_ADDR_MASK_9_P0 0x0000044dU
+#define _reg_PI_BIST_ADDR_MASK_9_P1 0x0000044eU
+#define _reg_PI_BIST_MODE 0x0000044fU
+#define _reg_PI_BIST_ADDR_MODE 0x00000450U
+#define _reg_PI_BIST_PAT_MODE 0x00000451U
+#define _reg_PI_BIST_USER_PAT_P0 0x00000452U
+#define _reg_PI_BIST_USER_PAT_P1 0x00000453U
+#define _reg_PI_BIST_USER_PAT_P2 0x00000454U
+#define _reg_PI_BIST_USER_PAT_P3 0x00000455U
+#define _reg_PI_BIST_PAT_NUM 0x00000456U
+#define _reg_PI_BIST_STAGE_0 0x00000457U
+#define _reg_PI_BIST_STAGE_1 0x00000458U
+#define _reg_PI_BIST_STAGE_2 0x00000459U
+#define _reg_PI_BIST_STAGE_3 0x0000045aU
+#define _reg_PI_BIST_STAGE_4 0x0000045bU
+#define _reg_PI_BIST_STAGE_5 0x0000045cU
+#define _reg_PI_BIST_STAGE_6 0x0000045dU
+#define _reg_PI_BIST_STAGE_7 0x0000045eU
+#define _reg_PI_COL_DIFF 0x0000045fU
+#define _reg_PI_SELF_REFRESH_EN 0x00000460U
+#define _reg_PI_TXSR_F0 0x00000461U
+#define _reg_PI_TXSR_F1 0x00000462U
+#define _reg_PI_TXSR_F2 0x00000463U
+#define _reg_PI_MONITOR_SRC_SEL_0 0x00000464U
+#define _reg_PI_MONITOR_CAP_SEL_0 0x00000465U
+#define _reg_PI_MONITOR_0 0x00000466U
+#define _reg_PI_MONITOR_SRC_SEL_1 0x00000467U
+#define _reg_PI_MONITOR_CAP_SEL_1 0x00000468U
+#define _reg_PI_MONITOR_1 0x00000469U
+#define _reg_PI_MONITOR_SRC_SEL_2 0x0000046aU
+#define _reg_PI_MONITOR_CAP_SEL_2 0x0000046bU
+#define _reg_PI_MONITOR_2 0x0000046cU
+#define _reg_PI_MONITOR_SRC_SEL_3 0x0000046dU
+#define _reg_PI_MONITOR_CAP_SEL_3 0x0000046eU
+#define _reg_PI_MONITOR_3 0x0000046fU
+#define _reg_PI_MONITOR_SRC_SEL_4 0x00000470U
+#define _reg_PI_MONITOR_CAP_SEL_4 0x00000471U
+#define _reg_PI_MONITOR_4 0x00000472U
+#define _reg_PI_MONITOR_SRC_SEL_5 0x00000473U
+#define _reg_PI_MONITOR_CAP_SEL_5 0x00000474U
+#define _reg_PI_MONITOR_5 0x00000475U
+#define _reg_PI_MONITOR_SRC_SEL_6 0x00000476U
+#define _reg_PI_MONITOR_CAP_SEL_6 0x00000477U
+#define _reg_PI_MONITOR_6 0x00000478U
+#define _reg_PI_MONITOR_SRC_SEL_7 0x00000479U
+#define _reg_PI_MONITOR_CAP_SEL_7 0x0000047aU
+#define _reg_PI_MONITOR_7 0x0000047bU
+#define _reg_PI_MONITOR_STROBE 0x0000047cU
+#define _reg_PI_DLL_LOCK 0x0000047dU
+#define _reg_PI_FREQ_NUMBER_STATUS 0x0000047eU
+#define _reg_RESERVED_R24 0x0000047fU
+#define _reg_PI_PHYMSTR_TYPE 0x00000480U
+#define _reg_PI_POWER_REDUC_EN 0x00000481U
+#define _reg_RESERVED_R25 0x00000482U
+#define _reg_RESERVED_R26 0x00000483U
+#define _reg_RESERVED_R27 0x00000484U
+#define _reg_RESERVED_R28 0x00000485U
+#define _reg_RESERVED_R29 0x00000486U
+#define _reg_RESERVED_R30 0x00000487U
+#define _reg_RESERVED_R31 0x00000488U
+#define _reg_RESERVED_R32 0x00000489U
+#define _reg_RESERVED_R33 0x0000048aU
+#define _reg_RESERVED_R34 0x0000048bU
+#define _reg_RESERVED_R35 0x0000048cU
+#define _reg_RESERVED_R36 0x0000048dU
+#define _reg_RESERVED_R37 0x0000048eU
+#define _reg_RESERVED_R38 0x0000048fU
+#define _reg_RESERVED_R39 0x00000490U
+#define _reg_PI_WRLVL_MAX_STROBE_PEND 0x00000491U
+#define _reg_PI_TSDO_F0 0x00000492U
+#define _reg_PI_TSDO_F1 0x00000493U
+#define _reg_PI_TSDO_F2 0x00000494U
+
+#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xffffU)
+#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xffU)
+#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xffU)
+
+static const uint32_t DDR_REGDEF_TBL[4][1173] = {
+ {
+/*0000*/ 0xffffffffU,
+/*0001*/ 0xffffffffU,
+/*0002*/ 0x000b0400U,
+/*0003*/ 0xffffffffU,
+/*0004*/ 0xffffffffU,
+/*0005*/ 0x10010400U,
+/*0006*/ 0x18050400U,
+/*0007*/ 0x00050401U,
+/*0008*/ 0x08050401U,
+/*0009*/ 0x10050401U,
+/*000a*/ 0x18050401U,
+/*000b*/ 0x00050402U,
+/*000c*/ 0x08050402U,
+/*000d*/ 0x10050402U,
+/*000e*/ 0x18050402U,
+/*000f*/ 0x00040403U,
+/*0010*/ 0x08030403U,
+/*0011*/ 0x00180404U,
+/*0012*/ 0x18030404U,
+/*0013*/ 0x00180405U,
+/*0014*/ 0x18020405U,
+/*0015*/ 0x00010406U,
+/*0016*/ 0x08020406U,
+/*0017*/ 0x10010406U,
+/*0018*/ 0x18010406U,
+/*0019*/ 0x00020407U,
+/*001a*/ 0x08040407U,
+/*001b*/ 0x10040407U,
+/*001c*/ 0x18040407U,
+/*001d*/ 0x000a0408U,
+/*001e*/ 0x10040408U,
+/*001f*/ 0xffffffffU,
+/*0020*/ 0xffffffffU,
+/*0021*/ 0x18070408U,
+/*0022*/ 0xffffffffU,
+/*0023*/ 0xffffffffU,
+/*0024*/ 0xffffffffU,
+/*0025*/ 0xffffffffU,
+/*0026*/ 0xffffffffU,
+/*0027*/ 0xffffffffU,
+/*0028*/ 0x000a0409U,
+/*0029*/ 0x10040409U,
+/*002a*/ 0x18010409U,
+/*002b*/ 0x0001040aU,
+/*002c*/ 0x0802040aU,
+/*002d*/ 0x1009040aU,
+/*002e*/ 0x0009040bU,
+/*002f*/ 0x1002040bU,
+/*0030*/ 0x0020040cU,
+/*0031*/ 0xffffffffU,
+/*0032*/ 0x0001040dU,
+/*0033*/ 0xffffffffU,
+/*0034*/ 0xffffffffU,
+/*0035*/ 0xffffffffU,
+/*0036*/ 0xffffffffU,
+/*0037*/ 0x0020040eU,
+/*0038*/ 0x0020040fU,
+/*0039*/ 0x00200410U,
+/*003a*/ 0x00200411U,
+/*003b*/ 0x00030412U,
+/*003c*/ 0x08010412U,
+/*003d*/ 0x10030412U,
+/*003e*/ 0x18030412U,
+/*003f*/ 0x00040413U,
+/*0040*/ 0x08040413U,
+/*0041*/ 0x10040413U,
+/*0042*/ 0x18040413U,
+/*0043*/ 0x00010414U,
+/*0044*/ 0x08010414U,
+/*0045*/ 0x10060414U,
+/*0046*/ 0x18040414U,
+/*0047*/ 0xffffffffU,
+/*0048*/ 0x00060415U,
+/*0049*/ 0x08040415U,
+/*004a*/ 0x10060415U,
+/*004b*/ 0x18040415U,
+/*004c*/ 0x00020416U,
+/*004d*/ 0x08050416U,
+/*004e*/ 0x10080416U,
+/*004f*/ 0x00200417U,
+/*0050*/ 0x00060418U,
+/*0051*/ 0x08030418U,
+/*0052*/ 0x100b0418U,
+/*0053*/ 0x00040419U,
+/*0054*/ 0x08040419U,
+/*0055*/ 0x10040419U,
+/*0056*/ 0xffffffffU,
+/*0057*/ 0x18010419U,
+/*0058*/ 0x0009041aU,
+/*0059*/ 0x0020041bU,
+/*005a*/ 0x0020041cU,
+/*005b*/ 0x0020041dU,
+/*005c*/ 0x0020041eU,
+/*005d*/ 0x0010041fU,
+/*005e*/ 0x00200420U,
+/*005f*/ 0x00010421U,
+/*0060*/ 0x08060421U,
+/*0061*/ 0x10080421U,
+/*0062*/ 0x00200422U,
+/*0063*/ 0xffffffffU,
+/*0064*/ 0x000a0423U,
+/*0065*/ 0x10060423U,
+/*0066*/ 0x18070423U,
+/*0067*/ 0x00080424U,
+/*0068*/ 0x08080424U,
+/*0069*/ 0x100a0424U,
+/*006a*/ 0x00070425U,
+/*006b*/ 0x08080425U,
+/*006c*/ 0x10080425U,
+/*006d*/ 0x18030425U,
+/*006e*/ 0x000a0426U,
+/*006f*/ 0x100a0426U,
+/*0070*/ 0x00110427U,
+/*0071*/ 0x00090428U,
+/*0072*/ 0x10090428U,
+/*0073*/ 0x00100429U,
+/*0074*/ 0x100e0429U,
+/*0075*/ 0x000e042aU,
+/*0076*/ 0x100c042aU,
+/*0077*/ 0x000a042bU,
+/*0078*/ 0x100a042bU,
+/*0079*/ 0x0002042cU,
+/*007a*/ 0x0020042dU,
+/*007b*/ 0x000b042eU,
+/*007c*/ 0x100b042eU,
+/*007d*/ 0x0020042fU,
+/*007e*/ 0x00120430U,
+/*007f*/ 0x00200431U,
+/*0080*/ 0x00200432U,
+/*0081*/ 0xffffffffU,
+/*0082*/ 0xffffffffU,
+/*0083*/ 0x00010433U,
+/*0084*/ 0x08010433U,
+/*0085*/ 0x10080433U,
+/*0086*/ 0x000c0434U,
+/*0087*/ 0x100c0434U,
+/*0088*/ 0x000c0435U,
+/*0089*/ 0x100c0435U,
+/*008a*/ 0x000c0436U,
+/*008b*/ 0x100c0436U,
+/*008c*/ 0x000c0437U,
+/*008d*/ 0x100c0437U,
+/*008e*/ 0x000c0438U,
+/*008f*/ 0x100c0438U,
+/*0090*/ 0x000c0439U,
+/*0091*/ 0x100b0439U,
+/*0092*/ 0xffffffffU,
+/*0093*/ 0xffffffffU,
+/*0094*/ 0x000b043aU,
+/*0095*/ 0x100b043aU,
+/*0096*/ 0x000b043bU,
+/*0097*/ 0x100b043bU,
+/*0098*/ 0x000b043cU,
+/*0099*/ 0x100b043cU,
+/*009a*/ 0x000b043dU,
+/*009b*/ 0x100b043dU,
+/*009c*/ 0x000b043eU,
+/*009d*/ 0x100a043eU,
+/*009e*/ 0xffffffffU,
+/*009f*/ 0x000a043fU,
+/*00a0*/ 0x100a043fU,
+/*00a1*/ 0x000a0440U,
+/*00a2*/ 0x100a0440U,
+/*00a3*/ 0x000a0441U,
+/*00a4*/ 0x100a0441U,
+/*00a5*/ 0x000a0442U,
+/*00a6*/ 0x100a0442U,
+/*00a7*/ 0xffffffffU,
+/*00a8*/ 0x000a0443U,
+/*00a9*/ 0x100a0443U,
+/*00aa*/ 0x000a0444U,
+/*00ab*/ 0x100a0444U,
+/*00ac*/ 0x000a0445U,
+/*00ad*/ 0x100a0445U,
+/*00ae*/ 0x000a0446U,
+/*00af*/ 0x100a0446U,
+/*00b0*/ 0x000a0447U,
+/*00b1*/ 0x100a0447U,
+/*00b2*/ 0x000a0448U,
+/*00b3*/ 0x100a0448U,
+/*00b4*/ 0x000a0449U,
+/*00b5*/ 0x100a0449U,
+/*00b6*/ 0x000a044aU,
+/*00b7*/ 0x100a044aU,
+/*00b8*/ 0x000a044bU,
+/*00b9*/ 0x100a044bU,
+/*00ba*/ 0x000a044cU,
+/*00bb*/ 0x1004044cU,
+/*00bc*/ 0x1803044cU,
+/*00bd*/ 0x000a044dU,
+/*00be*/ 0x100a044dU,
+/*00bf*/ 0x0001044eU,
+/*00c0*/ 0x080a044eU,
+/*00c1*/ 0x1804044eU,
+/*00c2*/ 0x000b044fU,
+/*00c3*/ 0x100a044fU,
+/*00c4*/ 0xffffffffU,
+/*00c5*/ 0x00080450U,
+/*00c6*/ 0x08080450U,
+/*00c7*/ 0x10080450U,
+/*00c8*/ 0x18080450U,
+/*00c9*/ 0x00080451U,
+/*00ca*/ 0xffffffffU,
+/*00cb*/ 0x08080451U,
+/*00cc*/ 0x10010451U,
+/*00cd*/ 0x18080451U,
+/*00ce*/ 0x00080452U,
+/*00cf*/ 0x08020452U,
+/*00d0*/ 0x10020452U,
+/*00d1*/ 0x18040452U,
+/*00d2*/ 0x00040453U,
+/*00d3*/ 0xffffffffU,
+/*00d4*/ 0x08040453U,
+/*00d5*/ 0x100a0453U,
+/*00d6*/ 0x00060454U,
+/*00d7*/ 0x08080454U,
+/*00d8*/ 0xffffffffU,
+/*00d9*/ 0x10040454U,
+/*00da*/ 0x18040454U,
+/*00db*/ 0x00050455U,
+/*00dc*/ 0x08040455U,
+/*00dd*/ 0x10050455U,
+/*00de*/ 0x000a0456U,
+/*00df*/ 0x100a0456U,
+/*00e0*/ 0x00080457U,
+/*00e1*/ 0xffffffffU,
+/*00e2*/ 0x08040457U,
+/*00e3*/ 0xffffffffU,
+/*00e4*/ 0xffffffffU,
+/*00e5*/ 0x00050600U,
+/*00e6*/ 0x08050600U,
+/*00e7*/ 0x10050600U,
+/*00e8*/ 0x18050600U,
+/*00e9*/ 0x00050601U,
+/*00ea*/ 0x08050601U,
+/*00eb*/ 0x100b0601U,
+/*00ec*/ 0x00010602U,
+/*00ed*/ 0x08030602U,
+/*00ee*/ 0x00200603U,
+/*00ef*/ 0xffffffffU,
+/*00f0*/ 0x00030604U,
+/*00f1*/ 0x080a0604U,
+/*00f2*/ 0xffffffffU,
+/*00f3*/ 0xffffffffU,
+/*00f4*/ 0x18030604U,
+/*00f5*/ 0x00030605U,
+/*00f6*/ 0x08010605U,
+/*00f7*/ 0x10010605U,
+/*00f8*/ 0x18060605U,
+/*00f9*/ 0xffffffffU,
+/*00fa*/ 0xffffffffU,
+/*00fb*/ 0xffffffffU,
+/*00fc*/ 0x00020606U,
+/*00fd*/ 0x08030606U,
+/*00fe*/ 0x10010606U,
+/*00ff*/ 0x000f0607U,
+/*0100*/ 0x00200608U,
+/*0101*/ 0x00200609U,
+/*0102*/ 0x000b060aU,
+/*0103*/ 0x100b060aU,
+/*0104*/ 0x000b060bU,
+/*0105*/ 0xffffffffU,
+/*0106*/ 0xffffffffU,
+/*0107*/ 0x0018060cU,
+/*0108*/ 0x0018060dU,
+/*0109*/ 0x0018060eU,
+/*010a*/ 0x0018060fU,
+/*010b*/ 0x1804060fU,
+/*010c*/ 0x00050610U,
+/*010d*/ 0x08020610U,
+/*010e*/ 0x10040610U,
+/*010f*/ 0x18040610U,
+/*0110*/ 0x00010611U,
+/*0111*/ 0x08010611U,
+/*0112*/ 0x10010611U,
+/*0113*/ 0x18030611U,
+/*0114*/ 0x00200612U,
+/*0115*/ 0x00200613U,
+/*0116*/ 0x00010614U,
+/*0117*/ 0x08140614U,
+/*0118*/ 0x00140615U,
+/*0119*/ 0x00140616U,
+/*011a*/ 0x00140617U,
+/*011b*/ 0x00140618U,
+/*011c*/ 0x00140619U,
+/*011d*/ 0x0014061aU,
+/*011e*/ 0x0014061bU,
+/*011f*/ 0x0018061cU,
+/*0120*/ 0x000a061dU,
+/*0121*/ 0x1006061dU,
+/*0122*/ 0x1806061dU,
+/*0123*/ 0x0006061eU,
+/*0124*/ 0xffffffffU,
+/*0125*/ 0xffffffffU,
+/*0126*/ 0x0008061fU,
+/*0127*/ 0x080b061fU,
+/*0128*/ 0x000b0620U,
+/*0129*/ 0x100b0620U,
+/*012a*/ 0x000b0621U,
+/*012b*/ 0x100b0621U,
+/*012c*/ 0x000b0622U,
+/*012d*/ 0x10040622U,
+/*012e*/ 0x000a0623U,
+/*012f*/ 0x10060623U,
+/*0130*/ 0x18080623U,
+/*0131*/ 0xffffffffU,
+/*0132*/ 0x00040624U,
+/*0133*/ 0xffffffffU,
+/*0134*/ 0xffffffffU,
+/*0135*/ 0x00010700U,
+/*0136*/ 0x08020700U,
+/*0137*/ 0x10050700U,
+/*0138*/ 0x18050700U,
+/*0139*/ 0x00050701U,
+/*013a*/ 0x08050701U,
+/*013b*/ 0x100b0701U,
+/*013c*/ 0x00050702U,
+/*013d*/ 0x08010702U,
+/*013e*/ 0x10010702U,
+/*013f*/ 0xffffffffU,
+/*0140*/ 0x18010702U,
+/*0141*/ 0x00010703U,
+/*0142*/ 0x08040703U,
+/*0143*/ 0x100b0703U,
+/*0144*/ 0x000b0704U,
+/*0145*/ 0xffffffffU,
+/*0146*/ 0x10040704U,
+/*0147*/ 0x000b0705U,
+/*0148*/ 0x10040705U,
+/*0149*/ 0x18010705U,
+/*014a*/ 0x00010706U,
+/*014b*/ 0x08010706U,
+/*014c*/ 0x00200707U,
+/*014d*/ 0x00200708U,
+/*014e*/ 0x00080709U,
+/*014f*/ 0x080a0709U,
+/*0150*/ 0x18050709U,
+/*0151*/ 0x000a070aU,
+/*0152*/ 0x1003070aU,
+/*0153*/ 0x1803070aU,
+/*0154*/ 0x0001070bU,
+/*0155*/ 0x0802070bU,
+/*0156*/ 0x1001070bU,
+/*0157*/ 0x1801070bU,
+/*0158*/ 0x0001070cU,
+/*0159*/ 0x0802070cU,
+/*015a*/ 0xffffffffU,
+/*015b*/ 0xffffffffU,
+/*015c*/ 0xffffffffU,
+/*015d*/ 0xffffffffU,
+/*015e*/ 0xffffffffU,
+/*015f*/ 0xffffffffU,
+/*0160*/ 0xffffffffU,
+/*0161*/ 0xffffffffU,
+/*0162*/ 0xffffffffU,
+/*0163*/ 0xffffffffU,
+/*0164*/ 0xffffffffU,
+/*0165*/ 0xffffffffU,
+/*0166*/ 0x1001070cU,
+/*0167*/ 0x1801070cU,
+/*0168*/ 0x000d070dU,
+/*0169*/ 0xffffffffU,
+/*016a*/ 0xffffffffU,
+/*016b*/ 0x0005070eU,
+/*016c*/ 0x0001070fU,
+/*016d*/ 0x080e070fU,
+/*016e*/ 0x000e0710U,
+/*016f*/ 0x100e0710U,
+/*0170*/ 0x000e0711U,
+/*0171*/ 0x100e0711U,
+/*0172*/ 0x00040712U,
+/*0173*/ 0xffffffffU,
+/*0174*/ 0xffffffffU,
+/*0175*/ 0xffffffffU,
+/*0176*/ 0xffffffffU,
+/*0177*/ 0x080b0712U,
+/*0178*/ 0x000b0713U,
+/*0179*/ 0x100b0713U,
+/*017a*/ 0x000b0714U,
+/*017b*/ 0xffffffffU,
+/*017c*/ 0xffffffffU,
+/*017d*/ 0xffffffffU,
+/*017e*/ 0xffffffffU,
+/*017f*/ 0x000d0715U,
+/*0180*/ 0xffffffffU,
+/*0181*/ 0xffffffffU,
+/*0182*/ 0x10100715U,
+/*0183*/ 0x00080716U,
+/*0184*/ 0xffffffffU,
+/*0185*/ 0x08100716U,
+/*0186*/ 0x00100717U,
+/*0187*/ 0x10100717U,
+/*0188*/ 0x00100718U,
+/*0189*/ 0x10100718U,
+/*018a*/ 0x00030719U,
+/*018b*/ 0x08040719U,
+/*018c*/ 0x10010719U,
+/*018d*/ 0x18040719U,
+/*018e*/ 0xffffffffU,
+/*018f*/ 0xffffffffU,
+/*0190*/ 0x0001071aU,
+/*0191*/ 0x0812071aU,
+/*0192*/ 0x000a071bU,
+/*0193*/ 0x100c071bU,
+/*0194*/ 0x0012071cU,
+/*0195*/ 0x0014071dU,
+/*0196*/ 0x0012071eU,
+/*0197*/ 0x0011071fU,
+/*0198*/ 0x00110720U,
+/*0199*/ 0x00120721U,
+/*019a*/ 0x00120722U,
+/*019b*/ 0x00120723U,
+/*019c*/ 0x00120724U,
+/*019d*/ 0x00120725U,
+/*019e*/ 0x00120726U,
+/*019f*/ 0x00120727U,
+/*01a0*/ 0x00120728U,
+/*01a1*/ 0xffffffffU,
+/*01a2*/ 0xffffffffU,
+/*01a3*/ 0x00190729U,
+/*01a4*/ 0x0019072aU,
+/*01a5*/ 0x0020072bU,
+/*01a6*/ 0x0017072cU,
+/*01a7*/ 0x1808072cU,
+/*01a8*/ 0x0001072dU,
+/*01a9*/ 0x0801072dU,
+/*01aa*/ 0x0020072eU,
+/*01ab*/ 0x0008072fU,
+/*01ac*/ 0xffffffffU,
+/*01ad*/ 0x0803072fU,
+/*01ae*/ 0x00180730U,
+/*01af*/ 0x00180731U,
+/*01b0*/ 0xffffffffU,
+/*01b1*/ 0xffffffffU,
+/*01b2*/ 0xffffffffU,
+/*01b3*/ 0xffffffffU,
+/*01b4*/ 0xffffffffU,
+/*01b5*/ 0xffffffffU,
+/*01b6*/ 0xffffffffU,
+/*01b7*/ 0xffffffffU,
+/*01b8*/ 0xffffffffU,
+/*01b9*/ 0xffffffffU,
+/*01ba*/ 0xffffffffU,
+/*01bb*/ 0xffffffffU,
+/*01bc*/ 0xffffffffU,
+/*01bd*/ 0xffffffffU,
+/*01be*/ 0xffffffffU,
+/*01bf*/ 0x00100732U,
+/*01c0*/ 0x10010732U,
+/*01c1*/ 0x18010732U,
+/*01c2*/ 0x00050733U,
+/*01c3*/ 0x00200734U,
+/*01c4*/ 0x00090735U,
+/*01c5*/ 0xffffffffU,
+/*01c6*/ 0xffffffffU,
+/*01c7*/ 0x00200736U,
+/*01c8*/ 0x00040737U,
+/*01c9*/ 0x08100737U,
+/*01ca*/ 0x18060737U,
+/*01cb*/ 0x00100738U,
+/*01cc*/ 0xffffffffU,
+/*01cd*/ 0xffffffffU,
+/*01ce*/ 0xffffffffU,
+/*01cf*/ 0xffffffffU,
+/*01d0*/ 0xffffffffU,
+/*01d1*/ 0xffffffffU,
+/*01d2*/ 0xffffffffU,
+/*01d3*/ 0xffffffffU,
+/*01d4*/ 0x00200739U,
+/*01d5*/ 0x000b073aU,
+/*01d6*/ 0xffffffffU,
+/*01d7*/ 0xffffffffU,
+/*01d8*/ 0xffffffffU,
+/*01d9*/ 0xffffffffU,
+/*01da*/ 0xffffffffU,
+/*01db*/ 0xffffffffU,
+/*01dc*/ 0xffffffffU,
+/*01dd*/ 0xffffffffU,
+/*01de*/ 0x00010200U,
+/*01df*/ 0x08040200U,
+/*01e0*/ 0x10100200U,
+/*01e1*/ 0x00010201U,
+/*01e2*/ 0x08010201U,
+/*01e3*/ 0xffffffffU,
+/*01e4*/ 0xffffffffU,
+/*01e5*/ 0x10100201U,
+/*01e6*/ 0xffffffffU,
+/*01e7*/ 0xffffffffU,
+/*01e8*/ 0xffffffffU,
+/*01e9*/ 0xffffffffU,
+/*01ea*/ 0xffffffffU,
+/*01eb*/ 0xffffffffU,
+/*01ec*/ 0xffffffffU,
+/*01ed*/ 0xffffffffU,
+/*01ee*/ 0xffffffffU,
+/*01ef*/ 0x00200202U,
+/*01f0*/ 0x00100203U,
+/*01f1*/ 0x00200204U,
+/*01f2*/ 0x00100205U,
+/*01f3*/ 0x00200206U,
+/*01f4*/ 0x00100207U,
+/*01f5*/ 0x10100207U,
+/*01f6*/ 0x00200208U,
+/*01f7*/ 0x00200209U,
+/*01f8*/ 0x0020020aU,
+/*01f9*/ 0x0020020bU,
+/*01fa*/ 0x0010020cU,
+/*01fb*/ 0x0020020dU,
+/*01fc*/ 0x0020020eU,
+/*01fd*/ 0x0020020fU,
+/*01fe*/ 0x00200210U,
+/*01ff*/ 0x00100211U,
+/*0200*/ 0x00200212U,
+/*0201*/ 0x00200213U,
+/*0202*/ 0x00200214U,
+/*0203*/ 0x00200215U,
+/*0204*/ 0x00090216U,
+/*0205*/ 0x10010216U,
+/*0206*/ 0x00200217U,
+/*0207*/ 0x00050218U,
+/*0208*/ 0x08010218U,
+/*0209*/ 0x10080218U,
+/*020a*/ 0x18080218U,
+/*020b*/ 0x001c0219U,
+/*020c*/ 0x001c021aU,
+/*020d*/ 0x001c021bU,
+/*020e*/ 0x001c021cU,
+/*020f*/ 0x001c021dU,
+/*0210*/ 0x001c021eU,
+/*0211*/ 0x001c021fU,
+/*0212*/ 0x001c0220U,
+/*0213*/ 0x001c0221U,
+/*0214*/ 0x001c0222U,
+/*0215*/ 0x001c0223U,
+/*0216*/ 0x001c0224U,
+/*0217*/ 0x001c0225U,
+/*0218*/ 0x001c0226U,
+/*0219*/ 0x001c0227U,
+/*021a*/ 0x001c0228U,
+/*021b*/ 0x00010229U,
+/*021c*/ 0x08010229U,
+/*021d*/ 0x10010229U,
+/*021e*/ 0x18040229U,
+/*021f*/ 0x0008022aU,
+/*0220*/ 0x0808022aU,
+/*0221*/ 0x1008022aU,
+/*0222*/ 0x1804022aU,
+/*0223*/ 0x0006022bU,
+/*0224*/ 0xffffffffU,
+/*0225*/ 0x0807022bU,
+/*0226*/ 0x1006022bU,
+/*0227*/ 0xffffffffU,
+/*0228*/ 0x1807022bU,
+/*0229*/ 0x0006022cU,
+/*022a*/ 0xffffffffU,
+/*022b*/ 0x0807022cU,
+/*022c*/ 0x1002022cU,
+/*022d*/ 0x1801022cU,
+/*022e*/ 0xffffffffU,
+/*022f*/ 0x000a022dU,
+/*0230*/ 0x1010022dU,
+/*0231*/ 0x000a022eU,
+/*0232*/ 0x1010022eU,
+/*0233*/ 0x000a022fU,
+/*0234*/ 0x1010022fU,
+/*0235*/ 0xffffffffU,
+/*0236*/ 0x00100230U,
+/*0237*/ 0xffffffffU,
+/*0238*/ 0xffffffffU,
+/*0239*/ 0x10010230U,
+/*023a*/ 0x18010230U,
+/*023b*/ 0x00010231U,
+/*023c*/ 0x08010231U,
+/*023d*/ 0x10010231U,
+/*023e*/ 0x18010231U,
+/*023f*/ 0x00020232U,
+/*0240*/ 0x08020232U,
+/*0241*/ 0x10020232U,
+/*0242*/ 0x18020232U,
+/*0243*/ 0x00020233U,
+/*0244*/ 0x08030233U,
+/*0245*/ 0x10010233U,
+/*0246*/ 0x18010233U,
+/*0247*/ 0x00010234U,
+/*0248*/ 0x08010234U,
+/*0249*/ 0xffffffffU,
+/*024a*/ 0x10020234U,
+/*024b*/ 0x18010234U,
+/*024c*/ 0x00010235U,
+/*024d*/ 0xffffffffU,
+/*024e*/ 0x08020235U,
+/*024f*/ 0x10010235U,
+/*0250*/ 0x18010235U,
+/*0251*/ 0xffffffffU,
+/*0252*/ 0x00020236U,
+/*0253*/ 0x08010236U,
+/*0254*/ 0x10010236U,
+/*0255*/ 0xffffffffU,
+/*0256*/ 0x18020236U,
+/*0257*/ 0x00070237U,
+/*0258*/ 0x08010237U,
+/*0259*/ 0x10010237U,
+/*025a*/ 0x18010237U,
+/*025b*/ 0x00010238U,
+/*025c*/ 0x08010238U,
+/*025d*/ 0x10010238U,
+/*025e*/ 0xffffffffU,
+/*025f*/ 0x18010238U,
+/*0260*/ 0x00040239U,
+/*0261*/ 0x08040239U,
+/*0262*/ 0x10040239U,
+/*0263*/ 0x18010239U,
+/*0264*/ 0x0002023aU,
+/*0265*/ 0x0806023aU,
+/*0266*/ 0x1006023aU,
+/*0267*/ 0xffffffffU,
+/*0268*/ 0xffffffffU,
+/*0269*/ 0xffffffffU,
+/*026a*/ 0x1802023aU,
+/*026b*/ 0x0010023bU,
+/*026c*/ 0x1001023bU,
+/*026d*/ 0x1801023bU,
+/*026e*/ 0xffffffffU,
+/*026f*/ 0x0004023cU,
+/*0270*/ 0x0801023cU,
+/*0271*/ 0x1004023cU,
+/*0272*/ 0x1802023cU,
+/*0273*/ 0x0008023dU,
+/*0274*/ 0xffffffffU,
+/*0275*/ 0xffffffffU,
+/*0276*/ 0xffffffffU,
+/*0277*/ 0x080a023dU,
+/*0278*/ 0x0020023eU,
+/*0279*/ 0x0020023fU,
+/*027a*/ 0x00050240U,
+/*027b*/ 0x08010240U,
+/*027c*/ 0x10050240U,
+/*027d*/ 0x18080240U,
+/*027e*/ 0x00010241U,
+/*027f*/ 0x08080241U,
+/*0280*/ 0x10010241U,
+/*0281*/ 0x18080241U,
+/*0282*/ 0x00010242U,
+/*0283*/ 0x08040242U,
+/*0284*/ 0x10040242U,
+/*0285*/ 0x18040242U,
+/*0286*/ 0x00040243U,
+/*0287*/ 0x08040243U,
+/*0288*/ 0x10040243U,
+/*0289*/ 0x18040243U,
+/*028a*/ 0x00040244U,
+/*028b*/ 0x08040244U,
+/*028c*/ 0x10040244U,
+/*028d*/ 0x18010244U,
+/*028e*/ 0x00040245U,
+/*028f*/ 0x08040245U,
+/*0290*/ 0x10040245U,
+/*0291*/ 0x18040245U,
+/*0292*/ 0x00040246U,
+/*0293*/ 0x08040246U,
+/*0294*/ 0x10060246U,
+/*0295*/ 0x18060246U,
+/*0296*/ 0x00060247U,
+/*0297*/ 0x08060247U,
+/*0298*/ 0x10060247U,
+/*0299*/ 0x18060247U,
+/*029a*/ 0xffffffffU,
+/*029b*/ 0x00010248U,
+/*029c*/ 0x08010248U,
+/*029d*/ 0x10020248U,
+/*029e*/ 0xffffffffU,
+/*029f*/ 0xffffffffU,
+/*02a0*/ 0xffffffffU,
+/*02a1*/ 0xffffffffU,
+/*02a2*/ 0xffffffffU,
+/*02a3*/ 0xffffffffU,
+/*02a4*/ 0xffffffffU,
+/*02a5*/ 0xffffffffU,
+/*02a6*/ 0x18040248U,
+/*02a7*/ 0x00040249U,
+/*02a8*/ 0x08010249U,
+/*02a9*/ 0x10010249U,
+/*02aa*/ 0xffffffffU,
+/*02ab*/ 0x18010249U,
+/*02ac*/ 0x0001024aU,
+/*02ad*/ 0xffffffffU,
+/*02ae*/ 0x0801024aU,
+/*02af*/ 0x1001024aU,
+/*02b0*/ 0x1801024aU,
+/*02b1*/ 0x0004024bU,
+/*02b2*/ 0x0804024bU,
+/*02b3*/ 0x100a024bU,
+/*02b4*/ 0x0020024cU,
+/*02b5*/ 0x0004024dU,
+/*02b6*/ 0x0808024dU,
+/*02b7*/ 0xffffffffU,
+/*02b8*/ 0xffffffffU,
+/*02b9*/ 0xffffffffU,
+/*02ba*/ 0xffffffffU,
+/*02bb*/ 0xffffffffU,
+/*02bc*/ 0xffffffffU,
+/*02bd*/ 0x1002024dU,
+/*02be*/ 0x1802024dU,
+/*02bf*/ 0x0020024eU,
+/*02c0*/ 0x0002024fU,
+/*02c1*/ 0x0810024fU,
+/*02c2*/ 0x00100250U,
+/*02c3*/ 0x10040250U,
+/*02c4*/ 0x18040250U,
+/*02c5*/ 0x00050251U,
+/*02c6*/ 0x08050251U,
+/*02c7*/ 0xffffffffU,
+/*02c8*/ 0xffffffffU,
+/*02c9*/ 0xffffffffU,
+/*02ca*/ 0xffffffffU,
+/*02cb*/ 0x10010251U,
+/*02cc*/ 0x18010251U,
+/*02cd*/ 0x00070252U,
+/*02ce*/ 0x08070252U,
+/*02cf*/ 0x10070252U,
+/*02d0*/ 0x18070252U,
+/*02d1*/ 0x00070253U,
+/*02d2*/ 0x08070253U,
+/*02d3*/ 0x10070253U,
+/*02d4*/ 0x18070253U,
+/*02d5*/ 0x00070254U,
+/*02d6*/ 0x08070254U,
+/*02d7*/ 0x10070254U,
+/*02d8*/ 0xffffffffU,
+/*02d9*/ 0xffffffffU,
+/*02da*/ 0xffffffffU,
+/*02db*/ 0xffffffffU,
+/*02dc*/ 0xffffffffU,
+/*02dd*/ 0xffffffffU,
+/*02de*/ 0x18030254U,
+/*02df*/ 0x00010255U,
+/*02e0*/ 0x08020255U,
+/*02e1*/ 0x10010255U,
+/*02e2*/ 0x18040255U,
+/*02e3*/ 0x00020256U,
+/*02e4*/ 0x08010256U,
+/*02e5*/ 0x10010256U,
+/*02e6*/ 0xffffffffU,
+/*02e7*/ 0x18010256U,
+/*02e8*/ 0x00040257U,
+/*02e9*/ 0x08080257U,
+/*02ea*/ 0x100a0257U,
+/*02eb*/ 0x000a0258U,
+/*02ec*/ 0x100a0258U,
+/*02ed*/ 0x000a0259U,
+/*02ee*/ 0x100a0259U,
+/*02ef*/ 0x000a025aU,
+/*02f0*/ 0x0020025bU,
+/*02f1*/ 0x0020025cU,
+/*02f2*/ 0x0001025dU,
+/*02f3*/ 0xffffffffU,
+/*02f4*/ 0xffffffffU,
+/*02f5*/ 0xffffffffU,
+/*02f6*/ 0x0802025dU,
+/*02f7*/ 0x1002025dU,
+/*02f8*/ 0x0010025eU,
+/*02f9*/ 0x1005025eU,
+/*02fa*/ 0x1806025eU,
+/*02fb*/ 0x0005025fU,
+/*02fc*/ 0x0805025fU,
+/*02fd*/ 0x100e025fU,
+/*02fe*/ 0x00050260U,
+/*02ff*/ 0x080e0260U,
+/*0300*/ 0x18050260U,
+/*0301*/ 0x000e0261U,
+/*0302*/ 0x10050261U,
+/*0303*/ 0x18010261U,
+/*0304*/ 0x00050262U,
+/*0305*/ 0x08050262U,
+/*0306*/ 0x100a0262U,
+/*0307*/ 0x000a0263U,
+/*0308*/ 0x10050263U,
+/*0309*/ 0x18050263U,
+/*030a*/ 0x000a0264U,
+/*030b*/ 0x100a0264U,
+/*030c*/ 0x00050265U,
+/*030d*/ 0x08050265U,
+/*030e*/ 0x100a0265U,
+/*030f*/ 0x000a0266U,
+/*0310*/ 0xffffffffU,
+/*0311*/ 0xffffffffU,
+/*0312*/ 0xffffffffU,
+/*0313*/ 0xffffffffU,
+/*0314*/ 0xffffffffU,
+/*0315*/ 0xffffffffU,
+/*0316*/ 0x10070266U,
+/*0317*/ 0x18070266U,
+/*0318*/ 0x00040267U,
+/*0319*/ 0x08040267U,
+/*031a*/ 0xffffffffU,
+/*031b*/ 0xffffffffU,
+/*031c*/ 0xffffffffU,
+/*031d*/ 0x10040267U,
+/*031e*/ 0x18080267U,
+/*031f*/ 0x00080268U,
+/*0320*/ 0x08040268U,
+/*0321*/ 0xffffffffU,
+/*0322*/ 0xffffffffU,
+/*0323*/ 0xffffffffU,
+/*0324*/ 0x10040268U,
+/*0325*/ 0xffffffffU,
+/*0326*/ 0xffffffffU,
+/*0327*/ 0xffffffffU,
+/*0328*/ 0x18040268U,
+/*0329*/ 0xffffffffU,
+/*032a*/ 0xffffffffU,
+/*032b*/ 0xffffffffU,
+/*032c*/ 0x00040269U,
+/*032d*/ 0x08050269U,
+/*032e*/ 0x10070269U,
+/*032f*/ 0x18080269U,
+/*0330*/ 0x0010026aU,
+/*0331*/ 0x1008026aU,
+/*0332*/ 0x0010026bU,
+/*0333*/ 0x1008026bU,
+/*0334*/ 0x0010026cU,
+/*0335*/ 0x1008026cU,
+/*0336*/ 0x1808026cU,
+/*0337*/ 0x0001026dU,
+/*0338*/ 0x0801026dU,
+/*0339*/ 0x1006026dU,
+/*033a*/ 0x1806026dU,
+/*033b*/ 0x0006026eU,
+/*033c*/ 0xffffffffU,
+/*033d*/ 0x0801026eU,
+/*033e*/ 0x1003026eU,
+/*033f*/ 0xffffffffU,
+/*0340*/ 0xffffffffU,
+/*0341*/ 0xffffffffU,
+/*0342*/ 0x000a026fU,
+/*0343*/ 0x100a026fU,
+/*0344*/ 0x00040270U,
+/*0345*/ 0x08010270U,
+/*0346*/ 0x10040270U,
+/*0347*/ 0xffffffffU,
+/*0348*/ 0xffffffffU,
+/*0349*/ 0xffffffffU,
+/*034a*/ 0xffffffffU,
+/*034b*/ 0xffffffffU,
+/*034c*/ 0xffffffffU,
+/*034d*/ 0x18070270U,
+/*034e*/ 0x00070271U,
+/*034f*/ 0x08050271U,
+/*0350*/ 0x10050271U,
+/*0351*/ 0xffffffffU,
+/*0352*/ 0xffffffffU,
+/*0353*/ 0xffffffffU,
+/*0354*/ 0x18040271U,
+/*0355*/ 0x00010272U,
+/*0356*/ 0x08010272U,
+/*0357*/ 0x10020272U,
+/*0358*/ 0x18080272U,
+/*0359*/ 0x00200273U,
+/*035a*/ 0x00200274U,
+/*035b*/ 0x00100275U,
+/*035c*/ 0xffffffffU,
+/*035d*/ 0xffffffffU,
+/*035e*/ 0xffffffffU,
+/*035f*/ 0x10020275U,
+/*0360*/ 0x18010275U,
+/*0361*/ 0xffffffffU,
+/*0362*/ 0x00020276U,
+/*0363*/ 0x08080276U,
+/*0364*/ 0x10080276U,
+/*0365*/ 0x18080276U,
+/*0366*/ 0x00080277U,
+/*0367*/ 0x08080277U,
+/*0368*/ 0x10080277U,
+/*0369*/ 0xffffffffU,
+/*036a*/ 0x18080277U,
+/*036b*/ 0x00080278U,
+/*036c*/ 0x08080278U,
+/*036d*/ 0x10080278U,
+/*036e*/ 0x18080278U,
+/*036f*/ 0x00080279U,
+/*0370*/ 0xffffffffU,
+/*0371*/ 0x08080279U,
+/*0372*/ 0x10080279U,
+/*0373*/ 0x18080279U,
+/*0374*/ 0x0008027aU,
+/*0375*/ 0x0808027aU,
+/*0376*/ 0x1008027aU,
+/*0377*/ 0xffffffffU,
+/*0378*/ 0x1808027aU,
+/*0379*/ 0x0008027bU,
+/*037a*/ 0x0808027bU,
+/*037b*/ 0x1008027bU,
+/*037c*/ 0x1808027bU,
+/*037d*/ 0x0008027cU,
+/*037e*/ 0x0808027cU,
+/*037f*/ 0xffffffffU,
+/*0380*/ 0x1008027cU,
+/*0381*/ 0x1808027cU,
+/*0382*/ 0x0008027dU,
+/*0383*/ 0x0808027dU,
+/*0384*/ 0x1008027dU,
+/*0385*/ 0x1808027dU,
+/*0386*/ 0xffffffffU,
+/*0387*/ 0x0008027eU,
+/*0388*/ 0x0808027eU,
+/*0389*/ 0x1008027eU,
+/*038a*/ 0x1808027eU,
+/*038b*/ 0x0008027fU,
+/*038c*/ 0x0808027fU,
+/*038d*/ 0xffffffffU,
+/*038e*/ 0x1008027fU,
+/*038f*/ 0x1808027fU,
+/*0390*/ 0x00080280U,
+/*0391*/ 0x08080280U,
+/*0392*/ 0x10080280U,
+/*0393*/ 0x18080280U,
+/*0394*/ 0x00080281U,
+/*0395*/ 0xffffffffU,
+/*0396*/ 0x08080281U,
+/*0397*/ 0x10080281U,
+/*0398*/ 0x18080281U,
+/*0399*/ 0x00080282U,
+/*039a*/ 0x08080282U,
+/*039b*/ 0x10080282U,
+/*039c*/ 0xffffffffU,
+/*039d*/ 0x18080282U,
+/*039e*/ 0x00080283U,
+/*039f*/ 0x08080283U,
+/*03a0*/ 0x10080283U,
+/*03a1*/ 0x18080283U,
+/*03a2*/ 0x00080284U,
+/*03a3*/ 0xffffffffU,
+/*03a4*/ 0x08080284U,
+/*03a5*/ 0x10080284U,
+/*03a6*/ 0x18080284U,
+/*03a7*/ 0x00080285U,
+/*03a8*/ 0x08080285U,
+/*03a9*/ 0x10080285U,
+/*03aa*/ 0x18080285U,
+/*03ab*/ 0xffffffffU,
+/*03ac*/ 0x00080286U,
+/*03ad*/ 0x08080286U,
+/*03ae*/ 0x10080286U,
+/*03af*/ 0x18080286U,
+/*03b0*/ 0x00080287U,
+/*03b1*/ 0x08080287U,
+/*03b2*/ 0xffffffffU,
+/*03b3*/ 0x10080287U,
+/*03b4*/ 0x18080287U,
+/*03b5*/ 0x00080288U,
+/*03b6*/ 0x08080288U,
+/*03b7*/ 0x10080288U,
+/*03b8*/ 0x18080288U,
+/*03b9*/ 0xffffffffU,
+/*03ba*/ 0x00080289U,
+/*03bb*/ 0x08020289U,
+/*03bc*/ 0x10030289U,
+/*03bd*/ 0x000a028aU,
+/*03be*/ 0x100a028aU,
+/*03bf*/ 0x000a028bU,
+/*03c0*/ 0x1005028bU,
+/*03c1*/ 0x1804028bU,
+/*03c2*/ 0x0008028cU,
+/*03c3*/ 0x0808028cU,
+/*03c4*/ 0x1006028cU,
+/*03c5*/ 0x1806028cU,
+/*03c6*/ 0x0011028dU,
+/*03c7*/ 0x1808028dU,
+/*03c8*/ 0x0004028eU,
+/*03c9*/ 0x0806028eU,
+/*03ca*/ 0xffffffffU,
+/*03cb*/ 0x1006028eU,
+/*03cc*/ 0x1808028eU,
+/*03cd*/ 0xffffffffU,
+/*03ce*/ 0x0004028fU,
+/*03cf*/ 0x0808028fU,
+/*03d0*/ 0x1008028fU,
+/*03d1*/ 0x1806028fU,
+/*03d2*/ 0x00060290U,
+/*03d3*/ 0x08110290U,
+/*03d4*/ 0x00080291U,
+/*03d5*/ 0x08040291U,
+/*03d6*/ 0x10060291U,
+/*03d7*/ 0xffffffffU,
+/*03d8*/ 0x18060291U,
+/*03d9*/ 0x00080292U,
+/*03da*/ 0xffffffffU,
+/*03db*/ 0x08040292U,
+/*03dc*/ 0x10080292U,
+/*03dd*/ 0x18080292U,
+/*03de*/ 0x00060293U,
+/*03df*/ 0x08060293U,
+/*03e0*/ 0x00110294U,
+/*03e1*/ 0x18080294U,
+/*03e2*/ 0x00040295U,
+/*03e3*/ 0x08060295U,
+/*03e4*/ 0xffffffffU,
+/*03e5*/ 0x10060295U,
+/*03e6*/ 0x18080295U,
+/*03e7*/ 0xffffffffU,
+/*03e8*/ 0x00040296U,
+/*03e9*/ 0x08040296U,
+/*03ea*/ 0x10040296U,
+/*03eb*/ 0x18040296U,
+/*03ec*/ 0x00040297U,
+/*03ed*/ 0x08040297U,
+/*03ee*/ 0x10040297U,
+/*03ef*/ 0x18040297U,
+/*03f0*/ 0x00040298U,
+/*03f1*/ 0x08040298U,
+/*03f2*/ 0x10040298U,
+/*03f3*/ 0x18040298U,
+/*03f4*/ 0x00040299U,
+/*03f5*/ 0x08040299U,
+/*03f6*/ 0x10040299U,
+/*03f7*/ 0x18040299U,
+/*03f8*/ 0x0004029aU,
+/*03f9*/ 0x0804029aU,
+/*03fa*/ 0x1004029aU,
+/*03fb*/ 0x1804029aU,
+/*03fc*/ 0x0011029bU,
+/*03fd*/ 0x0010029cU,
+/*03fe*/ 0x0011029dU,
+/*03ff*/ 0x0020029eU,
+/*0400*/ 0x0020029fU,
+/*0401*/ 0x002002a0U,
+/*0402*/ 0x002002a1U,
+/*0403*/ 0x002002a2U,
+/*0404*/ 0x002002a3U,
+/*0405*/ 0x002002a4U,
+/*0406*/ 0x002002a5U,
+/*0407*/ 0x002002a6U,
+/*0408*/ 0x000202a7U,
+/*0409*/ 0x080502a7U,
+/*040a*/ 0x100502a7U,
+/*040b*/ 0xffffffffU,
+/*040c*/ 0xffffffffU,
+/*040d*/ 0xffffffffU,
+/*040e*/ 0xffffffffU,
+/*040f*/ 0xffffffffU,
+/*0410*/ 0xffffffffU,
+/*0411*/ 0xffffffffU,
+/*0412*/ 0xffffffffU,
+/*0413*/ 0xffffffffU,
+/*0414*/ 0xffffffffU,
+/*0415*/ 0xffffffffU,
+/*0416*/ 0xffffffffU,
+/*0417*/ 0xffffffffU,
+/*0418*/ 0xffffffffU,
+/*0419*/ 0xffffffffU,
+/*041a*/ 0xffffffffU,
+/*041b*/ 0xffffffffU,
+/*041c*/ 0xffffffffU,
+/*041d*/ 0xffffffffU,
+/*041e*/ 0xffffffffU,
+/*041f*/ 0xffffffffU,
+/*0420*/ 0xffffffffU,
+/*0421*/ 0xffffffffU,
+/*0422*/ 0xffffffffU,
+/*0423*/ 0xffffffffU,
+/*0424*/ 0xffffffffU,
+/*0425*/ 0xffffffffU,
+/*0426*/ 0xffffffffU,
+/*0427*/ 0x180102a7U,
+/*0428*/ 0x000402a8U,
+/*0429*/ 0x081002a8U,
+/*042a*/ 0x002002a9U,
+/*042b*/ 0x001002aaU,
+/*042c*/ 0x002002abU,
+/*042d*/ 0x001002acU,
+/*042e*/ 0x002002adU,
+/*042f*/ 0x000702aeU,
+/*0430*/ 0x080102aeU,
+/*0431*/ 0x100202aeU,
+/*0432*/ 0x180602aeU,
+/*0433*/ 0x000102afU,
+/*0434*/ 0x080102afU,
+/*0435*/ 0x002002b0U,
+/*0436*/ 0x000202b1U,
+/*0437*/ 0x002002b2U,
+/*0438*/ 0x002002b3U,
+/*0439*/ 0xffffffffU,
+/*043a*/ 0xffffffffU,
+/*043b*/ 0xffffffffU,
+/*043c*/ 0xffffffffU,
+/*043d*/ 0xffffffffU,
+/*043e*/ 0xffffffffU,
+/*043f*/ 0xffffffffU,
+/*0440*/ 0xffffffffU,
+/*0441*/ 0xffffffffU,
+/*0442*/ 0xffffffffU,
+/*0443*/ 0xffffffffU,
+/*0444*/ 0xffffffffU,
+/*0445*/ 0xffffffffU,
+/*0446*/ 0xffffffffU,
+/*0447*/ 0xffffffffU,
+/*0448*/ 0xffffffffU,
+/*0449*/ 0xffffffffU,
+/*044a*/ 0xffffffffU,
+/*044b*/ 0xffffffffU,
+/*044c*/ 0xffffffffU,
+/*044d*/ 0xffffffffU,
+/*044e*/ 0xffffffffU,
+/*044f*/ 0xffffffffU,
+/*0450*/ 0xffffffffU,
+/*0451*/ 0xffffffffU,
+/*0452*/ 0xffffffffU,
+/*0453*/ 0xffffffffU,
+/*0454*/ 0xffffffffU,
+/*0455*/ 0xffffffffU,
+/*0456*/ 0xffffffffU,
+/*0457*/ 0xffffffffU,
+/*0458*/ 0xffffffffU,
+/*0459*/ 0xffffffffU,
+/*045a*/ 0xffffffffU,
+/*045b*/ 0xffffffffU,
+/*045c*/ 0xffffffffU,
+/*045d*/ 0xffffffffU,
+/*045e*/ 0xffffffffU,
+/*045f*/ 0x000402b4U,
+/*0460*/ 0xffffffffU,
+/*0461*/ 0xffffffffU,
+/*0462*/ 0xffffffffU,
+/*0463*/ 0xffffffffU,
+/*0464*/ 0xffffffffU,
+/*0465*/ 0xffffffffU,
+/*0466*/ 0xffffffffU,
+/*0467*/ 0xffffffffU,
+/*0468*/ 0xffffffffU,
+/*0469*/ 0xffffffffU,
+/*046a*/ 0xffffffffU,
+/*046b*/ 0xffffffffU,
+/*046c*/ 0xffffffffU,
+/*046d*/ 0xffffffffU,
+/*046e*/ 0xffffffffU,
+/*046f*/ 0xffffffffU,
+/*0470*/ 0xffffffffU,
+/*0471*/ 0xffffffffU,
+/*0472*/ 0xffffffffU,
+/*0473*/ 0xffffffffU,
+/*0474*/ 0xffffffffU,
+/*0475*/ 0xffffffffU,
+/*0476*/ 0xffffffffU,
+/*0477*/ 0xffffffffU,
+/*0478*/ 0xffffffffU,
+/*0479*/ 0xffffffffU,
+/*047a*/ 0xffffffffU,
+/*047b*/ 0xffffffffU,
+/*047c*/ 0xffffffffU,
+/*047d*/ 0xffffffffU,
+/*047e*/ 0xffffffffU,
+/*047f*/ 0xffffffffU,
+/*0480*/ 0xffffffffU,
+/*0481*/ 0xffffffffU,
+/*0482*/ 0xffffffffU,
+/*0483*/ 0xffffffffU,
+/*0484*/ 0xffffffffU,
+/*0485*/ 0xffffffffU,
+/*0486*/ 0xffffffffU,
+/*0487*/ 0xffffffffU,
+/*0488*/ 0xffffffffU,
+/*0489*/ 0xffffffffU,
+/*048a*/ 0xffffffffU,
+/*048b*/ 0xffffffffU,
+/*048c*/ 0xffffffffU,
+/*048d*/ 0xffffffffU,
+/*048e*/ 0xffffffffU,
+/*048f*/ 0xffffffffU,
+/*0490*/ 0xffffffffU,
+/*0491*/ 0xffffffffU,
+/*0492*/ 0xffffffffU,
+/*0493*/ 0xffffffffU,
+/*0494*/ 0xffffffffU,
+ },
+ {
+/*0000*/ 0x00200800U,
+/*0001*/ 0x00040801U,
+/*0002*/ 0x080b0801U,
+/*0003*/ 0xffffffffU,
+/*0004*/ 0xffffffffU,
+/*0005*/ 0x18010801U,
+/*0006*/ 0x00050802U,
+/*0007*/ 0x08050802U,
+/*0008*/ 0x10050802U,
+/*0009*/ 0x18050802U,
+/*000a*/ 0x00050803U,
+/*000b*/ 0x08050803U,
+/*000c*/ 0x10050803U,
+/*000d*/ 0x18050803U,
+/*000e*/ 0x00050804U,
+/*000f*/ 0x08040804U,
+/*0010*/ 0x10030804U,
+/*0011*/ 0x00180805U,
+/*0012*/ 0x18030805U,
+/*0013*/ 0x00180806U,
+/*0014*/ 0x18020806U,
+/*0015*/ 0x00010807U,
+/*0016*/ 0x08020807U,
+/*0017*/ 0x10010807U,
+/*0018*/ 0x18010807U,
+/*0019*/ 0x00020808U,
+/*001a*/ 0x08040808U,
+/*001b*/ 0x10040808U,
+/*001c*/ 0x18040808U,
+/*001d*/ 0x000a0809U,
+/*001e*/ 0x10040809U,
+/*001f*/ 0xffffffffU,
+/*0020*/ 0xffffffffU,
+/*0021*/ 0x18070809U,
+/*0022*/ 0xffffffffU,
+/*0023*/ 0xffffffffU,
+/*0024*/ 0xffffffffU,
+/*0025*/ 0xffffffffU,
+/*0026*/ 0xffffffffU,
+/*0027*/ 0xffffffffU,
+/*0028*/ 0x000a080aU,
+/*0029*/ 0x1005080aU,
+/*002a*/ 0x1801080aU,
+/*002b*/ 0x0001080bU,
+/*002c*/ 0x0802080bU,
+/*002d*/ 0x1009080bU,
+/*002e*/ 0x0009080cU,
+/*002f*/ 0x1002080cU,
+/*0030*/ 0x0020080dU,
+/*0031*/ 0xffffffffU,
+/*0032*/ 0x0001080eU,
+/*0033*/ 0xffffffffU,
+/*0034*/ 0xffffffffU,
+/*0035*/ 0xffffffffU,
+/*0036*/ 0xffffffffU,
+/*0037*/ 0x0020080fU,
+/*0038*/ 0x00200810U,
+/*0039*/ 0x00200811U,
+/*003a*/ 0x00200812U,
+/*003b*/ 0x00030813U,
+/*003c*/ 0x08010813U,
+/*003d*/ 0x10030813U,
+/*003e*/ 0x18030813U,
+/*003f*/ 0x00040814U,
+/*0040*/ 0x08040814U,
+/*0041*/ 0x10040814U,
+/*0042*/ 0x18040814U,
+/*0043*/ 0x00010815U,
+/*0044*/ 0x08010815U,
+/*0045*/ 0x10060815U,
+/*0046*/ 0x18040815U,
+/*0047*/ 0xffffffffU,
+/*0048*/ 0x00060816U,
+/*0049*/ 0x08040816U,
+/*004a*/ 0x10060816U,
+/*004b*/ 0x18040816U,
+/*004c*/ 0x00020817U,
+/*004d*/ 0x08050817U,
+/*004e*/ 0x10080817U,
+/*004f*/ 0x00200818U,
+/*0050*/ 0x00060819U,
+/*0051*/ 0x08030819U,
+/*0052*/ 0x100b0819U,
+/*0053*/ 0x0004081aU,
+/*0054*/ 0x0804081aU,
+/*0055*/ 0x1004081aU,
+/*0056*/ 0xffffffffU,
+/*0057*/ 0x1801081aU,
+/*0058*/ 0x0009081bU,
+/*0059*/ 0x0020081cU,
+/*005a*/ 0x0020081dU,
+/*005b*/ 0x0020081eU,
+/*005c*/ 0x0020081fU,
+/*005d*/ 0x00100820U,
+/*005e*/ 0xffffffffU,
+/*005f*/ 0x10010820U,
+/*0060*/ 0x18060820U,
+/*0061*/ 0x00080821U,
+/*0062*/ 0x00200822U,
+/*0063*/ 0xffffffffU,
+/*0064*/ 0x000a0823U,
+/*0065*/ 0x10060823U,
+/*0066*/ 0x18070823U,
+/*0067*/ 0x00080824U,
+/*0068*/ 0x08080824U,
+/*0069*/ 0x100a0824U,
+/*006a*/ 0x00070825U,
+/*006b*/ 0x08080825U,
+/*006c*/ 0x10080825U,
+/*006d*/ 0x18030825U,
+/*006e*/ 0x000a0826U,
+/*006f*/ 0x100a0826U,
+/*0070*/ 0x00110827U,
+/*0071*/ 0x00090828U,
+/*0072*/ 0x10090828U,
+/*0073*/ 0x00100829U,
+/*0074*/ 0x100e0829U,
+/*0075*/ 0x000e082aU,
+/*0076*/ 0x100c082aU,
+/*0077*/ 0x000a082bU,
+/*0078*/ 0x100a082bU,
+/*0079*/ 0x0002082cU,
+/*007a*/ 0x0020082dU,
+/*007b*/ 0x000b082eU,
+/*007c*/ 0x100b082eU,
+/*007d*/ 0x0020082fU,
+/*007e*/ 0x00120830U,
+/*007f*/ 0x00200831U,
+/*0080*/ 0x00200832U,
+/*0081*/ 0xffffffffU,
+/*0082*/ 0xffffffffU,
+/*0083*/ 0x00010833U,
+/*0084*/ 0x08010833U,
+/*0085*/ 0x10080833U,
+/*0086*/ 0x000c0834U,
+/*0087*/ 0x100c0834U,
+/*0088*/ 0x000c0835U,
+/*0089*/ 0x100c0835U,
+/*008a*/ 0x000c0836U,
+/*008b*/ 0x100c0836U,
+/*008c*/ 0x000c0837U,
+/*008d*/ 0x100c0837U,
+/*008e*/ 0x000c0838U,
+/*008f*/ 0x100c0838U,
+/*0090*/ 0x000c0839U,
+/*0091*/ 0x100b0839U,
+/*0092*/ 0xffffffffU,
+/*0093*/ 0xffffffffU,
+/*0094*/ 0x000b083aU,
+/*0095*/ 0x100b083aU,
+/*0096*/ 0x000b083bU,
+/*0097*/ 0x100b083bU,
+/*0098*/ 0x000b083cU,
+/*0099*/ 0x100b083cU,
+/*009a*/ 0x000b083dU,
+/*009b*/ 0x100b083dU,
+/*009c*/ 0x000b083eU,
+/*009d*/ 0x100a083eU,
+/*009e*/ 0xffffffffU,
+/*009f*/ 0x000a083fU,
+/*00a0*/ 0x100a083fU,
+/*00a1*/ 0x000a0840U,
+/*00a2*/ 0x100a0840U,
+/*00a3*/ 0x000a0841U,
+/*00a4*/ 0x100a0841U,
+/*00a5*/ 0x000a0842U,
+/*00a6*/ 0x100a0842U,
+/*00a7*/ 0x000a0843U,
+/*00a8*/ 0x100a0843U,
+/*00a9*/ 0x000a0844U,
+/*00aa*/ 0x100a0844U,
+/*00ab*/ 0x000a0845U,
+/*00ac*/ 0x100a0845U,
+/*00ad*/ 0x000a0846U,
+/*00ae*/ 0x100a0846U,
+/*00af*/ 0x000a0847U,
+/*00b0*/ 0x100a0847U,
+/*00b1*/ 0x000a0848U,
+/*00b2*/ 0x100a0848U,
+/*00b3*/ 0x000a0849U,
+/*00b4*/ 0x100a0849U,
+/*00b5*/ 0x000a084aU,
+/*00b6*/ 0x100a084aU,
+/*00b7*/ 0x000a084bU,
+/*00b8*/ 0x100a084bU,
+/*00b9*/ 0x000a084cU,
+/*00ba*/ 0x100a084cU,
+/*00bb*/ 0x0004084dU,
+/*00bc*/ 0x0803084dU,
+/*00bd*/ 0x100a084dU,
+/*00be*/ 0x000a084eU,
+/*00bf*/ 0x1001084eU,
+/*00c0*/ 0x000a084fU,
+/*00c1*/ 0x1004084fU,
+/*00c2*/ 0x000b0850U,
+/*00c3*/ 0x100a0850U,
+/*00c4*/ 0xffffffffU,
+/*00c5*/ 0x00080851U,
+/*00c6*/ 0x08080851U,
+/*00c7*/ 0x10080851U,
+/*00c8*/ 0x18080851U,
+/*00c9*/ 0x00080852U,
+/*00ca*/ 0xffffffffU,
+/*00cb*/ 0x08080852U,
+/*00cc*/ 0x10010852U,
+/*00cd*/ 0x18080852U,
+/*00ce*/ 0x00080853U,
+/*00cf*/ 0x08020853U,
+/*00d0*/ 0x10020853U,
+/*00d1*/ 0x18040853U,
+/*00d2*/ 0x00040854U,
+/*00d3*/ 0xffffffffU,
+/*00d4*/ 0x08040854U,
+/*00d5*/ 0x100a0854U,
+/*00d6*/ 0x00060855U,
+/*00d7*/ 0x08080855U,
+/*00d8*/ 0xffffffffU,
+/*00d9*/ 0x10040855U,
+/*00da*/ 0x18040855U,
+/*00db*/ 0x00050856U,
+/*00dc*/ 0x08040856U,
+/*00dd*/ 0x10050856U,
+/*00de*/ 0x000a0857U,
+/*00df*/ 0x100a0857U,
+/*00e0*/ 0x00080858U,
+/*00e1*/ 0xffffffffU,
+/*00e2*/ 0x08040858U,
+/*00e3*/ 0xffffffffU,
+/*00e4*/ 0xffffffffU,
+/*00e5*/ 0x00050a00U,
+/*00e6*/ 0x08050a00U,
+/*00e7*/ 0x10050a00U,
+/*00e8*/ 0x18050a00U,
+/*00e9*/ 0x00050a01U,
+/*00ea*/ 0x08050a01U,
+/*00eb*/ 0x100b0a01U,
+/*00ec*/ 0x00010a02U,
+/*00ed*/ 0x08030a02U,
+/*00ee*/ 0x00200a03U,
+/*00ef*/ 0xffffffffU,
+/*00f0*/ 0x00030a04U,
+/*00f1*/ 0x080a0a04U,
+/*00f2*/ 0xffffffffU,
+/*00f3*/ 0xffffffffU,
+/*00f4*/ 0x18030a04U,
+/*00f5*/ 0x00030a05U,
+/*00f6*/ 0x08010a05U,
+/*00f7*/ 0x10010a05U,
+/*00f8*/ 0x18060a05U,
+/*00f9*/ 0xffffffffU,
+/*00fa*/ 0xffffffffU,
+/*00fb*/ 0xffffffffU,
+/*00fc*/ 0x00020a06U,
+/*00fd*/ 0x08030a06U,
+/*00fe*/ 0x10010a06U,
+/*00ff*/ 0x000f0a07U,
+/*0100*/ 0x00200a08U,
+/*0101*/ 0x00200a09U,
+/*0102*/ 0x000b0a0aU,
+/*0103*/ 0x100b0a0aU,
+/*0104*/ 0x000b0a0bU,
+/*0105*/ 0xffffffffU,
+/*0106*/ 0xffffffffU,
+/*0107*/ 0x00180a0cU,
+/*0108*/ 0x00180a0dU,
+/*0109*/ 0x00180a0eU,
+/*010a*/ 0x00180a0fU,
+/*010b*/ 0x18040a0fU,
+/*010c*/ 0x00020a10U,
+/*010d*/ 0x08020a10U,
+/*010e*/ 0x10040a10U,
+/*010f*/ 0x18040a10U,
+/*0110*/ 0x00010a11U,
+/*0111*/ 0x08010a11U,
+/*0112*/ 0x10010a11U,
+/*0113*/ 0x18030a11U,
+/*0114*/ 0x00200a12U,
+/*0115*/ 0x00200a13U,
+/*0116*/ 0xffffffffU,
+/*0117*/ 0x00140a14U,
+/*0118*/ 0x00140a15U,
+/*0119*/ 0x00140a16U,
+/*011a*/ 0x00140a17U,
+/*011b*/ 0x00140a18U,
+/*011c*/ 0x00140a19U,
+/*011d*/ 0x00140a1aU,
+/*011e*/ 0x00140a1bU,
+/*011f*/ 0x001e0a1cU,
+/*0120*/ 0x000a0a1dU,
+/*0121*/ 0x10060a1dU,
+/*0122*/ 0x18060a1dU,
+/*0123*/ 0x00060a1eU,
+/*0124*/ 0xffffffffU,
+/*0125*/ 0x08060a1eU,
+/*0126*/ 0x00080a1fU,
+/*0127*/ 0x080b0a1fU,
+/*0128*/ 0x000b0a20U,
+/*0129*/ 0x100b0a20U,
+/*012a*/ 0x000b0a21U,
+/*012b*/ 0x100b0a21U,
+/*012c*/ 0x000b0a22U,
+/*012d*/ 0x10040a22U,
+/*012e*/ 0x000a0a23U,
+/*012f*/ 0x10060a23U,
+/*0130*/ 0x18080a23U,
+/*0131*/ 0xffffffffU,
+/*0132*/ 0x00040a24U,
+/*0133*/ 0xffffffffU,
+/*0134*/ 0xffffffffU,
+/*0135*/ 0x00010b80U,
+/*0136*/ 0x08020b80U,
+/*0137*/ 0x10050b80U,
+/*0138*/ 0x18050b80U,
+/*0139*/ 0x00050b81U,
+/*013a*/ 0x08050b81U,
+/*013b*/ 0x100b0b81U,
+/*013c*/ 0x00050b82U,
+/*013d*/ 0x08010b82U,
+/*013e*/ 0x10010b82U,
+/*013f*/ 0xffffffffU,
+/*0140*/ 0x18010b82U,
+/*0141*/ 0x00010b83U,
+/*0142*/ 0x08040b83U,
+/*0143*/ 0x100b0b83U,
+/*0144*/ 0x000b0b84U,
+/*0145*/ 0xffffffffU,
+/*0146*/ 0x10040b84U,
+/*0147*/ 0x000b0b85U,
+/*0148*/ 0x10040b85U,
+/*0149*/ 0x18010b85U,
+/*014a*/ 0x00010b86U,
+/*014b*/ 0x08010b86U,
+/*014c*/ 0x00200b87U,
+/*014d*/ 0x00200b88U,
+/*014e*/ 0x00080b89U,
+/*014f*/ 0x080a0b89U,
+/*0150*/ 0x18050b89U,
+/*0151*/ 0x000a0b8aU,
+/*0152*/ 0x10030b8aU,
+/*0153*/ 0x18030b8aU,
+/*0154*/ 0x00010b8bU,
+/*0155*/ 0x08020b8bU,
+/*0156*/ 0x10010b8bU,
+/*0157*/ 0x18010b8bU,
+/*0158*/ 0x00010b8cU,
+/*0159*/ 0x08030b8cU,
+/*015a*/ 0xffffffffU,
+/*015b*/ 0x10040b8cU,
+/*015c*/ 0x18040b8cU,
+/*015d*/ 0x00040b8dU,
+/*015e*/ 0x08040b8dU,
+/*015f*/ 0xffffffffU,
+/*0160*/ 0xffffffffU,
+/*0161*/ 0xffffffffU,
+/*0162*/ 0xffffffffU,
+/*0163*/ 0xffffffffU,
+/*0164*/ 0xffffffffU,
+/*0165*/ 0xffffffffU,
+/*0166*/ 0xffffffffU,
+/*0167*/ 0xffffffffU,
+/*0168*/ 0x000d0b8eU,
+/*0169*/ 0x100d0b8eU,
+/*016a*/ 0x000d0b8fU,
+/*016b*/ 0x00050b90U,
+/*016c*/ 0x00010b91U,
+/*016d*/ 0x080e0b91U,
+/*016e*/ 0x000e0b92U,
+/*016f*/ 0x100e0b92U,
+/*0170*/ 0x000e0b93U,
+/*0171*/ 0x100e0b93U,
+/*0172*/ 0x00040b94U,
+/*0173*/ 0x08040b94U,
+/*0174*/ 0x10040b94U,
+/*0175*/ 0x18040b94U,
+/*0176*/ 0x00040b95U,
+/*0177*/ 0x080b0b95U,
+/*0178*/ 0x000b0b96U,
+/*0179*/ 0x100b0b96U,
+/*017a*/ 0x000b0b97U,
+/*017b*/ 0xffffffffU,
+/*017c*/ 0xffffffffU,
+/*017d*/ 0xffffffffU,
+/*017e*/ 0xffffffffU,
+/*017f*/ 0x000d0b98U,
+/*0180*/ 0x100d0b98U,
+/*0181*/ 0x000d0b99U,
+/*0182*/ 0x10100b99U,
+/*0183*/ 0x10080b8dU,
+/*0184*/ 0x18080b8dU,
+/*0185*/ 0x00100b9aU,
+/*0186*/ 0x10100b9aU,
+/*0187*/ 0x00100b9bU,
+/*0188*/ 0x10100b9bU,
+/*0189*/ 0x00100b9cU,
+/*018a*/ 0x10030b9cU,
+/*018b*/ 0x18040b9cU,
+/*018c*/ 0x00010b9dU,
+/*018d*/ 0x08040b9dU,
+/*018e*/ 0xffffffffU,
+/*018f*/ 0xffffffffU,
+/*0190*/ 0x10010b9dU,
+/*0191*/ 0x00140b9eU,
+/*0192*/ 0x000a0b9fU,
+/*0193*/ 0x100c0b9fU,
+/*0194*/ 0x00120ba0U,
+/*0195*/ 0x00140ba1U,
+/*0196*/ 0x00120ba2U,
+/*0197*/ 0x00110ba3U,
+/*0198*/ 0x00110ba4U,
+/*0199*/ 0x00120ba5U,
+/*019a*/ 0x00120ba6U,
+/*019b*/ 0x00120ba7U,
+/*019c*/ 0x00120ba8U,
+/*019d*/ 0x00120ba9U,
+/*019e*/ 0x00120baaU,
+/*019f*/ 0x00120babU,
+/*01a0*/ 0x00120bacU,
+/*01a1*/ 0xffffffffU,
+/*01a2*/ 0xffffffffU,
+/*01a3*/ 0x00190badU,
+/*01a4*/ 0x00190baeU,
+/*01a5*/ 0x00200bafU,
+/*01a6*/ 0x00170bb0U,
+/*01a7*/ 0x18080bb0U,
+/*01a8*/ 0x00010bb1U,
+/*01a9*/ 0x08010bb1U,
+/*01aa*/ 0x00200bb2U,
+/*01ab*/ 0x00080bb3U,
+/*01ac*/ 0xffffffffU,
+/*01ad*/ 0x08030bb3U,
+/*01ae*/ 0x00180bb4U,
+/*01af*/ 0x00180bb5U,
+/*01b0*/ 0xffffffffU,
+/*01b1*/ 0xffffffffU,
+/*01b2*/ 0xffffffffU,
+/*01b3*/ 0xffffffffU,
+/*01b4*/ 0xffffffffU,
+/*01b5*/ 0xffffffffU,
+/*01b6*/ 0xffffffffU,
+/*01b7*/ 0xffffffffU,
+/*01b8*/ 0xffffffffU,
+/*01b9*/ 0xffffffffU,
+/*01ba*/ 0xffffffffU,
+/*01bb*/ 0xffffffffU,
+/*01bc*/ 0xffffffffU,
+/*01bd*/ 0xffffffffU,
+/*01be*/ 0xffffffffU,
+/*01bf*/ 0x00100bb6U,
+/*01c0*/ 0x10010bb6U,
+/*01c1*/ 0x18010bb6U,
+/*01c2*/ 0x00050bb7U,
+/*01c3*/ 0x00200bb8U,
+/*01c4*/ 0x00090bb9U,
+/*01c5*/ 0xffffffffU,
+/*01c6*/ 0xffffffffU,
+/*01c7*/ 0x00200bbaU,
+/*01c8*/ 0x00040bbbU,
+/*01c9*/ 0x08100bbbU,
+/*01ca*/ 0x18060bbbU,
+/*01cb*/ 0x00100bbcU,
+/*01cc*/ 0xffffffffU,
+/*01cd*/ 0x10080bbcU,
+/*01ce*/ 0xffffffffU,
+/*01cf*/ 0xffffffffU,
+/*01d0*/ 0xffffffffU,
+/*01d1*/ 0x18030bbcU,
+/*01d2*/ 0x00020bbdU,
+/*01d3*/ 0xffffffffU,
+/*01d4*/ 0x00200bbeU,
+/*01d5*/ 0x000b0bbfU,
+/*01d6*/ 0xffffffffU,
+/*01d7*/ 0xffffffffU,
+/*01d8*/ 0xffffffffU,
+/*01d9*/ 0x10020bbfU,
+/*01da*/ 0xffffffffU,
+/*01db*/ 0xffffffffU,
+/*01dc*/ 0xffffffffU,
+/*01dd*/ 0xffffffffU,
+/*01de*/ 0x00010200U,
+/*01df*/ 0x08040200U,
+/*01e0*/ 0x10100200U,
+/*01e1*/ 0x00010201U,
+/*01e2*/ 0x08010201U,
+/*01e3*/ 0xffffffffU,
+/*01e4*/ 0xffffffffU,
+/*01e5*/ 0x10100201U,
+/*01e6*/ 0xffffffffU,
+/*01e7*/ 0xffffffffU,
+/*01e8*/ 0xffffffffU,
+/*01e9*/ 0xffffffffU,
+/*01ea*/ 0xffffffffU,
+/*01eb*/ 0xffffffffU,
+/*01ec*/ 0xffffffffU,
+/*01ed*/ 0xffffffffU,
+/*01ee*/ 0xffffffffU,
+/*01ef*/ 0x00200202U,
+/*01f0*/ 0x00100203U,
+/*01f1*/ 0x00200204U,
+/*01f2*/ 0x00100205U,
+/*01f3*/ 0x00200206U,
+/*01f4*/ 0x00100207U,
+/*01f5*/ 0x10100207U,
+/*01f6*/ 0x00200208U,
+/*01f7*/ 0x00200209U,
+/*01f8*/ 0x0020020aU,
+/*01f9*/ 0x0020020bU,
+/*01fa*/ 0x0010020cU,
+/*01fb*/ 0x0020020dU,
+/*01fc*/ 0x0020020eU,
+/*01fd*/ 0x0020020fU,
+/*01fe*/ 0x00200210U,
+/*01ff*/ 0x00100211U,
+/*0200*/ 0x00200212U,
+/*0201*/ 0x00200213U,
+/*0202*/ 0x00200214U,
+/*0203*/ 0x00200215U,
+/*0204*/ 0x00090216U,
+/*0205*/ 0x10010216U,
+/*0206*/ 0x00200217U,
+/*0207*/ 0x00050218U,
+/*0208*/ 0x08010218U,
+/*0209*/ 0x10080218U,
+/*020a*/ 0x18080218U,
+/*020b*/ 0x001e0219U,
+/*020c*/ 0x001e021aU,
+/*020d*/ 0x001e021bU,
+/*020e*/ 0x001e021cU,
+/*020f*/ 0x001e021dU,
+/*0210*/ 0x001e021eU,
+/*0211*/ 0x001e021fU,
+/*0212*/ 0x001e0220U,
+/*0213*/ 0x001e0221U,
+/*0214*/ 0x001e0222U,
+/*0215*/ 0x001e0223U,
+/*0216*/ 0x001e0224U,
+/*0217*/ 0x001e0225U,
+/*0218*/ 0x001e0226U,
+/*0219*/ 0x001e0227U,
+/*021a*/ 0x001e0228U,
+/*021b*/ 0x00010229U,
+/*021c*/ 0x08010229U,
+/*021d*/ 0x10010229U,
+/*021e*/ 0x18040229U,
+/*021f*/ 0x0008022aU,
+/*0220*/ 0x0808022aU,
+/*0221*/ 0x1008022aU,
+/*0222*/ 0x1804022aU,
+/*0223*/ 0x0005022bU,
+/*0224*/ 0x0806022bU,
+/*0225*/ 0x1007022bU,
+/*0226*/ 0x1805022bU,
+/*0227*/ 0x0006022cU,
+/*0228*/ 0x0807022cU,
+/*0229*/ 0x1005022cU,
+/*022a*/ 0x1806022cU,
+/*022b*/ 0x0007022dU,
+/*022c*/ 0x0802022dU,
+/*022d*/ 0x1001022dU,
+/*022e*/ 0xffffffffU,
+/*022f*/ 0x000a022eU,
+/*0230*/ 0x1010022eU,
+/*0231*/ 0x000a022fU,
+/*0232*/ 0x1010022fU,
+/*0233*/ 0x000a0230U,
+/*0234*/ 0x10100230U,
+/*0235*/ 0xffffffffU,
+/*0236*/ 0x00100231U,
+/*0237*/ 0xffffffffU,
+/*0238*/ 0xffffffffU,
+/*0239*/ 0x10010231U,
+/*023a*/ 0x18010231U,
+/*023b*/ 0x00010232U,
+/*023c*/ 0x08010232U,
+/*023d*/ 0x10010232U,
+/*023e*/ 0x18010232U,
+/*023f*/ 0x00020233U,
+/*0240*/ 0x08020233U,
+/*0241*/ 0x10020233U,
+/*0242*/ 0x18020233U,
+/*0243*/ 0x00020234U,
+/*0244*/ 0x08030234U,
+/*0245*/ 0x10010234U,
+/*0246*/ 0x18010234U,
+/*0247*/ 0x00010235U,
+/*0248*/ 0x08010235U,
+/*0249*/ 0xffffffffU,
+/*024a*/ 0x10020235U,
+/*024b*/ 0x18010235U,
+/*024c*/ 0x00010236U,
+/*024d*/ 0xffffffffU,
+/*024e*/ 0x08020236U,
+/*024f*/ 0x10010236U,
+/*0250*/ 0x18010236U,
+/*0251*/ 0xffffffffU,
+/*0252*/ 0x00020237U,
+/*0253*/ 0x08010237U,
+/*0254*/ 0x10010237U,
+/*0255*/ 0xffffffffU,
+/*0256*/ 0x18020237U,
+/*0257*/ 0x00070238U,
+/*0258*/ 0x08010238U,
+/*0259*/ 0x10010238U,
+/*025a*/ 0x18010238U,
+/*025b*/ 0x00010239U,
+/*025c*/ 0x08010239U,
+/*025d*/ 0x10010239U,
+/*025e*/ 0xffffffffU,
+/*025f*/ 0x18010239U,
+/*0260*/ 0x0004023aU,
+/*0261*/ 0x0804023aU,
+/*0262*/ 0x1004023aU,
+/*0263*/ 0x1801023aU,
+/*0264*/ 0x0002023bU,
+/*0265*/ 0x0806023bU,
+/*0266*/ 0x1006023bU,
+/*0267*/ 0xffffffffU,
+/*0268*/ 0xffffffffU,
+/*0269*/ 0xffffffffU,
+/*026a*/ 0x1802023bU,
+/*026b*/ 0x0010023cU,
+/*026c*/ 0x1001023cU,
+/*026d*/ 0x1801023cU,
+/*026e*/ 0xffffffffU,
+/*026f*/ 0x0004023dU,
+/*0270*/ 0x0801023dU,
+/*0271*/ 0x1004023dU,
+/*0272*/ 0x1802023dU,
+/*0273*/ 0x0008023eU,
+/*0274*/ 0xffffffffU,
+/*0275*/ 0xffffffffU,
+/*0276*/ 0xffffffffU,
+/*0277*/ 0x080a023eU,
+/*0278*/ 0x0020023fU,
+/*0279*/ 0x00200240U,
+/*027a*/ 0x00050241U,
+/*027b*/ 0x08010241U,
+/*027c*/ 0x10050241U,
+/*027d*/ 0x18080241U,
+/*027e*/ 0x00010242U,
+/*027f*/ 0x08080242U,
+/*0280*/ 0x10010242U,
+/*0281*/ 0x18080242U,
+/*0282*/ 0x00010243U,
+/*0283*/ 0x08040243U,
+/*0284*/ 0x10040243U,
+/*0285*/ 0x18040243U,
+/*0286*/ 0x00040244U,
+/*0287*/ 0x08040244U,
+/*0288*/ 0x10040244U,
+/*0289*/ 0x18040244U,
+/*028a*/ 0x00040245U,
+/*028b*/ 0x08040245U,
+/*028c*/ 0x10040245U,
+/*028d*/ 0x18010245U,
+/*028e*/ 0x00040246U,
+/*028f*/ 0x08040246U,
+/*0290*/ 0x10040246U,
+/*0291*/ 0x18040246U,
+/*0292*/ 0x00040247U,
+/*0293*/ 0x08040247U,
+/*0294*/ 0x10060247U,
+/*0295*/ 0x18060247U,
+/*0296*/ 0x00060248U,
+/*0297*/ 0x08060248U,
+/*0298*/ 0x10060248U,
+/*0299*/ 0x18060248U,
+/*029a*/ 0x00040249U,
+/*029b*/ 0x08010249U,
+/*029c*/ 0x10010249U,
+/*029d*/ 0x18020249U,
+/*029e*/ 0xffffffffU,
+/*029f*/ 0xffffffffU,
+/*02a0*/ 0xffffffffU,
+/*02a1*/ 0xffffffffU,
+/*02a2*/ 0xffffffffU,
+/*02a3*/ 0xffffffffU,
+/*02a4*/ 0xffffffffU,
+/*02a5*/ 0xffffffffU,
+/*02a6*/ 0x0004024aU,
+/*02a7*/ 0x0804024aU,
+/*02a8*/ 0x1001024aU,
+/*02a9*/ 0x1801024aU,
+/*02aa*/ 0xffffffffU,
+/*02ab*/ 0x0001024bU,
+/*02ac*/ 0x0801024bU,
+/*02ad*/ 0xffffffffU,
+/*02ae*/ 0x1001024bU,
+/*02af*/ 0x1801024bU,
+/*02b0*/ 0x0001024cU,
+/*02b1*/ 0x0804024cU,
+/*02b2*/ 0x1004024cU,
+/*02b3*/ 0x000a024dU,
+/*02b4*/ 0x0020024eU,
+/*02b5*/ 0x0004024fU,
+/*02b6*/ 0x0808024fU,
+/*02b7*/ 0xffffffffU,
+/*02b8*/ 0xffffffffU,
+/*02b9*/ 0xffffffffU,
+/*02ba*/ 0xffffffffU,
+/*02bb*/ 0xffffffffU,
+/*02bc*/ 0xffffffffU,
+/*02bd*/ 0x1002024fU,
+/*02be*/ 0x1802024fU,
+/*02bf*/ 0x00200250U,
+/*02c0*/ 0x00020251U,
+/*02c1*/ 0x08100251U,
+/*02c2*/ 0x00100252U,
+/*02c3*/ 0x10040252U,
+/*02c4*/ 0x18040252U,
+/*02c5*/ 0x00050253U,
+/*02c6*/ 0x08050253U,
+/*02c7*/ 0xffffffffU,
+/*02c8*/ 0xffffffffU,
+/*02c9*/ 0xffffffffU,
+/*02ca*/ 0xffffffffU,
+/*02cb*/ 0x10010253U,
+/*02cc*/ 0x18010253U,
+/*02cd*/ 0x00080254U,
+/*02ce*/ 0x08080254U,
+/*02cf*/ 0x10080254U,
+/*02d0*/ 0x18080254U,
+/*02d1*/ 0x00080255U,
+/*02d2*/ 0x08080255U,
+/*02d3*/ 0x10080255U,
+/*02d4*/ 0x18080255U,
+/*02d5*/ 0x00080256U,
+/*02d6*/ 0x08080256U,
+/*02d7*/ 0x10080256U,
+/*02d8*/ 0xffffffffU,
+/*02d9*/ 0xffffffffU,
+/*02da*/ 0xffffffffU,
+/*02db*/ 0xffffffffU,
+/*02dc*/ 0xffffffffU,
+/*02dd*/ 0xffffffffU,
+/*02de*/ 0x18030256U,
+/*02df*/ 0x00010257U,
+/*02e0*/ 0x08020257U,
+/*02e1*/ 0x10010257U,
+/*02e2*/ 0x18040257U,
+/*02e3*/ 0x00020258U,
+/*02e4*/ 0x08010258U,
+/*02e5*/ 0x10010258U,
+/*02e6*/ 0xffffffffU,
+/*02e7*/ 0x18010258U,
+/*02e8*/ 0x00040259U,
+/*02e9*/ 0x08080259U,
+/*02ea*/ 0x100a0259U,
+/*02eb*/ 0x000a025aU,
+/*02ec*/ 0x100a025aU,
+/*02ed*/ 0x000a025bU,
+/*02ee*/ 0x100a025bU,
+/*02ef*/ 0x000a025cU,
+/*02f0*/ 0x0020025dU,
+/*02f1*/ 0x0020025eU,
+/*02f2*/ 0x0001025fU,
+/*02f3*/ 0xffffffffU,
+/*02f4*/ 0xffffffffU,
+/*02f5*/ 0xffffffffU,
+/*02f6*/ 0x0802025fU,
+/*02f7*/ 0x1002025fU,
+/*02f8*/ 0x00100260U,
+/*02f9*/ 0x10050260U,
+/*02fa*/ 0x18060260U,
+/*02fb*/ 0x00050261U,
+/*02fc*/ 0x08050261U,
+/*02fd*/ 0x100e0261U,
+/*02fe*/ 0x00050262U,
+/*02ff*/ 0x080e0262U,
+/*0300*/ 0x18050262U,
+/*0301*/ 0x000e0263U,
+/*0302*/ 0x10050263U,
+/*0303*/ 0x18010263U,
+/*0304*/ 0x00050264U,
+/*0305*/ 0x08050264U,
+/*0306*/ 0x100a0264U,
+/*0307*/ 0x000a0265U,
+/*0308*/ 0x10050265U,
+/*0309*/ 0x18050265U,
+/*030a*/ 0x000a0266U,
+/*030b*/ 0x100a0266U,
+/*030c*/ 0x00050267U,
+/*030d*/ 0x08050267U,
+/*030e*/ 0x100a0267U,
+/*030f*/ 0x000a0268U,
+/*0310*/ 0xffffffffU,
+/*0311*/ 0xffffffffU,
+/*0312*/ 0xffffffffU,
+/*0313*/ 0xffffffffU,
+/*0314*/ 0xffffffffU,
+/*0315*/ 0xffffffffU,
+/*0316*/ 0x10070268U,
+/*0317*/ 0x18070268U,
+/*0318*/ 0x00040269U,
+/*0319*/ 0x08040269U,
+/*031a*/ 0xffffffffU,
+/*031b*/ 0xffffffffU,
+/*031c*/ 0xffffffffU,
+/*031d*/ 0x10040269U,
+/*031e*/ 0x18080269U,
+/*031f*/ 0x0008026aU,
+/*0320*/ 0x0804026aU,
+/*0321*/ 0xffffffffU,
+/*0322*/ 0xffffffffU,
+/*0323*/ 0xffffffffU,
+/*0324*/ 0x1004026aU,
+/*0325*/ 0xffffffffU,
+/*0326*/ 0xffffffffU,
+/*0327*/ 0xffffffffU,
+/*0328*/ 0x1804026aU,
+/*0329*/ 0xffffffffU,
+/*032a*/ 0xffffffffU,
+/*032b*/ 0xffffffffU,
+/*032c*/ 0x0004026bU,
+/*032d*/ 0x0805026bU,
+/*032e*/ 0x1007026bU,
+/*032f*/ 0x1808026bU,
+/*0330*/ 0x0010026cU,
+/*0331*/ 0x1008026cU,
+/*0332*/ 0x0010026dU,
+/*0333*/ 0x1008026dU,
+/*0334*/ 0x0010026eU,
+/*0335*/ 0x1008026eU,
+/*0336*/ 0x1808026eU,
+/*0337*/ 0x0001026fU,
+/*0338*/ 0x0801026fU,
+/*0339*/ 0x1006026fU,
+/*033a*/ 0x1806026fU,
+/*033b*/ 0x00060270U,
+/*033c*/ 0xffffffffU,
+/*033d*/ 0x08010270U,
+/*033e*/ 0x10030270U,
+/*033f*/ 0xffffffffU,
+/*0340*/ 0xffffffffU,
+/*0341*/ 0xffffffffU,
+/*0342*/ 0x000a0271U,
+/*0343*/ 0x100a0271U,
+/*0344*/ 0x00040272U,
+/*0345*/ 0x08010272U,
+/*0346*/ 0x10040272U,
+/*0347*/ 0xffffffffU,
+/*0348*/ 0xffffffffU,
+/*0349*/ 0xffffffffU,
+/*034a*/ 0xffffffffU,
+/*034b*/ 0xffffffffU,
+/*034c*/ 0xffffffffU,
+/*034d*/ 0x18070272U,
+/*034e*/ 0x00070273U,
+/*034f*/ 0x08050273U,
+/*0350*/ 0x10050273U,
+/*0351*/ 0xffffffffU,
+/*0352*/ 0xffffffffU,
+/*0353*/ 0xffffffffU,
+/*0354*/ 0x18040273U,
+/*0355*/ 0x00010274U,
+/*0356*/ 0x08010274U,
+/*0357*/ 0x10020274U,
+/*0358*/ 0x18080274U,
+/*0359*/ 0x00200275U,
+/*035a*/ 0x00200276U,
+/*035b*/ 0x00100277U,
+/*035c*/ 0xffffffffU,
+/*035d*/ 0xffffffffU,
+/*035e*/ 0xffffffffU,
+/*035f*/ 0x10020277U,
+/*0360*/ 0x18010277U,
+/*0361*/ 0xffffffffU,
+/*0362*/ 0x00020278U,
+/*0363*/ 0x08100278U,
+/*0364*/ 0x00100279U,
+/*0365*/ 0x10100279U,
+/*0366*/ 0x0008027aU,
+/*0367*/ 0x0808027aU,
+/*0368*/ 0x1008027aU,
+/*0369*/ 0xffffffffU,
+/*036a*/ 0x0010027bU,
+/*036b*/ 0x1010027bU,
+/*036c*/ 0x0010027cU,
+/*036d*/ 0x1008027cU,
+/*036e*/ 0x1808027cU,
+/*036f*/ 0x0008027dU,
+/*0370*/ 0xffffffffU,
+/*0371*/ 0x0810027dU,
+/*0372*/ 0x0010027eU,
+/*0373*/ 0x1010027eU,
+/*0374*/ 0x0008027fU,
+/*0375*/ 0x0808027fU,
+/*0376*/ 0x1008027fU,
+/*0377*/ 0xffffffffU,
+/*0378*/ 0x1808027fU,
+/*0379*/ 0x00100280U,
+/*037a*/ 0x10100280U,
+/*037b*/ 0x00100281U,
+/*037c*/ 0x10080281U,
+/*037d*/ 0x18080281U,
+/*037e*/ 0x00080282U,
+/*037f*/ 0xffffffffU,
+/*0380*/ 0x08100282U,
+/*0381*/ 0x00100283U,
+/*0382*/ 0x10100283U,
+/*0383*/ 0x00080284U,
+/*0384*/ 0x08080284U,
+/*0385*/ 0x10080284U,
+/*0386*/ 0xffffffffU,
+/*0387*/ 0x00100285U,
+/*0388*/ 0x10100285U,
+/*0389*/ 0x00100286U,
+/*038a*/ 0x10080286U,
+/*038b*/ 0x18080286U,
+/*038c*/ 0x00080287U,
+/*038d*/ 0xffffffffU,
+/*038e*/ 0x08080287U,
+/*038f*/ 0x10100287U,
+/*0390*/ 0x00100288U,
+/*0391*/ 0x10100288U,
+/*0392*/ 0x00080289U,
+/*0393*/ 0x08080289U,
+/*0394*/ 0x10080289U,
+/*0395*/ 0xffffffffU,
+/*0396*/ 0x0010028aU,
+/*0397*/ 0x1010028aU,
+/*0398*/ 0x0010028bU,
+/*0399*/ 0x1008028bU,
+/*039a*/ 0x1808028bU,
+/*039b*/ 0x0008028cU,
+/*039c*/ 0xffffffffU,
+/*039d*/ 0x0810028cU,
+/*039e*/ 0x0010028dU,
+/*039f*/ 0x1010028dU,
+/*03a0*/ 0x0008028eU,
+/*03a1*/ 0x0808028eU,
+/*03a2*/ 0x1008028eU,
+/*03a3*/ 0xffffffffU,
+/*03a4*/ 0x1808028eU,
+/*03a5*/ 0x0010028fU,
+/*03a6*/ 0x1010028fU,
+/*03a7*/ 0x00100290U,
+/*03a8*/ 0x10080290U,
+/*03a9*/ 0x18080290U,
+/*03aa*/ 0x00080291U,
+/*03ab*/ 0xffffffffU,
+/*03ac*/ 0x08100291U,
+/*03ad*/ 0x00100292U,
+/*03ae*/ 0x10100292U,
+/*03af*/ 0x00080293U,
+/*03b0*/ 0x08080293U,
+/*03b1*/ 0x10080293U,
+/*03b2*/ 0xffffffffU,
+/*03b3*/ 0x00100294U,
+/*03b4*/ 0x10100294U,
+/*03b5*/ 0x00100295U,
+/*03b6*/ 0x10080295U,
+/*03b7*/ 0x18080295U,
+/*03b8*/ 0x00080296U,
+/*03b9*/ 0xffffffffU,
+/*03ba*/ 0x08080296U,
+/*03bb*/ 0x10020296U,
+/*03bc*/ 0x18030296U,
+/*03bd*/ 0x000a0297U,
+/*03be*/ 0x100a0297U,
+/*03bf*/ 0x000a0298U,
+/*03c0*/ 0x10050298U,
+/*03c1*/ 0x18040298U,
+/*03c2*/ 0x00080299U,
+/*03c3*/ 0x08080299U,
+/*03c4*/ 0x10060299U,
+/*03c5*/ 0x18060299U,
+/*03c6*/ 0x0011029aU,
+/*03c7*/ 0x1808029aU,
+/*03c8*/ 0x0004029bU,
+/*03c9*/ 0x0806029bU,
+/*03ca*/ 0xffffffffU,
+/*03cb*/ 0x1006029bU,
+/*03cc*/ 0x1808029bU,
+/*03cd*/ 0x0008029cU,
+/*03ce*/ 0x0804029cU,
+/*03cf*/ 0x1008029cU,
+/*03d0*/ 0x1808029cU,
+/*03d1*/ 0x0006029dU,
+/*03d2*/ 0x0806029dU,
+/*03d3*/ 0x0011029eU,
+/*03d4*/ 0x1808029eU,
+/*03d5*/ 0x0004029fU,
+/*03d6*/ 0x0806029fU,
+/*03d7*/ 0xffffffffU,
+/*03d8*/ 0x1006029fU,
+/*03d9*/ 0x1808029fU,
+/*03da*/ 0x000802a0U,
+/*03db*/ 0x080402a0U,
+/*03dc*/ 0x100802a0U,
+/*03dd*/ 0x180802a0U,
+/*03de*/ 0x000602a1U,
+/*03df*/ 0x080602a1U,
+/*03e0*/ 0x001102a2U,
+/*03e1*/ 0x180802a2U,
+/*03e2*/ 0x000402a3U,
+/*03e3*/ 0x080602a3U,
+/*03e4*/ 0xffffffffU,
+/*03e5*/ 0x100602a3U,
+/*03e6*/ 0x180802a3U,
+/*03e7*/ 0x000802a4U,
+/*03e8*/ 0x080402a4U,
+/*03e9*/ 0x100402a4U,
+/*03ea*/ 0x180402a4U,
+/*03eb*/ 0x000402a5U,
+/*03ec*/ 0x080402a5U,
+/*03ed*/ 0x100402a5U,
+/*03ee*/ 0x180402a5U,
+/*03ef*/ 0x000402a6U,
+/*03f0*/ 0x080402a6U,
+/*03f1*/ 0x100402a6U,
+/*03f2*/ 0x180402a6U,</