diff options
author | Dehui Sun <dehui.sun@mediatek.com> | 2020-07-03 09:19:06 +0800 |
---|---|---|
committer | Nina Wu <nina-cm.wu@mediatek.com> | 2020-10-28 17:21:55 +0800 |
commit | 4a128018b63ca9a4517eeefbe0c1c50b691ce433 (patch) | |
tree | ddd5363f26e5b2ee5fbacd43d47086600d1a9c39 /plat | |
parent | 0f408247292b6e49a4228dc7bd3941caf1db5dbc (diff) | |
download | trusted-firmware-a-4a128018b63ca9a4517eeefbe0c1c50b691ce433.tar.gz |
mediatek: mt8192: add timer support
add timer driver.
Signed-off-by: Dehui Sun <dehui.sun@mediatek.com>
Change-Id: I07448d85a15bb14577b05e4f302860d609420ba7
Diffstat (limited to 'plat')
-rw-r--r-- | plat/mediatek/mt8192/drivers/timer/mt_timer.c | 30 | ||||
-rw-r--r-- | plat/mediatek/mt8192/drivers/timer/mt_timer.h | 30 | ||||
-rw-r--r-- | plat/mediatek/mt8192/platform.mk | 6 |
3 files changed, 64 insertions, 2 deletions
diff --git a/plat/mediatek/mt8192/drivers/timer/mt_timer.c b/plat/mediatek/mt8192/drivers/timer/mt_timer.c new file mode 100644 index 0000000000..781f940b69 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/timer/mt_timer.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch_helpers.h> +#include <mt_timer.h> +#include <platform_def.h> + + +uint64_t normal_time_base; +uint64_t atf_time_base; + +void sched_clock_init(uint64_t normal_base, uint64_t atf_base) +{ + normal_time_base += normal_base; + atf_time_base = atf_base; +} + +uint64_t sched_clock(void) +{ + uint64_t cval; + uint64_t rel_base; + + rel_base = read_cntpct_el0() - atf_time_base; + cval = ((rel_base * 1000U) / SYS_COUNTER_FREQ_IN_MHZ) + - normal_time_base; + return cval; +} diff --git a/plat/mediatek/mt8192/drivers/timer/mt_timer.h b/plat/mediatek/mt8192/drivers/timer/mt_timer.h new file mode 100644 index 0000000000..7aca4a3bf9 --- /dev/null +++ b/plat/mediatek/mt8192/drivers/timer/mt_timer.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_TIMER_H +#define MT_TIMER_H + +#define SYSTIMER_BASE (0x10017000) +#define CNTCR_REG (SYSTIMER_BASE + 0x0) +#define CNTSR_REG (SYSTIMER_BASE + 0x4) +#define CNTSYS_L_REG (SYSTIMER_BASE + 0x8) +#define CNTSYS_H_REG (SYSTIMER_BASE + 0xc) + +#define TIEO_EN (1 << 3) +#define COMP_15_EN (1 << 10) +#define COMP_20_EN (1 << 11) +#define COMP_25_EN (1 << 12) + +#define COMP_FEATURE_MASK (COMP_15_EN | COMP_20_EN | COMP_25_EN | TIEO_EN) +#define COMP_15_MASK (COMP_15_EN) +#define COMP_20_MASK (COMP_20_EN | TIEO_EN) +#define COMP_25_MASK (COMP_20_EN | COMP_25_EN) + + +void sched_clock_init(uint64_t normal_base, uint64_t atf_base); +uint64_t sched_clock(void); + +#endif /* MT_TIMER_H */ diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk index 071700ee98..7544b26583 100644 --- a/plat/mediatek/mt8192/platform.mk +++ b/plat/mediatek/mt8192/platform.mk @@ -10,7 +10,8 @@ MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ -I${MTK_PLAT_SOC}/include/ \ -I${MTK_PLAT_SOC}/drivers/ \ - -I${MTK_PLAT_SOC}/drivers/gpio/ + -I${MTK_PLAT_SOC}/drivers/gpio/ \ + -I${MTK_PLAT_SOC}/drivers/timer/ GICV3_SUPPORT_GIC600 := 1 include drivers/arm/gic/v3/gicv3.mk @@ -37,7 +38,8 @@ BL31_SOURCES += common/desc_image_load.c \ ${MTK_PLAT_SOC}/plat_topology.c \ ${MTK_PLAT_SOC}/plat_mt_gic.c \ ${MTK_PLAT_SOC}/plat_mt_cirq.c \ - ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c + ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \ + ${MTK_PLAT_SOC}/drivers/timer/mt_timer.c # Configs for A76 and A55 |