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authorVarun Wadekar <vwadekar@nvidia.com>2016-04-09 00:40:45 -0700
committerVarun Wadekar <vwadekar@nvidia.com>2017-03-23 15:23:22 -0700
commitb46ac6dcc5d20d53a62b02430cafc6aeba154d3b (patch)
treec1337f3361278135c2e35b3af58f0893963aed3f /plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
parentabd3a91d6fed30be47bd47f9ecb914a5917f6784 (diff)
downloadtrusted-firmware-a-b46ac6dcc5d20d53a62b02430cafc6aeba154d3b.tar.gz
Tegra186: reset power state info during CPU_ON
This patch resets the power state info for CPUs when onlining, as we set deepest power when offlining a core but that may not be requested by non-secure sw which controls idle states. It will re-init this info from non-secure software when the core come online. Original change by Prashant Gaikwad <pgaikwad@nvidia.com> Change-Id: Id6c2fa2b821c7705aafbb561a62348c36fd3abd8 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'plat/nvidia/tegra/soc/t186/plat_psci_handlers.c')
-rw-r--r--plat/nvidia/tegra/soc/t186/plat_psci_handlers.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
index 8911e8f617..b518918314 100644
--- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
@@ -247,6 +247,18 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
gp_regs_t *gp_regs = get_gpregs_ctx(ctx);
/*
+ * Reset power state info for CPUs when onlining, we set deepest power
+ * when offlining a core but that may not be requested by non-secure
+ * sw which controls idle states. It will re-init this info from
+ * non-secure software when the core come online.
+ */
+ write_ctx_reg(gp_regs, CTX_GPREG_X4, 0);
+ write_ctx_reg(gp_regs, CTX_GPREG_X5, 0);
+ write_ctx_reg(gp_regs, CTX_GPREG_X6, 1);
+ mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, TEGRA_ARI_CLUSTER_CC1,
+ 0, 0);
+
+ /*
* Check if we are exiting from deep sleep and restore SE
* context if we are.
*/