diff options
author | Varun Wadekar <vwadekar@nvidia.com> | 2017-11-08 14:45:08 -0800 |
---|---|---|
committer | Varun Wadekar <vwadekar@nvidia.com> | 2019-01-23 10:32:53 -0800 |
commit | 889c07c7b1a9739bcc907ad1f988fa484d22f84c (patch) | |
tree | 4a8cda1f248cfefb1c2bff43f39ff06ee216d7b1 /plat/nvidia/tegra/soc/t186/plat_psci_handlers.c | |
parent | d7be5e2e3af87c059bd692459ce8c4a493f404bb (diff) | |
download | trusted-firmware-a-889c07c7b1a9739bcc907ad1f988fa484d22f84c.tar.gz |
Tegra186: helper functions for CPU rst handler and SMMU ctx offset
This patch adds a helper function to get the SMMU context's offset
and uses another helper function to get the CPU trampoline offset.
These helper functions are used by the System Suspend entry sequence
to save the SMMU context and CPU reset handler to TZDRAM.
Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'plat/nvidia/tegra/soc/t186/plat_psci_handlers.c')
-rw-r--r-- | plat/nvidia/tegra/soc/t186/plat_psci_handlers.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c index 5d3cdfaf5c..162a2833ad 100644 --- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c @@ -22,12 +22,10 @@ #include <smmu.h> #include <stdbool.h> #include <t18x_ari.h> +#include <tegra186_private.h> #include <tegra_private.h> extern void memcpy16(void *dest, const void *src, unsigned int length); -extern void tegra186_cpu_reset_handler(void); -extern uint64_t __tegra186_cpu_reset_handler_end, - __tegra186_smmu_context; /* state id mask */ #define TEGRA186_STATE_ID_MASK 0xFU @@ -127,8 +125,7 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) /* save SMMU context to TZDRAM */ smmu_ctx_base = params_from_bl2->tzdram_base + - ((uintptr_t)&__tegra186_smmu_context - - (uintptr_t)&tegra186_cpu_reset_handler); + tegra186_get_smmu_ctx_offset(); tegra_smmu_save_context((uintptr_t)smmu_ctx_base); /* Prepare for system suspend */ @@ -279,8 +276,7 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta * BL3-1 over to TZDRAM. */ val = params_from_bl2->tzdram_base + - ((uintptr_t)&__tegra186_cpu_reset_handler_end - - (uintptr_t)&tegra186_cpu_reset_handler); + tegra186_get_cpu_reset_handler_size(); memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); } |