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authorSteven Kao <skao@nvidia.com>2018-02-09 20:50:02 +0800
committerVarun Wadekar <vwadekar@nvidia.com>2019-01-31 08:47:51 -0800
commit1d11f73e581bfbe9945a298ab1c4fd5ff261f6e7 (patch)
tree9adf056082ad58964b61045367deab4151051998 /plat/nvidia/tegra/include/platform_def.h
parent26cf08494b3db526c4b887d27c797da49efb7505 (diff)
downloadtrusted-firmware-a-1d11f73e581bfbe9945a298ab1c4fd5ff261f6e7.tar.gz
Tegra: platform dependent address space sizes
This patch moves the PLAT_PHY_ADDR_SPACE_SIZE & PLAT_VIRT_ADDR_SPACE macros to tegra_def.h, to define the virtual/physical address space size on the platform. Change-Id: I1c5d264c7ffc1af0e7b14cc16ae2c0416efc76f6 Signed-off-by: Steven Kao <skao@nvidia.com>
Diffstat (limited to 'plat/nvidia/tegra/include/platform_def.h')
-rw-r--r--plat/nvidia/tegra/include/platform_def.h8
1 files changed, 1 insertions, 7 deletions
diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h
index 0a0126b1e0..334ad129a1 100644
--- a/plat/nvidia/tegra/include/platform_def.h
+++ b/plat/nvidia/tegra/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -54,12 +54,6 @@
#define BL32_LIMIT TZDRAM_END
/*******************************************************************************
- * Platform specific page table and MMU setup constants
- ******************************************************************************/
-#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
-
-/*******************************************************************************
* Some data must be aligned on the biggest cache line size in the platform.
* This is known only to the platform as it might have a combination of
* integrated and external caches.