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authorBryan O'Donoghue <bryan.odonoghue@linaro.org>2018-05-25 16:45:27 +0100
committerBryan O'Donoghue <bryan.odonoghue@linaro.org>2018-09-04 14:18:31 +0100
commitb42ceebb40ae57ea18e77e2270fb131fa981c906 (patch)
treedbf3a45ffcbabaff2b7f9dc8685e4779b2c884b5 /plat/imx/common/include/imx_wdog.h
parentca52cbe65b1453f4a2811249847d3387b6888fd3 (diff)
downloadtrusted-firmware-a-b42ceebb40ae57ea18e77e2270fb131fa981c906.tar.gz
imx: imx_wdog: Add code to initialize the wdog block
The watchdog block on the IMX is mercifully simple. This patch maps the various registers and bits associated with the block. We are mostly only really interested in the power-down-enable (PDE) bits in the block for the purposes of ATF. The i.MX7 Solo Applications Processor Reference Manual details the PDE bit as follows: "Power Down Enable bit. Reset value of this bit is 1, which means the power down counter inside the WDOG is enabled after reset. The software must write 0 to this bit to disable the counter within 16 seconds of reset de-assertion. Once disabled this counter cannot be enabled again. See Power-down counter event for operation of this counter." This patch does that zero write in-lieu of later phases in the boot no-longer have the necessary permissions to rewrite the PDE bit directly. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Diffstat (limited to 'plat/imx/common/include/imx_wdog.h')
-rw-r--r--plat/imx/common/include/imx_wdog.h61
1 files changed, 61 insertions, 0 deletions
diff --git a/plat/imx/common/include/imx_wdog.h b/plat/imx/common/include/imx_wdog.h
new file mode 100644
index 000000000..8033e6268
--- /dev/null
+++ b/plat/imx/common/include/imx_wdog.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __IMX_WDOG_H__
+#define __IMX_WDOG_H__
+
+#include <arch.h>
+#include <stdint.h>
+
+struct wdog_regs {
+ uint16_t wcr;
+ uint16_t wsr;
+ uint16_t wrsr;
+ uint16_t wicr;
+ uint16_t wmcr;
+};
+
+/* WCR bits */
+#define WCR_WDZST BIT(0)
+#define WCR_WDBG BIT(1)
+#define WCR_WDE BIT(2)
+#define WCR_WDT BIT(3)
+#define WCR_SRS BIT(4)
+#define WCR_WDA BIT(5)
+#define WCR_SRE BIT(6)
+#define WCR_WDW BIT(7)
+#define WCR_WT(x) ((x) << 8)
+
+/* WSR bits */
+#define WSR_FIRST 0x5555
+#define WSR_SECOND 0xAAAA
+
+/* WRSR bits */
+#define WRSR_SFTW BIT(0)
+#define WRSR_TOUT BIT(1)
+#define WRSR_POR BIT(4)
+
+/* WICR bits */
+static inline int wicr_calc_wict(int sec, int half_sec)
+{
+ int wict_bits;
+
+ /* Represents WICR bits 7 - 0 */
+ wict_bits = ((sec << 1) | (half_sec ? 1 : 0));
+
+ return wict_bits;
+}
+
+#define WICR_WTIS BIT(14)
+#define WICR_WIE BIT(15)
+
+/* WMCR bits */
+#define WMCR_PDE BIT(0)
+
+/* External facing API */
+void imx_wdog_init(void);
+
+#endif /* __IMX_WDOG_H__ */