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authorBryan O'Donoghue <bryan.odonoghue@linaro.org>2018-05-25 16:43:22 +0100
committerBryan O'Donoghue <bryan.odonoghue@linaro.org>2018-09-04 13:36:23 +0100
commit49a6413447d2893b56b3c8189785680f7b0d95ab (patch)
tree5ecaf88b83e739c750cc5a6931a1052abe8357e6 /plat/imx/common/imx_aips.c
parent965bda4d4e846439df1baf91068d572f1b099c16 (diff)
downloadtrusted-firmware-a-49a6413447d2893b56b3c8189785680f7b0d95ab.tar.gz
imx: imx_aips: Add initial AIPS support
This patch adds an initial AHB-to-IP TrustZone (AIPS-TZ) initialization routine. Setting up the AIPSTZ controller is required to inform the SoC interconnect fabric which bus-masters can read/write and if the read/writes are buffered. For our purposes the initial configuration is for everything to be open. We can lock-down later on as necessary. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Diffstat (limited to 'plat/imx/common/imx_aips.c')
-rw-r--r--plat/imx/common/imx_aips.c56
1 files changed, 56 insertions, 0 deletions
diff --git a/plat/imx/common/imx_aips.c b/plat/imx/common/imx_aips.c
new file mode 100644
index 000000000..991c262bc
--- /dev/null
+++ b/plat/imx/common/imx_aips.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include <utils_def.h>
+#include <imx_aips.h>
+#include <imx_regs.h>
+
+static void imx_aips_set_default_access(struct aipstz_regs *aips_regs)
+{
+ int i;
+ uintptr_t addr;
+
+ /*
+ * See section 4.7.7.1 AIPSTZ_MPR field descriptions
+ * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
+ * 0111 ->
+ * 0: Write Access from master not buffered
+ * 1: Master is trusted for read access
+ * 1: Master is trsuted for write access
+ * 1: Access from master is not forced to user mode
+ */
+ addr = (uintptr_t)&aips_regs->aipstz_mpr;
+ mmio_write_32(addr, 0x77777777);
+
+ /*
+ * Helpfully the OPACR registers have the logical inversion of the above
+ * See section 4.7.7.1 AIPSTZ_MPR field descriptions
+ * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
+ * 0000 ->
+ * 0: Write Access to the peripheral is not buffered by AIPSTZ
+ * 0: The peripheral does not require supervisor priv to access
+ * 0: Master is trsuted for write access
+ * 0: Access from master is not forced to user mode
+ */
+ for (i = 0; i < AIPSTZ_OAPCR_COUNT; i++) {
+ addr = (uintptr_t)&aips_regs->aipstz_opacr[i];
+ mmio_write_32(addr, 0x00000000);
+ }
+}
+
+void imx_aips_init(void)
+{
+ int i;
+ struct aipstz_regs *aips_regs[] = {
+ (struct aipstz_regs *)(AIPS1_BASE + AIPSTZ_CONFIG_OFFSET),
+ (struct aipstz_regs *)(AIPS2_BASE + AIPSTZ_CONFIG_OFFSET),
+ (struct aipstz_regs *)(AIPS3_BASE + AIPSTZ_CONFIG_OFFSET),
+ };
+
+ for (i = 0; i < ARRAY_SIZE(aips_regs); i++)
+ imx_aips_set_default_access(aips_regs[i]);
+}