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authorJiancheng Xue <xuejiancheng@hisilicon.com>2017-08-28 18:55:43 +0800
committerVictor Chong <victor.chong@linaro.org>2017-12-12 13:01:09 +0900
commitd45a1c303e71221086eb2464c5f3d506eeccb50a (patch)
treee89442ae81eb505105cae89dee555ce356719861 /plat/hisilicon/poplar
parent94725a26d82384f2f4c544d750117fa6d7a3312c (diff)
downloadtrusted-firmware-a-d45a1c303e71221086eb2464c5f3d506eeccb50a.tar.gz
Poplar: Initialize security properties of IP blocks.
The security properties of some IP blocks are configured to secure mode after reset. This means these IP blocks can only be accessed by cpus in secure state by default. These should be configured correclty as needed. Signed-off-by: y00241285 <yyangwei.yangwei@hisilicon.com> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Diffstat (limited to 'plat/hisilicon/poplar')
-rw-r--r--plat/hisilicon/poplar/bl31_plat_setup.c10
-rw-r--r--plat/hisilicon/poplar/include/hi3798cv200.h3
2 files changed, 13 insertions, 0 deletions
diff --git a/plat/hisilicon/poplar/bl31_plat_setup.c b/plat/hisilicon/poplar/bl31_plat_setup.c
index b9a0e18e7..9e970e773 100644
--- a/plat/hisilicon/poplar/bl31_plat_setup.c
+++ b/plat/hisilicon/poplar/bl31_plat_setup.c
@@ -32,8 +32,15 @@
#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
+#define TZPC_SEC_ATTR_CTRL_VALUE (0x9DB98D45)
+
static entry_point_info_t bl33_image_ep_info;
+static void hisi_tzpc_sec_init(void)
+{
+ mmio_write_32(HISI_TZPC_SEC_ATTR_CTRL, TZPC_SEC_ATTR_CTRL_VALUE);
+}
+
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
{
return &bl33_image_ep_info;
@@ -58,6 +65,9 @@ void bl31_platform_setup(void)
/* Init GIC distributor and CPU interface */
plat_arm_gic_driver_init();
plat_arm_gic_init();
+
+ /* Init security properties of IP blocks */
+ hisi_tzpc_sec_init();
}
void bl31_plat_runtime_setup(void)
diff --git a/plat/hisilicon/poplar/include/hi3798cv200.h b/plat/hisilicon/poplar/include/hi3798cv200.h
index 06dadc2b5..540d0aa18 100644
--- a/plat/hisilicon/poplar/include/hi3798cv200.h
+++ b/plat/hisilicon/poplar/include/hi3798cv200.h
@@ -97,4 +97,7 @@
/* Watchdog */
#define HISI_WDG0_BASE (0xF8A2C000)
+#define HISI_TZPC_BASE (0xF8A80000)
+#define HISI_TZPC_SEC_ATTR_CTRL (HISI_TZPC_BASE + 0x10)
+
#endif /* __HI3798cv200_H__ */