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authorSamuel Holland <samuel@sholland.org>2019-10-20 14:17:30 -0500
committerSamuel Holland <samuel@sholland.org>2019-12-13 19:20:36 -0600
commiteb75518d988e8a59f21ab1ac77e5ae928526e06e (patch)
tree5becddf119a6f5878e2c3a49c7b4e6e7a6f9753a /plat/allwinner/common/sunxi_common.c
parent1a433965afd5734cec1dbc9d5e3b878ccd3eb98c (diff)
downloadtrusted-firmware-a-eb75518d988e8a59f21ab1ac77e5ae928526e06e.tar.gz
allwinner: Enable clock before resetting I2C/RSB
The clock must be running for the module to be reset. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Ic8fafc946f3a1a697174b91288e357ffa033ab9a
Diffstat (limited to 'plat/allwinner/common/sunxi_common.c')
-rw-r--r--plat/allwinner/common/sunxi_common.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c
index 0797452a6e..1e21a42626 100644
--- a/plat/allwinner/common/sunxi_common.c
+++ b/plat/allwinner/common/sunxi_common.c
@@ -150,16 +150,16 @@ int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb)
/* set both pins to pull-up */
mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x1c, 0x0fU, 0x5U);
- /* assert, then de-assert reset of I2C/RSB controller */
- mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit);
- mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit);
-
/* un-gate clock */
if (socid != SUNXI_SOC_H6)
mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit);
else
mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x19c, device_bit | BIT(0));
+ /* assert, then de-assert reset of I2C/RSB controller */
+ mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit);
+ mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit);
+
return 0;
}