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author | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-02-21 17:35:07 +0000 |
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committer | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-02-26 16:21:06 +0000 |
commit | 508d71108a06c7fce2eeef78659b9b7739cee6eb (patch) | |
tree | 0a79684da2ea12a62188da7d4415598f2a0d4398 /lib/cpus/aarch64/cortex_a76.S | |
parent | 98551591f5371de2c2f0dee6be2e12b75653f04d (diff) | |
download | trusted-firmware-a-508d71108a06c7fce2eeef78659b9b7739cee6eb.tar.gz |
Add workaround for errata 1130799 for Cortex-A76
TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page
aggregated address translation data in the L2 TLB might cause
corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to
prevent this.
Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Diffstat (limited to 'lib/cpus/aarch64/cortex_a76.S')
-rw-r--r-- | lib/cpus/aarch64/cortex_a76.S | 41 |
1 files changed, 40 insertions, 1 deletions
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index 27db74e418..8438fa6cf9 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -189,6 +189,34 @@ vector_entry cortex_a76_serror_aarch32 b serror_aarch32 end_vector_entry cortex_a76_serror_aarch32 + /* -------------------------------------------------- + * Errata Workaround for Cortex A76 Errata #1130799. + * This applies only to revision <= r2p0 of Cortex A76. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a76_1130799_wa + /* + * Compare x0 against revision r2p0 + */ + mov x17, x30 + bl check_errata_1130799 + cbz x0, 1f + mrs x1, CORTEX_A76_CPUACTLR2_EL1 + orr x1, x1 ,#(1 << 59) + msr CORTEX_A76_CPUACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_a76_1130799_wa + +func check_errata_1130799 + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_1130799 + func check_errata_cve_2018_3639 #if WORKAROUND_CVE_2018_3639 mov x0, #ERRATA_APPLIES @@ -206,8 +234,18 @@ func cortex_a76_disable_wa_cve_2018_3639 ret endfunc cortex_a76_disable_wa_cve_2018_3639 + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A76. + * Shall clobber: x0-x19 + * ------------------------------------------------- + */ func cortex_a76_reset_func mov x19, x30 + bl cpu_get_rev_var + +#if ERRATA_A76_1130799 + bl errata_a76_1130799_wa +#endif #if WORKAROUND_CVE_2018_3639 /* If the PE implements SSBS, we don't need the dynamic workaround */ @@ -271,6 +309,7 @@ func cortex_a76_errata_report * Report all errata. The revision-variant information is passed to * checking functions of each errata. */ + report_errata ERRATA_A76_1130799, cortex_a76, 1130799 report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639 report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184 |