diff options
author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2016-01-13 14:57:38 +0000 |
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committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2016-02-08 09:31:18 +0000 |
commit | 54035fc4672aab046f3cf5288ce9870613bd713d (patch) | |
tree | 211e2343035056381eed8764300c9f76170d63dc /include/lib/cpus/aarch64/cortex_a57.h | |
parent | dbc807179fea7438efa3374584310727ce44bbc9 (diff) | |
download | trusted-firmware-a-54035fc4672aab046f3cf5288ce9870613bd713d.tar.gz |
Disable non-temporal hint on Cortex-A53/57
The LDNP/STNP instructions as implemented on Cortex-A53 and
Cortex-A57 do not behave in a way most programmers expect, and will
most probably result in a significant speed degradation to any code
that employs them. The ARMv8-A architecture (see Document ARM DDI
0487A.h, section D3.4.3) allows cores to ignore the non-temporal hint
and treat LDNP/STNP as LDP/STP instead.
This patch introduces 2 new build flags:
A53_DISABLE_NON_TEMPORAL_HINT and A57_DISABLE_NON_TEMPORAL_HINT
to enforce this behaviour on Cortex-A53 and Cortex-A57. They are
enabled by default.
The string printed in debug builds when a specific CPU errata
workaround is compiled in but skipped at runtime has been
generalised, so that it can be reused for the non-temporal hint use
case as well.
Change-Id: I3e354f4797fd5d3959872a678e160322b13867a1
Diffstat (limited to 'include/lib/cpus/aarch64/cortex_a57.h')
-rw-r--r-- | include/lib/cpus/aarch64/cortex_a57.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index c81259c894..c512129a17 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -61,8 +61,9 @@ ******************************************************************************/ #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ -#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) -#define CPUACTLR_DCC_AS_DCCI (1 << 44) +#define CPUACTLR_DIS_OVERREAD (1 << 52) +#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) +#define CPUACTLR_DCC_AS_DCCI (1 << 44) /******************************************************************************* * L2 Control register specific definitions. |