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authorMarcin Wojtas <mw@semihalf.com>2018-03-21 09:55:47 +0100
committerKonstantin Porotchkin <kostap@marvell.com>2018-09-03 15:46:14 +0300
commit4acd900df6275cd724266157e04e2b75d82cf24a (patch)
treeaacd6b760a02e7deab2a8c9972b9d09b1238dfe9 /include/drivers
parent155d01ff1eea98fbec128688eedbefc8a6b798af (diff)
downloadtrusted-firmware-a-4acd900df6275cd724266157e04e2b75d82cf24a.tar.gz
gicv2: enable configuring IRQ trigger type
This patch introduces new helper routines that allow configuring the individual IRQs to be edge/level-triggered via GICD_ICFGR registers. This is helpful to modify the default configuration of the non-secure GIC SPI's, which are all set during initialization to be level-sensitive. Change-Id: I23deb4a0381691a686a3cda52405aa1dfd5e56f2 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Diffstat (limited to 'include/drivers')
-rw-r--r--include/drivers/arm/gicv2.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h
index 925d1c25c1..3472c37d7b 100644
--- a/include/drivers/arm/gicv2.h
+++ b/include/drivers/arm/gicv2.h
@@ -191,6 +191,7 @@ void gicv2_set_spi_routing(unsigned int id, int proc_num);
void gicv2_set_interrupt_pending(unsigned int id);
void gicv2_clear_interrupt_pending(unsigned int id);
unsigned int gicv2_set_pmr(unsigned int mask);
+void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg);
#endif /* __ASSEMBLY__ */
#endif /* __GICV2_H__ */