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authorQixiang Xu <qixiang.xu@arm.com>2018-03-05 09:31:11 +0800
committerQixiang Xu <qixiang.xu@arm.com>2018-05-22 16:19:17 +0800
commit79c17995aa7ab385bb97eeff783dd8acd6ca0935 (patch)
tree17f952efacb3bdb546ca89d2c0d02e1b504f3a4d /include/common
parent1f4d62df6cba1cb25e40ea050f5327c1c4d4a7b9 (diff)
downloadtrusted-firmware-a-79c17995aa7ab385bb97eeff783dd8acd6ca0935.tar.gz
Correct some typo errors in comment
File: include/common/aarch64/el3_common_macros.S Change-Id: I619401e961a3f627ad8864781b5f90bc747c3ddb Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
Diffstat (limited to 'include/common')
-rw-r--r--include/common/aarch64/el3_common_macros.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/common/aarch64/el3_common_macros.S b/include/common/aarch64/el3_common_macros.S
index d5f527aa3b..03b977e369 100644
--- a/include/common/aarch64/el3_common_macros.S
+++ b/include/common/aarch64/el3_common_macros.S
@@ -20,7 +20,7 @@
*
* SCTLR_EL3.I: Enable the instruction cache.
*
- * SCTLR_EL3.SA: Enable Stack Aligment check. A SP alignment fault
+ * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault
* exception is generated if a load or store instruction executed at
* EL3 uses the SP as the base address and the SP is not aligned to a
* 16-byte boundary.
@@ -186,7 +186,7 @@
* XN (Execute-never). Set to zero so that this control has no
* effect on memory access permissions.
*
- * SCTLR_EL3.SA: Set to zero to disable Stack Aligment check.
+ * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check.
*
* SCTLR_EL3.A: Set to zero to disable Alignment fault checking.
* -------------------------------------------------------------