diff options
author | Yann Gautier <yann.gautier@st.com> | 2019-02-14 11:01:20 +0100 |
---|---|---|
committer | Yann Gautier <yann.gautier@st.com> | 2019-02-14 11:20:23 +0100 |
commit | 7ae58c6ba79fee3cc032aae2105b073304409ebc (patch) | |
tree | 285ded01264f6dc644bd7adda5736e9b9da448af /drivers | |
parent | 447b2b137d7286a1ef451336c6e73fb7fd8999a1 (diff) | |
download | trusted-firmware-a-7ae58c6ba79fee3cc032aae2105b073304409ebc.tar.gz |
stm32mp1: use functions to retrieve some peripheral addresses
PWR, RCC, DDRPHYC & DDRCTRL addresses can be retrieved from device tree.
Platform asserts the value read from the DT are the SoC addresses.
Change-Id: I43f0890b51918a30c87ac067d3780ab27a0f59de
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/st/ddr/stm32mp1_ddr_helpers.c | 2 | ||||
-rw-r--r-- | drivers/st/ddr/stm32mp1_ram.c | 8 | ||||
-rw-r--r-- | drivers/st/reset/stm32mp1_reset.c | 10 |
3 files changed, 11 insertions, 9 deletions
diff --git a/drivers/st/ddr/stm32mp1_ddr_helpers.c b/drivers/st/ddr/stm32mp1_ddr_helpers.c index e50b27be8a..c66c9e707a 100644 --- a/drivers/st/ddr/stm32mp1_ddr_helpers.c +++ b/drivers/st/ddr/stm32mp1_ddr_helpers.c @@ -11,7 +11,7 @@ void ddr_enable_clock(void) { - mmio_setbits_32(RCC_BASE + RCC_DDRITFCR, + mmio_setbits_32(stm32mp_rcc_base() + RCC_DDRITFCR, RCC_DDRITFCR_DDRC1EN | RCC_DDRITFCR_DDRC2EN | RCC_DDRITFCR_DDRPHYCEN | diff --git a/drivers/st/ddr/stm32mp1_ram.c b/drivers/st/ddr/stm32mp1_ram.c index 7b13385fc9..59b4351f01 100644 --- a/drivers/st/ddr/stm32mp1_ram.c +++ b/drivers/st/ddr/stm32mp1_ram.c @@ -298,10 +298,10 @@ int stm32mp1_ddr_probe(void) VERBOSE("STM32MP DDR probe\n"); - priv->ctl = (struct stm32mp1_ddrctl *)DDRCTRL_BASE; - priv->phy = (struct stm32mp1_ddrphy *)DDRPHYC_BASE; - priv->pwr = PWR_BASE; - priv->rcc = RCC_BASE; + priv->ctl = (struct stm32mp1_ddrctl *)stm32mp_ddrctrl_base(); + priv->phy = (struct stm32mp1_ddrphy *)stm32mp_ddrphyc_base(); + priv->pwr = stm32mp_pwr_base(); + priv->rcc = stm32mp_rcc_base(); priv->info.base = STM32MP_DDR_BASE; priv->info.size = 0; diff --git a/drivers/st/reset/stm32mp1_reset.c b/drivers/st/reset/stm32mp1_reset.c index b9a7ac7c98..b2de76085d 100644 --- a/drivers/st/reset/stm32mp1_reset.c +++ b/drivers/st/reset/stm32mp1_reset.c @@ -20,9 +20,10 @@ void stm32mp_reset_assert(uint32_t id) { uint32_t offset = (id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t); uint32_t bit = id % (uint32_t)__LONG_BIT; + uintptr_t rcc_base = stm32mp_rcc_base(); - mmio_write_32(RCC_BASE + offset, BIT(bit)); - while ((mmio_read_32(RCC_BASE + offset) & BIT(bit)) == 0U) { + mmio_write_32(rcc_base + offset, BIT(bit)); + while ((mmio_read_32(rcc_base + offset) & BIT(bit)) == 0U) { ; } } @@ -32,9 +33,10 @@ void stm32mp_reset_deassert(uint32_t id) uint32_t offset = ((id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t)) + RST_CLR_OFFSET; uint32_t bit = id % (uint32_t)__LONG_BIT; + uintptr_t rcc_base = stm32mp_rcc_base(); - mmio_write_32(RCC_BASE + offset, BIT(bit)); - while ((mmio_read_32(RCC_BASE + offset) & BIT(bit)) != 0U) { + mmio_write_32(rcc_base + offset, BIT(bit)); + while ((mmio_read_32(rcc_base + offset) & BIT(bit)) != 0U) { ; } } |