diff options
author | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-05-20 21:43:27 +0100 |
---|---|---|
committer | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-05-23 08:49:36 +0100 |
commit | 399fb08fff2e4a0cad4cd1cf0ece84db6670447f (patch) | |
tree | 870a276f6e367046f563809a9e9e186e958b640c /bl32/tsp/aarch64/tsp_entrypoint.S | |
parent | 239b04fa31647100c537852b4a3fc8bd47e33aa6 (diff) | |
download | trusted-firmware-a-399fb08fff2e4a0cad4cd1cf0ece84db6670447f.tar.gz |
Use a vector table for TSP entrypoints
The TSP has a number of entrypoints used by the TSP on different
occasions. These were provided to the TSPD as a table of function
pointers, and required the TSPD to read the entry in the table,
which is in TSP memory, in order to program the exception return
address.
Ideally, the TSPD has no access to the TSP memory.
This patch changes the table of function pointers into a vector
table of single instruction entrypoints. This allows the TSPD to
calculate the entrypoint address instead of read it.
Fixes ARM-software/tf-issues#160
Change-Id: Iec6e055d537ade78a45799fbc6f43765a4725ad3
Diffstat (limited to 'bl32/tsp/aarch64/tsp_entrypoint.S')
-rw-r--r-- | bl32/tsp/aarch64/tsp_entrypoint.S | 23 |
1 files changed, 16 insertions, 7 deletions
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 9999c432b4..8fdfbc396d 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -34,13 +34,7 @@ .globl tsp_entrypoint - .globl tsp_cpu_on_entry - .globl tsp_cpu_off_entry - .globl tsp_cpu_suspend_entry - .globl tsp_cpu_resume_entry - .globl tsp_fast_smc_entry - .globl tsp_std_smc_entry - .globl tsp_fiq_entry + .globl tsp_vector_table @@ -157,6 +151,21 @@ func tsp_entrypoint tsp_entrypoint_panic: b tsp_entrypoint_panic + + /* ------------------------------------------- + * Table of entrypoint vectors provided to the + * TSPD for the various entrypoints + * ------------------------------------------- + */ +func tsp_vector_table + b tsp_std_smc_entry + b tsp_fast_smc_entry + b tsp_cpu_on_entry + b tsp_cpu_off_entry + b tsp_cpu_resume_entry + b tsp_cpu_suspend_entry + b tsp_fiq_entry + /*--------------------------------------------- * This entrypoint is used by the TSPD when this * cpu is to be turned off through a CPU_OFF |