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authorMadhukar Pappireddy <madhukar.pappireddy@arm.com>2021-01-11 22:53:53 +0000
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2021-01-11 22:53:53 +0000
commita33668bd9a5c9f13b16894920b4db01b05563d7c (patch)
tree91e1ada82173d011b4c88fe08a3b48850b0b7bc9
parente8a96e3e235b9f9866cedc95babbc6c3750babea (diff)
parente43258fa0055b3d9b22be63dbe7ea9dd9ffc794f (diff)
downloadtrusted-firmware-a-a33668bd9a5c9f13b16894920b4db01b05563d7c.tar.gz
Merge "plat: xilinx: Fix non-MISRA compliant code" into integration
-rw-r--r--plat/xilinx/versal/bl31_versal_setup.c6
-rw-r--r--plat/xilinx/versal/plat_versal.c6
-rw-r--r--plat/xilinx/zynqmp/bl31_zynqmp_setup.c20
-rw-r--r--plat/xilinx/zynqmp/plat_zynqmp.c6
4 files changed, 25 insertions, 13 deletions
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 27991d3818..5e870ff5f2 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -34,8 +34,9 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
{
assert(sec_state_is_valid(type));
- if (type == NON_SECURE)
+ if (type == NON_SECURE) {
return &bl33_image_ep_info;
+ }
return &bl32_image_ep_info;
}
@@ -68,8 +69,9 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
VERSAL_UART_CLOCK,
VERSAL_UART_BAUDRATE,
&versal_runtime_console);
- if (rc == 0)
+ if (rc == 0) {
panic();
+ }
console_set_scope(&versal_runtime_console, CONSOLE_FLAG_BOOT |
CONSOLE_FLAG_RUNTIME);
diff --git a/plat/xilinx/versal/plat_versal.c b/plat/xilinx/versal/plat_versal.c
index a080a76a95..107eae66b1 100644
--- a/plat/xilinx/versal/plat_versal.c
+++ b/plat/xilinx/versal/plat_versal.c
@@ -9,11 +9,13 @@
int plat_core_pos_by_mpidr(u_register_t mpidr)
{
- if (mpidr & MPIDR_CLUSTER_MASK)
+ if (mpidr & MPIDR_CLUSTER_MASK) {
return -1;
+ }
- if ((mpidr & MPIDR_CPU_MASK) >= PLATFORM_CORE_COUNT)
+ if ((mpidr & MPIDR_CPU_MASK) >= PLATFORM_CORE_COUNT) {
return -1;
+ }
return versal_calc_core_pos(mpidr);
}
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index 8272d6221a..d4cd7f65b8 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -32,8 +32,9 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
{
assert(sec_state_is_valid(type));
- if (type == NON_SECURE)
+ if (type == NON_SECURE) {
return &bl33_image_ep_info;
+ }
return &bl32_image_ep_info;
}
@@ -99,10 +100,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info,
&bl33_image_ep_info,
atf_handoff_addr);
- if (ret == FSBL_HANDOFF_NO_STRUCT)
+ if (ret == FSBL_HANDOFF_NO_STRUCT) {
bl31_set_default_config();
- else if (ret != FSBL_HANDOFF_SUCCESS)
+ } else if (ret != FSBL_HANDOFF_SUCCESS) {
panic();
+ }
}
if (bl32_image_ep_info.pc) {
VERBOSE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
@@ -137,12 +139,14 @@ static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3];
int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
{
/* Validate 'handler' and 'id' parameters */
- if (!handler || id >= MAX_INTR_EL3)
+ if (!handler || id >= MAX_INTR_EL3) {
return -EINVAL;
+ }
/* Check if a handler has already been registered */
- if (type_el3_interrupt_table[id])
+ if (type_el3_interrupt_table[id]) {
return -EALREADY;
+ }
type_el3_interrupt_table[id] = handler;
@@ -157,8 +161,9 @@ static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
intr_id = plat_ic_get_pending_interrupt_id();
handler = type_el3_interrupt_table[intr_id];
- if (handler != NULL)
+ if (handler != NULL) {
handler(intr_id, flags, handle, cookie);
+ }
return 0;
}
@@ -181,8 +186,9 @@ void bl31_plat_runtime_setup(void)
set_interrupt_rm_flag(flags, NON_SECURE);
rc = register_interrupt_type_handler(INTR_TYPE_EL3,
rdo_el3_interrupt_handler, flags);
- if (rc)
+ if (rc) {
panic();
+ }
#endif
}
diff --git a/plat/xilinx/zynqmp/plat_zynqmp.c b/plat/xilinx/zynqmp/plat_zynqmp.c
index 906ce1b7fe..58a52a3bf1 100644
--- a/plat/xilinx/zynqmp/plat_zynqmp.c
+++ b/plat/xilinx/zynqmp/plat_zynqmp.c
@@ -9,11 +9,13 @@
int plat_core_pos_by_mpidr(u_register_t mpidr)
{
- if (mpidr & MPIDR_CLUSTER_MASK)
+ if (mpidr & MPIDR_CLUSTER_MASK) {
return -1;
+ }
- if ((mpidr & MPIDR_CPU_MASK) >= PLATFORM_CORE_COUNT)
+ if ((mpidr & MPIDR_CPU_MASK) >= PLATFORM_CORE_COUNT) {
return -1;
+ }
return zynqmp_calc_core_pos(mpidr);
}