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authorAndré Przywara <andre.przywara@arm.com>2020-06-29 11:50:47 +0000
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2020-06-29 11:50:47 +0000
commita021b2dd871bba7cbbb578f53105a477ba5bda54 (patch)
treec1ad2a4dec1d00ed037f239180b9e770eb2bb1e7
parentedd8188d32eb989c069da185f47425ac739bfdfd (diff)
parent506ffe50dedf53882b5c0ba9f82cd4f448e94d4f (diff)
downloadtrusted-firmware-a-a021b2dd871bba7cbbb578f53105a477ba5bda54.tar.gz
Merge "allwinner: Disable NS access to PRCM power control registers" into integration
-rw-r--r--plat/allwinner/common/sunxi_security.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/plat/allwinner/common/sunxi_security.c b/plat/allwinner/common/sunxi_security.c
index 1f16a0b72..92c83b06e 100644
--- a/plat/allwinner/common/sunxi_security.c
+++ b/plat/allwinner/common/sunxi_security.c
@@ -39,8 +39,8 @@ void sunxi_security_setup(void)
/* set MBUS clocks, bus clocks (AXI/AHB/APB) and PLLs to non-secure */
mmio_write_32(SUNXI_CCU_SEC_SWITCH_REG, 0x7);
- /* set R_PRCM clocks to non-secure */
- mmio_write_32(SUNXI_R_PRCM_BASE + R_PRCM_SEC_SWITCH_REG, 0x7);
+ /* Set R_PRCM bus clocks to non-secure */
+ mmio_write_32(SUNXI_R_PRCM_BASE + R_PRCM_SEC_SWITCH_REG, 0x1);
/* Set all DMA channels (16 max.) to non-secure */
mmio_write_32(SUNXI_DMA_BASE + DMA_SEC_REG, 0xffff);