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author | Mark Dykes <mardyk01@review.trustedfirmware.org> | 2020-06-25 18:37:51 +0000 |
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committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2020-06-25 18:37:51 +0000 |
commit | 24cdbb22a9da2eb7d07592774777012552a5dd41 (patch) | |
tree | 5357c652e9f7d739f9e9831bacc55eaa96c320fe | |
parent | 3c20ad568dcb1fa704d6cd6b16b7d85ba460546f (diff) | |
parent | 0754143ac9934f201d60f1a67cf0348c13da2c44 (diff) | |
download | trusted-firmware-a-24cdbb22a9da2eb7d07592774777012552a5dd41.tar.gz |
Merge "stm32mp1: use last page of SYSRAM as SCMI shared memory" into integration
-rw-r--r-- | plat/st/stm32mp1/sp_min/sp_min_setup.c | 18 | ||||
-rw-r--r-- | plat/st/stm32mp1/stm32mp1_def.h | 19 | ||||
-rw-r--r-- | plat/st/stm32mp1/stm32mp1_private.c | 24 |
3 files changed, 53 insertions, 8 deletions
diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c index e1799eda62..1f96239c83 100644 --- a/plat/st/stm32mp1/sp_min/sp_min_setup.c +++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c @@ -77,7 +77,25 @@ entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) return next_image_info; } +CASSERT((STM32MP_SEC_SYSRAM_BASE == STM32MP_SYSRAM_BASE) && + ((STM32MP_SEC_SYSRAM_BASE + STM32MP_SEC_SYSRAM_SIZE) <= + (STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE)), + assert_secure_sysram_fits_at_begining_of_sysram); + +#ifdef STM32MP_NS_SYSRAM_BASE +CASSERT((STM32MP_NS_SYSRAM_BASE >= STM32MP_SEC_SYSRAM_BASE) && + ((STM32MP_NS_SYSRAM_BASE + STM32MP_NS_SYSRAM_SIZE) == + (STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE)), + assert_non_secure_sysram_fits_at_end_of_sysram); + +CASSERT((STM32MP_NS_SYSRAM_BASE & (PAGE_SIZE_4KB - U(1))) == 0U, + assert_non_secure_sysram_base_is_4kbyte_aligned); + +#define TZMA1_SECURE_RANGE \ + (((STM32MP_NS_SYSRAM_BASE - STM32MP_SYSRAM_BASE) >> FOUR_KB_SHIFT) - 1U) +#else #define TZMA1_SECURE_RANGE STM32MP1_ETZPC_TZMA_ALL_SECURE +#endif /* STM32MP_NS_SYSRAM_BASE */ #define TZMA0_SECURE_RANGE STM32MP1_ETZPC_TZMA_ALL_SECURE static void stm32mp1_etzpc_early_setup(void) diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 0a12b6e57f..4fae2d70cb 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -56,6 +56,15 @@ #define STM32MP_SYSRAM_BASE U(0x2FFC0000) #define STM32MP_SYSRAM_SIZE U(0x00040000) +#define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE +#define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \ + STM32MP_SYSRAM_SIZE - \ + STM32MP_NS_SYSRAM_SIZE) + +#define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE +#define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \ + STM32MP_NS_SYSRAM_SIZE) + /* DDR configuration */ #define STM32MP_DDR_BASE U(0xC0000000) #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ @@ -81,18 +90,18 @@ enum ddr_type { /* 256 Octets reserved for header */ #define STM32MP_HEADER_SIZE U(0x00000100) -#define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ +#define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \ STM32MP_PARAM_LOAD_SIZE + \ STM32MP_HEADER_SIZE) -#define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ +#define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ (STM32MP_PARAM_LOAD_SIZE + \ STM32MP_HEADER_SIZE)) #ifdef AARCH32_SP_OPTEE #define STM32MP_BL32_SIZE U(0) -#define STM32MP_OPTEE_BASE STM32MP_SYSRAM_BASE +#define STM32MP_OPTEE_BASE STM32MP_SEC_SYSRAM_BASE #define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \ STM32MP_OPTEE_BASE) @@ -104,8 +113,8 @@ enum ddr_type { #endif #endif -#define STM32MP_BL32_BASE (STM32MP_SYSRAM_BASE + \ - STM32MP_SYSRAM_SIZE - \ +#define STM32MP_BL32_BASE (STM32MP_SEC_SYSRAM_BASE + \ + STM32MP_SEC_SYSRAM_SIZE - \ STM32MP_BL32_SIZE) #ifdef AARCH32_SP_OPTEE diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c index 779228d4a0..fd60db282b 100644 --- a/plat/st/stm32mp1/stm32mp1_private.c +++ b/plat/st/stm32mp1/stm32mp1_private.c @@ -30,12 +30,29 @@ BOARD_ID_REVISION_SHIFT) #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) -#define MAP_SRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ +#if defined(IMAGE_BL2) +#define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ STM32MP_SYSRAM_SIZE, \ MT_MEMORY | \ MT_RW | \ MT_SECURE | \ MT_EXECUTE_NEVER) +#elif defined(IMAGE_BL32) +#define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \ + STM32MP_SEC_SYSRAM_SIZE, \ + MT_MEMORY | \ + MT_RW | \ + MT_SECURE | \ + MT_EXECUTE_NEVER) + +/* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */ +#define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \ + STM32MP_NS_SYSRAM_SIZE, \ + MT_DEVICE | \ + MT_RW | \ + MT_NS | \ + MT_EXECUTE_NEVER) +#endif #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ STM32MP1_DEVICE1_SIZE, \ @@ -53,7 +70,7 @@ #if defined(IMAGE_BL2) static const mmap_region_t stm32mp1_mmap[] = { - MAP_SRAM, + MAP_SEC_SYSRAM, MAP_DEVICE1, MAP_DEVICE2, {0} @@ -61,7 +78,8 @@ static const mmap_region_t stm32mp1_mmap[] = { #endif #if defined(IMAGE_BL32) static const mmap_region_t stm32mp1_mmap[] = { - MAP_SRAM, + MAP_SEC_SYSRAM, + MAP_NS_SYSRAM, MAP_DEVICE1, MAP_DEVICE2, {0} |