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authorMadhukar Pappireddy <madhukar.pappireddy@arm.com>2020-02-13 15:36:50 -0600
committerMadhukar Pappireddy <madhukar.pappireddy@arm.com>2020-02-13 15:45:06 -0600
commit0ad5b318f7e8e7ff35b5e607e3d11c31efeb3872 (patch)
treee135b9ce756e2f067cc3bc82ea55c6705e1f4808
parent572fcdd547753d668ca1146ca420664ccc3ac6fb (diff)
downloadtrusted-firmware-a-0ad5b318f7e8e7ff35b5e607e3d11c31efeb3872.tar.gz
Fix topology description of cpus for DynamIQ based FVP
DynamIQ based designs have upto 8 CPUs in each cluster. This patch fixes the device tree node which describes the topology of the CPU for DynamIQ FVP Model. Change-Id: I7146bc79029ce38314026d4853e5b6406863725c Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
-rw-r--r--fdts/fvp-base-gicv3-psci-common.dtsi2
-rw-r--r--fdts/fvp-base-gicv3-psci-dynamiq-2t.dts2
-rw-r--r--fdts/fvp-base-gicv3-psci-dynamiq-common.dtsi40
-rw-r--r--fdts/fvp-base-gicv3-psci-dynamiq.dts2
4 files changed, 43 insertions, 3 deletions
diff --git a/fdts/fvp-base-gicv3-psci-common.dtsi b/fdts/fvp-base-gicv3-psci-common.dtsi
index 94ed67d55..5b0470d89 100644
--- a/fdts/fvp-base-gicv3-psci-common.dtsi
+++ b/fdts/fvp-base-gicv3-psci-common.dtsi
@@ -39,7 +39,7 @@
#address-cells = <2>;
#size-cells = <0>;
- cpu-map {
+ CPU_MAP:cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
diff --git a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
index 48269a065..daa2e66ce 100644
--- a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
+++ b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
@@ -6,7 +6,7 @@
/dts-v1/;
-#include "fvp-base-gicv3-psci-common.dtsi"
+#include "fvp-base-gicv3-psci-dynamiq-common.dtsi"
&CPU0 {
reg = <0x0 0x0>;
diff --git a/fdts/fvp-base-gicv3-psci-dynamiq-common.dtsi b/fdts/fvp-base-gicv3-psci-dynamiq-common.dtsi
new file mode 100644
index 000000000..f3f768417
--- /dev/null
+++ b/fdts/fvp-base-gicv3-psci-dynamiq-common.dtsi
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+#include "fvp-base-gicv3-psci-common.dtsi"
+
+/* DynamIQ based designs have upto 8 CPUs in each cluster */
+
+&CPU_MAP {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+ core1 {
+ cpu = <&CPU1>;
+ };
+ core2 {
+ cpu = <&CPU2>;
+ };
+ core3 {
+ cpu = <&CPU3>;
+ };
+ core4 {
+ cpu = <&CPU4>;
+ };
+ core5 {
+ cpu = <&CPU5>;
+ };
+ core6 {
+ cpu = <&CPU6>;
+ };
+ core7 {
+ cpu = <&CPU7>;
+ };
+ };
+};
diff --git a/fdts/fvp-base-gicv3-psci-dynamiq.dts b/fdts/fvp-base-gicv3-psci-dynamiq.dts
index 51c7acacf..b8b044500 100644
--- a/fdts/fvp-base-gicv3-psci-dynamiq.dts
+++ b/fdts/fvp-base-gicv3-psci-dynamiq.dts
@@ -6,7 +6,7 @@
/dts-v1/;
-#include "fvp-base-gicv3-psci-common.dtsi"
+#include "fvp-base-gicv3-psci-dynamiq-common.dtsi"
&CPU0 {
reg = <0x0 0x0>;