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authorAndre Przywara <andre.przywara@arm.com>2020-09-16 17:13:33 +0100
committerAndre Przywara <andre.przywara@arm.com>2020-09-29 13:28:25 +0100
commit01301b116ea32c6529a69bfc679cab2d2fdaa4d9 (patch)
tree367b4d799b419f69f3b09c5eb2878f22cd877384
parentf45c6d8623309a256718212a1a2c72ad5efe925d (diff)
downloadtrusted-firmware-a-01301b116ea32c6529a69bfc679cab2d2fdaa4d9.tar.gz
arm_fpga: Add post-build linker script
For the Arm Ltd. FPGAs to run, we need to load several payloads into the FPGA's memory: - Some trampoline code at address 0x0, to jump to BL31's entry point. - The actual BL31 binary at the beginning of DRAM. - The (generic) DTB image to describe the hardware. - The actual non-secure payloads (kernel, ramdisks, ...) The latter is application specific, but the first three blobs are rather generic. Since the uploader tool supports ELF binaries, it seems helpful to combine these three images into one .axf file, as this also simplifies the command line. Add a post-build linker script, that combines those three bits into one ELF file, together with their specific load addresses. Include a call to "ld" with this linker script in the platform Makefile, so it will be build automatically. The result will be called "bl31.axf". Change-Id: I4a90da16fa1e0e83b51d19e5b1daf61f5a0bbfca Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-rw-r--r--plat/arm/board/arm_fpga/build_axf.ld.S47
-rw-r--r--plat/arm/board/arm_fpga/platform.mk7
2 files changed, 53 insertions, 1 deletions
diff --git a/plat/arm/board/arm_fpga/build_axf.ld.S b/plat/arm/board/arm_fpga/build_axf.ld.S
new file mode 100644
index 0000000000..d7cd00882a
--- /dev/null
+++ b/plat/arm/board/arm_fpga/build_axf.ld.S
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2020, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Linker script for the Arm Ltd. FPGA boards to generate an ELF file that
+ * contains the ROM trampoline, BL31 and the DTB.
+ *
+ * This allows to pass just one file to the uploader tool, and automatically
+ * provides the correct load addresses.
+ */
+
+#include <platform_def.h>
+
+OUTPUT_FORMAT("elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+
+INPUT(./bl31/bl31.elf)
+INPUT(./rom_trampoline.o)
+
+TARGET(binary)
+INPUT(./fdts/arm_fpga.dtb)
+
+ENTRY(_start)
+
+SECTIONS
+{
+ .rom (0x0): {
+ *rom_trampoline.o(.text*)
+ KEEP(*(.rom))
+ }
+
+ .bl31 (BL31_BASE): {
+ ASSERT(. == ALIGN(PAGE_SIZE), "BL31_BASE is not page aligned");
+ *bl31.elf(.text* .data* .rodata* ro* .bss*)
+ *bl31.elf(.stack)
+ }
+
+ .dtb (FPGA_PRELOADED_DTB_BASE): {
+ ASSERT(. == ALIGN(8), "DTB address is not 8-byte aligned");
+ *arm_fpga.dtb
+ }
+
+ /DISCARD/ : { *(.debug_*) }
+ /DISCARD/ : { *(.note*) }
+ /DISCARD/ : { *(.comment*) }
+}
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index f3be3cd32d..ad9001b56a 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -101,5 +101,10 @@ BL31_SOURCES += common/fdt_wrappers.c \
${FPGA_GIC_SOURCES}
$(eval $(call MAKE_S,$(BUILD_PLAT),plat/arm/board/arm_fpga/rom_trampoline.S,31))
+$(eval $(call MAKE_LD,$(BUILD_PLAT)/build_axf.ld,plat/arm/board/arm_fpga/build_axf.ld.S,31))
-all: bl31
+bl31.axf: bl31 dtbs ${BUILD_PLAT}/rom_trampoline.o ${BUILD_PLAT}/build_axf.ld
+ $(ECHO) " LD $@"
+ $(Q)$(LD) -T ${BUILD_PLAT}/build_axf.ld -L ${BUILD_PLAT} --strip-debug -o ${BUILD_PLAT}/bl31.axf
+
+all: bl31.axf