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author | Jimmy Brisson <jimmy.brisson@arm.com> | 2020-01-08 13:52:51 -0600 |
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committer | Jimmy Brisson <jimmy.brisson@arm.com> | 2020-02-18 09:00:04 -0600 |
commit | da3b47e925a9a524538f9e471a20327b8112f75b (patch) | |
tree | adec3622a8814fed8a86b5dae9df24c7cae11c28 | |
parent | f4744720a00c130bbc46e7cf22af46a3526ee550 (diff) | |
download | trusted-firmware-a-da3b47e925a9a524538f9e471a20327b8112f75b.tar.gz |
Add Matterhorn CPU lib
Also update copyright statements
Change-Id: Iba0305522ac0f2ddc4da99127fd773f340e67300
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
-rw-r--r-- | include/lib/cpus/aarch64/cortex_matterhorn.h | 23 | ||||
-rw-r--r-- | lib/cpus/aarch64/cortex_matterhorn.S | 77 | ||||
-rw-r--r-- | plat/arm/board/fvp/platform.mk | 1 |
3 files changed, 101 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_matterhorn.h b/include/lib/cpus/aarch64/cortex_matterhorn.h new file mode 100644 index 0000000000..018553359b --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_matterhorn.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_MATTERHORN_H +#define CORTEX_MATTERHORN_H + +#define CORTEX_MATTERHORN_MIDR U(0x410FD470) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_MATTERHORN_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_MATTERHORN_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_MATTERHORN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_MATTERHORN_H */ diff --git a/lib/cpus/aarch64/cortex_matterhorn.S b/lib/cpus/aarch64/cortex_matterhorn.S new file mode 100644 index 0000000000..4156f3cf89 --- /dev/null +++ b/lib/cpus/aarch64/cortex_matterhorn.S @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2020, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <common/bl_common.h> +#include <cortex_matterhorn.h> +#include <cpu_macros.S> +#include <plat_macros.S> + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex Matterhorn must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex Matterhorn supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_matterhorn_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + mrs x0, CORTEX_MATTERHORN_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_MATTERHORN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_MATTERHORN_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_matterhorn_core_pwr_dwn + + /* + * Errata printing function for Cortex Matterhorn. Must follow AAPCS. + */ +#if REPORT_ERRATA +func cortex_matterhorn_errata_report + ret +endfunc cortex_matterhorn_errata_report +#endif + +func cortex_matterhorn_reset_func + /* Disable speculative loads */ + msr SSBS, xzr + isb + ret +endfunc cortex_matterhorn_reset_func + + /* --------------------------------------------- + * This function provides Cortex-Matterhorn specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_matterhorn_regs, "aS" +cortex_matterhorn_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_matterhorn_cpu_reg_dump + adr x6, cortex_matterhorn_regs + mrs x8, CORTEX_MATTERHORN_CPUECTLR_EL1 + ret +endfunc cortex_matterhorn_cpu_reg_dump + +declare_cpu_ops cortex_matterhorn, CORTEX_MATTERHORN_MIDR, \ + cortex_matterhorn_reset_func, \ + cortex_matterhorn_core_pwr_dwn diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 65dc5457f9..4176968f89 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -123,6 +123,7 @@ else lib/cpus/aarch64/cortex_hercules.S \ lib/cpus/aarch64/cortex_hercules_ae.S \ lib/cpus/aarch64/cortex_klein.S \ + lib/cpus/aarch64/cortex_matterhorn.S \ lib/cpus/aarch64/cortex_a65.S \ lib/cpus/aarch64/cortex_a65ae.S endif |