aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorjoanna.farley <joanna.farley@arm.com>2020-02-21 10:59:46 +0000
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2020-02-21 10:59:46 +0000
commit876b38497eff517e751c5f627d62065ce94c242a (patch)
tree78f48464c958a06e2c34fad212e548ba8727fd3e
parenteda880ff8ec77ee429f5249f08571c41232b27db (diff)
parent8a47fe4375234120b041f55e578d051453514e67 (diff)
downloadtrusted-firmware-a-876b38497eff517e751c5f627d62065ce94c242a.tar.gz
Merge changes from topic "tegra-downstream-02092020" into integration
* changes: Tegra: spe: uninit console on a timeout Tegra: handler to check support for System Suspend Tegra: bpmp_ipc: improve cyclomatic complexity Tegra: platform handler to relocate BL32 image Tegra: common: improve cyclomatic complexity Tegra210: secure PMC hardware block Tegra: delay_timer: support for physical secure timer include: move MHZ_TICKS_PER_SEC to utils_def.h Tegra194: memctrl: lock mc stream id security config Tegra210: resume PMC hardware block for all platforms Tegra: macro for legacy WDT FIQ handling Tegra186: enable higher performance non-cacheable load forwarding Tegra210: enable higher performance non-cacheable load forwarding cpus: higher performance non-cacheable load forwarding
-rw-r--r--docs/design/cpu-specific-build-macros.rst7
-rw-r--r--drivers/delay_timer/generic_delay_timer.c5
-rw-r--r--include/arch/aarch64/arch.h5
-rw-r--r--include/lib/cpus/aarch64/cortex_a57.h2
-rw-r--r--include/lib/utils_def.h6
-rw-r--r--lib/cpus/aarch64/cortex_a57.S12
-rw-r--r--lib/cpus/cpu-ops.mk9
-rw-r--r--plat/common/plat_psci_common.c5
-rw-r--r--plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c55
-rw-r--r--plat/nvidia/tegra/common/drivers/spe/shared_console.S37
-rw-r--r--plat/nvidia/tegra/common/tegra_bl31_setup.c63
-rw-r--r--plat/nvidia/tegra/common/tegra_delay_timer.c46
-rw-r--r--plat/nvidia/tegra/common/tegra_pm.c10
-rw-r--r--plat/nvidia/tegra/include/tegra_private.h3
-rw-r--r--plat/nvidia/tegra/platform.mk11
-rw-r--r--plat/nvidia/tegra/soc/t132/plat_setup.c8
-rw-r--r--plat/nvidia/tegra/soc/t186/plat_setup.c51
-rw-r--r--plat/nvidia/tegra/soc/t186/platform_t186.mk6
-rw-r--r--plat/nvidia/tegra/soc/t194/plat_memctrl.c218
-rw-r--r--plat/nvidia/tegra/soc/t194/plat_setup.c11
-rw-r--r--plat/nvidia/tegra/soc/t210/plat_psci_handlers.c20
-rw-r--r--plat/nvidia/tegra/soc/t210/plat_setup.c25
-rw-r--r--plat/nvidia/tegra/soc/t210/platform_t210.mk3
23 files changed, 401 insertions, 217 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index f3096b4186..258f73d0b7 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -324,6 +324,13 @@ architecture that can be enabled by the platform as desired.
as recommended in section "4.7 Non-Temporal Loads/Stores" of the
`Cortex-A57 Software Optimization Guide`_.
+- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable
+ streaming enhancement feature for Cortex-A57 CPUs. Platforms can set
+ this bit only if their memory system meets the requirement that cache
+ line fill requests from the Cortex-A57 processor are atomic. Each
+ Cortex-A57 based platform must make its own decision on whether to use
+ the optimization. This flag is disabled by default.
+
- ``NEOVERSE_N1_EXTERNAL_LLC``: This flag indicates that an external last
level cache(LLC) is present in the system, and that the DataSource field
on the master CHI interface indicates when data is returned from the LLC.
diff --git a/drivers/delay_timer/generic_delay_timer.c b/drivers/delay_timer/generic_delay_timer.c
index 3d0a11f595..ca522e05ab 100644
--- a/drivers/delay_timer/generic_delay_timer.c
+++ b/drivers/delay_timer/generic_delay_timer.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,11 +13,9 @@
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <drivers/generic_delay_timer.h>
+#include <lib/utils_def.h>
#include <plat/common/platform.h>
-/* Ticks elapsed in one second by a signal of 1 MHz */
-#define MHZ_TICKS_PER_SEC 1000000
-
static timer_ops_t ops;
static uint32_t get_timer_value(void)
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 1fcd0f9ba5..1faddbedc4 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -597,6 +598,10 @@
#define CNTP_CTL_IMASK_MASK U(1)
#define CNTP_CTL_ISTATUS_MASK U(1)
+/* Physical timer control macros */
+#define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT)
+#define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT)
+
/* Exception Syndrome register bits and bobs */
#define ESR_EC_SHIFT U(26)
#define ESR_EC_MASK U(0x3f)
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index 102ff60c3a..dc40e31adf 100644
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -54,6 +55,7 @@
#define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38)
#define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
#define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27)
+#define CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD (ULL(1) << 24)
#define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25)
#define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 23f59bdc33..09ae3999db 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -157,4 +158,9 @@
# define SPECULATION_SAFE_VALUE(var) var
#endif
+/*
+ * Ticks elapsed in one second with a signal of 1 MHz
+ */
+#define MHZ_TICKS_PER_SEC U(1000000)
+
#endif /* UTILS_DEF_H */
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index dd03c0f022..3fee4704e8 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -469,6 +470,17 @@ func cortex_a57_reset_func
dsb sy
#endif
+#if A57_ENABLE_NONCACHEABLE_LOAD_FWD
+ /* ---------------------------------------------
+ * Enable higher performance non-cacheable load
+ * forwarding
+ * ---------------------------------------------
+ */
+ mrs x0, CORTEX_A57_CPUACTLR_EL1
+ orr x0, x0, #CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD
+ msr CORTEX_A57_CPUACTLR_EL1, x0
+#endif
+
/* ---------------------------------------------
* Enable the SMP bit.
* ---------------------------------------------
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index e3bfc2f2e8..3c0c9cd135 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -1,5 +1,6 @@
#
# Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -16,6 +17,10 @@ A53_DISABLE_NON_TEMPORAL_HINT ?=1
# It is enabled by default.
A57_DISABLE_NON_TEMPORAL_HINT ?=1
+# Flag to enable higher performance non-cacheable load forwarding.
+# It is disabled by default.
+A57_ENABLE_NONCACHEABLE_LOAD_FWD ?= 0
+
WORKAROUND_CVE_2017_5715 ?=1
WORKAROUND_CVE_2018_3639 ?=1
DYNAMIC_WORKAROUND_CVE_2018_3639 ?=0
@@ -24,6 +29,10 @@ DYNAMIC_WORKAROUND_CVE_2018_3639 ?=0
# By default internal
NEOVERSE_N1_EXTERNAL_LLC ?=0
+# Process A57_ENABLE_NONCACHEABLE_LOAD_FWD flag
+$(eval $(call assert_boolean,A57_ENABLE_NONCACHEABLE_LOAD_FWD))
+$(eval $(call add_define,A57_ENABLE_NONCACHEABLE_LOAD_FWD))
+
# Process SKIP_A57_L1_FLUSH_PWR_DWN flag
$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN))
$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN))
diff --git a/plat/common/plat_psci_common.c b/plat/common/plat_psci_common.c
index 80ed8198b2..bed8890a73 100644
--- a/plat/common/plat_psci_common.c
+++ b/plat/common/plat_psci_common.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +10,7 @@
#include <arch.h>
#include <lib/pmf/pmf.h>
#include <lib/psci/psci.h>
+#include <lib/utils_def.h>
#include <plat/common/platform.h>
#if ENABLE_PSCI_STAT && ENABLE_PMF
@@ -16,9 +18,6 @@
#pragma weak plat_psci_stat_accounting_stop
#pragma weak plat_psci_stat_get_residency
-/* Ticks elapsed in one second by a signal of 1 MHz */
-#define MHZ_TICKS_PER_SEC 1000000U
-
/* Maximum time-stamp value read from architectural counters */
#ifdef __aarch64__
#define MAX_TS UINT64_MAX
diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c b/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c
index eaf96751ce..2e90d25474 100644
--- a/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c
+++ b/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c
@@ -175,44 +175,39 @@ static int32_t tegra_bpmp_ipc_send_req_atomic(uint32_t mrq, void *p_out,
if ((p_out == NULL) || (size_out > IVC_DATA_SZ_BYTES) ||
(frame == NULL)) {
ERROR("%s: invalid parameters, exiting\n", __func__);
- ret = -EINVAL;
+ return -EINVAL;
}
- if (ret == 0) {
-
- /* prepare the command frame */
- frame->mrq = mrq;
- frame->flags = FLAG_DO_ACK;
- p_fdata = frame->data;
- (void)memcpy(p_fdata, p_out, (size_t)size_out);
+ /* prepare the command frame */
+ frame->mrq = mrq;
+ frame->flags = FLAG_DO_ACK;
+ p_fdata = frame->data;
+ (void)memcpy(p_fdata, p_out, (size_t)size_out);
- /* signal the slave */
- tegra_bpmp_signal_slave();
+ /* signal the slave */
+ tegra_bpmp_signal_slave();
- /* wait for slave to ack */
- ret = tegra_bpmp_wait_for_slave_ack();
- if (ret != 0) {
- ERROR("failed waiting for the slave to ack\n");
- }
+ /* wait for slave to ack */
+ ret = tegra_bpmp_wait_for_slave_ack();
+ if (ret < 0) {
+ ERROR("%s: wait for slave failed (%d)\n", __func__, ret);
+ return ret;
+ }
- /* retrieve the response frame */
- if ((size_in <= IVC_DATA_SZ_BYTES) && (p_in != NULL) &&
- (ret == 0)) {
+ /* retrieve the response frame */
+ if ((size_in <= IVC_DATA_SZ_BYTES) && (p_in != NULL)) {
- f_in = tegra_bpmp_get_cur_in_frame();
- if (f_in != NULL) {
- ERROR("Failed to get next input frame!\n");
- } else {
- (void)memcpy(p_in, p_fdata, (size_t)size_in);
- }
+ f_in = tegra_bpmp_get_cur_in_frame();
+ if (f_in != NULL) {
+ ERROR("Failed to get next input frame!\n");
+ } else {
+ (void)memcpy(p_in, p_fdata, (size_t)size_in);
}
+ }
- if (ret == 0) {
- ret = tegra_bpmp_free_master();
- if (ret != 0) {
- ERROR("Failed to free master\n");
- }
- }
+ ret = tegra_bpmp_free_master();
+ if (ret < 0) {
+ ERROR("%s: free master failed (%d)\n", __func__, ret);
}
return ret;
diff --git a/plat/nvidia/tegra/common/drivers/spe/shared_console.S b/plat/nvidia/tegra/common/drivers/spe/shared_console.S
index a3e110ec98..0be34e4173 100644
--- a/plat/nvidia/tegra/common/drivers/spe/shared_console.S
+++ b/plat/nvidia/tegra/common/drivers/spe/shared_console.S
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +11,7 @@
#define CONSOLE_FLUSH_DATA_TO_PORT (1 << 26)
#define CONSOLE_RING_DOORBELL (1 << 31)
#define CONSOLE_IS_BUSY (1 << 31)
+#define CONSOLE_TIMEOUT 0xC000 /* approx. 50 ms */
#define CONSOLE_WRITE (CONSOLE_RING_DOORBELL | CONSOLE_FLUSH_DATA_TO_PORT)
/*
@@ -30,6 +32,20 @@
.globl console_spe_flush
.globl console_spe_register
+.macro check_if_console_is_ready base, tmp1, tmp2, label
+ /* wait until spe is ready or timeout expires */
+ mrs \tmp2, cntps_tval_el1
+1: ldr \tmp1, [\base]
+ and \tmp1, \tmp1, #CONSOLE_IS_BUSY
+ cbz \tmp1, 2f
+ mrs \tmp1, cntps_tval_el1
+ sub \tmp1, \tmp2, \tmp1
+ cmp \tmp1, #CONSOLE_TIMEOUT
+ b.lt 1b
+ b \label
+2:
+.endm
+
/* -------------------------------------------------
* int console_spe_register(uintptr_t baseaddr,
* uint32_t clock, uint32_t baud,
@@ -46,6 +62,12 @@
* -------------------------------------------------
*/
func console_spe_register
+ /* Check the input base address */
+ cbz x0, register_fail
+
+ /* Dont use clock or baud rate, so ok to overwrite them */
+ check_if_console_is_ready x0, x1, x2, register_fail
+
cbz x3, register_fail
str x0, [x3, #CONSOLE_T_DRVDATA]
mov x0, x3
@@ -63,7 +85,7 @@ endfunc console_spe_register
* In : w0 - character to be printed
* x1 - console base address
* Out : return -1 on error else return character.
- * Clobber list : x2
+ * Clobber list : x2, x3
* --------------------------------------------------------
*/
func console_spe_core_putc
@@ -72,12 +94,9 @@ func console_spe_core_putc
/* Prepend '\r' to '\n' */
cmp w0, #0xA
- b.ne 2f
+ b.ne not_eol
- /* wait until spe is ready */
-1: ldr w2, [x1]
- and w2, w2, #CONSOLE_IS_BUSY
- cbnz w2, 1b
+ check_if_console_is_ready x1, x2, x3, putc_error
/* spe is ready */
mov w2, #0xD /* '\r' */
@@ -86,10 +105,8 @@ func console_spe_core_putc
orr w2, w2, w3
str w2, [x1]
- /* wait until spe is ready */
-2: ldr w2, [x1]
- and w2, w2, #CONSOLE_IS_BUSY
- cbnz w2, 2b
+not_eol:
+ check_if_console_is_ready x1, x2, x3, putc_error
/* spe is ready */
mov w2, w0
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 8a49e232db..46686c368c 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -34,8 +35,6 @@
/* length of Trusty's input parameters (in bytes) */
#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
-extern void memcpy16(void *dest, const void *src, unsigned int length);
-
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
@@ -101,8 +100,6 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
{
struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
- image_info_t bl32_img_info = { {0} };
- uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
int32_t ret;
/*
@@ -163,20 +160,17 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
* location to store the boot profiler logs. Sanity check the
* address and initialise the profiler library, if it looks ok.
*/
- if (plat_params->boot_profiler_shmem_base != 0ULL) {
-
- ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base,
- PROFILER_SIZE_BYTES);
- if (ret == (int32_t)0) {
+ ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base,
+ PROFILER_SIZE_BYTES);
+ if (ret == (int32_t)0) {
- /* store the membase for the profiler lib */
- plat_bl31_params_from_bl2.boot_profiler_shmem_base =
- plat_params->boot_profiler_shmem_base;
+ /* store the membase for the profiler lib */
+ plat_bl31_params_from_bl2.boot_profiler_shmem_base =
+ plat_params->boot_profiler_shmem_base;
- /* initialise the profiler library */
- boot_profiler_init(plat_params->boot_profiler_shmem_base,
- TEGRA_TMRUS_BASE);
- }
+ /* initialise the profiler library */
+ boot_profiler_init(plat_params->boot_profiler_shmem_base,
+ TEGRA_TMRUS_BASE);
}
/*
@@ -198,41 +192,14 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
(uint32_t)plat_bl31_params_from_bl2.tzdram_size);
+#if RELOCATE_BL32_IMAGE
/*
* The previous bootloader might not have placed the BL32 image
- * inside the TZDRAM. We check the BL32 image info to find out
- * the base/PC values and relocate the image if necessary.
+ * inside the TZDRAM. Platform handler to allow relocation of BL32
+ * image to TZDRAM memory. This behavior might change per platform.
*/
- if (arg_from_bl2->bl32_image_info != NULL) {
-
- bl32_img_info = *arg_from_bl2->bl32_image_info;
-
- /* Relocate BL32 if it resides outside of the TZDRAM */
- tzdram_start = plat_bl31_params_from_bl2.tzdram_base;
- tzdram_end = plat_bl31_params_from_bl2.tzdram_base +
- plat_bl31_params_from_bl2.tzdram_size;
- bl32_start = bl32_img_info.image_base;
- bl32_end = bl32_img_info.image_base + bl32_img_info.image_size;
-
- assert(tzdram_end > tzdram_start);
- assert(bl32_end > bl32_start);
- assert(bl32_image_ep_info.pc > tzdram_start);
- assert(bl32_image_ep_info.pc < tzdram_end);
-
- /* relocate BL32 */
- if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) {
-
- INFO("Relocate BL32 to TZDRAM\n");
-
- (void)memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc,
- (void *)(uintptr_t)bl32_start,
- bl32_img_info.image_size);
-
- /* clean up non-secure intermediate buffer */
- zeromem((void *)(uintptr_t)bl32_start,
- bl32_img_info.image_size);
- }
- }
+ plat_relocate_bl32_image(arg_from_bl2->bl32_image_info);
+#endif
/*
* Add timestamp for platform early setup exit.
diff --git a/plat/nvidia/tegra/common/tegra_delay_timer.c b/plat/nvidia/tegra/common/tegra_delay_timer.c
index 63dcf410c2..cfd9a15e30 100644
--- a/plat/nvidia/tegra/common/tegra_delay_timer.c
+++ b/plat/nvidia/tegra/common/tegra_delay_timer.c
@@ -1,31 +1,59 @@
/*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <arch.h>
+
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <plat/common/platform.h>
#include <tegra_def.h>
#include <tegra_private.h>
-static uint32_t tegra_timerus_get_value(void)
+static uint32_t tegra_timer_get_value(void)
{
- return mmio_read_32(TEGRA_TMRUS_BASE);
+ /* enable cntps_tval_el1 timer, mask interrupt */
+ write_cntps_ctl_el1(CNTP_CTL_IMASK_BIT | CNTP_CTL_ENABLE_BIT);
+
+ /*
+ * Generic delay timer implementation expects the timer to be a down
+ * counter. We apply bitwise NOT operator to the tick values returned
+ * by read_cntps_tval_el1() to simulate the down counter. The value is
+ * clipped from 64 to 32 bits.
+ */
+ return (uint32_t)(~read_cntps_tval_el1());
}
/*
- * Initialise the on-chip free rolling us counter as the delay
- * timer.
+ * Initialise the architecture provided counter as the delay timer.
*/
void tegra_delay_timer_init(void)
{
- static const timer_ops_t tegra_timer_ops = {
- .get_timer_value = tegra_timerus_get_value,
- .clk_mult = 1,
- .clk_div = 1,
- };
+ static timer_ops_t tegra_timer_ops;
+
+ /* Value in ticks */
+ uint32_t multiplier = MHZ_TICKS_PER_SEC;
+
+ /* Value in ticks per second (Hz) */
+ uint32_t divider = plat_get_syscnt_freq2();
+
+ /* Reduce multiplier and divider by dividing them repeatedly by 10 */
+ while (((multiplier % 10U) == 0U) && ((divider % 10U) == 0U)) {
+ multiplier /= 10U;
+ divider /= 10U;
+ }
+
+ /* enable cntps_tval_el1 timer, mask interrupt */
+ write_cntps_ctl_el1(CNTP_CTL_IMASK_BIT | CNTP_CTL_ENABLE_BIT);
+ /* register the timer */
+ tegra_timer_ops.get_timer_value = tegra_timer_get_value;
+ tegra_timer_ops.clk_mult = multiplier;
+ tegra_timer_ops.clk_div = divider;
timer_init(&tegra_timer_ops);
}
diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c
index 1f59f30aad..5ec6f849ee 100644
--- a/plat/nvidia/tegra/common/tegra_pm.c
+++ b/plat/nvidia/tegra/common/tegra_pm.c
@@ -259,7 +259,7 @@ int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint)
/*******************************************************************************
* Export the platform handlers to enable psci to invoke them
******************************************************************************/
-static const plat_psci_ops_t tegra_plat_psci_ops = {
+static plat_psci_ops_t tegra_plat_psci_ops = {
.cpu_standby = tegra_cpu_standby,
.pwr_domain_on = tegra_pwr_domain_on,
.pwr_domain_off = tegra_pwr_domain_off,
@@ -296,6 +296,14 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint,
(void)tegra_soc_pwr_domain_on_finish(&target_state);
/*
+ * Disable System Suspend if the platform does not
+ * support it
+ */
+ if (!plat_supports_system_suspend()) {
+ tegra_plat_psci_ops.get_sys_suspend_power_state = NULL;
+ }
+
+ /*
* Initialize PSCI ops struct
*/
*psci_ops = &tegra_plat_psci_ops;
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index b419d94e5a..ad3cee4b45 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -9,6 +9,7 @@
#define TEGRA_PRIVATE_H
#include <platform_def.h>
+#include <stdbool.h>
#include <arch.h>
#include <arch_helpers.h>
@@ -77,6 +78,8 @@ struct tegra_bl31_params *plat_get_bl31_params(void);
plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
void plat_early_platform_setup(void);
void plat_late_platform_setup(void);
+void plat_relocate_bl32_image(const image_info_t *bl32_img_info);
+bool plat_supports_system_suspend(void);
/* Declarations for plat_secondary.c */
void plat_secondary_setup(void);
diff --git a/plat/nvidia/tegra/platform.mk b/plat/nvidia/tegra/platform.mk
index 0917d87012..d0ed5d57ae 100644
--- a/plat/nvidia/tegra/platform.mk
+++ b/plat/nvidia/tegra/platform.mk
@@ -1,5 +1,6 @@
#
# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -37,9 +38,19 @@ WARMBOOT_ENABLE_DCACHE_EARLY := 1
# remove the standard libc
OVERRIDE_LIBC := 1
+# Flag to enable WDT FIQ interrupt handling for Tegra SoCs
+# prior to Tegra186
+ENABLE_WDT_LEGACY_FIQ_HANDLING ?= 0
+
+# Flag to allow relocation of BL32 image to TZDRAM during boot
+RELOCATE_BL32_IMAGE ?= 0
+
include plat/nvidia/tegra/common/tegra_common.mk
include ${SOC_DIR}/platform_${TARGET_SOC}.mk
+$(eval $(call add_define,ENABLE_WDT_LEGACY_FIQ_HANDLING))
+$(eval $(call add_define,RELOCATE_BL32_IMAGE))
+
# modify BUILD_PLAT to point to SoC specific build directory
BUILD_PLAT := ${BUILD_BASE}/${PLAT}/${TARGET_SOC}/${BUILD_TYPE}
diff --git a/plat/nvidia/tegra/soc/t132/plat_setup.c b/plat/nvidia/tegra/soc/t132/plat_setup.c
index 2f54dd5253..4bfc2de0e9 100644
--- a/plat/nvidia/tegra/soc/t132/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t132/plat_setup.c
@@ -154,3 +154,11 @@ void plat_late_platform_setup(void)
{
; /* do nothing */
}
+
+/*******************************************************************************
+ * Handler to indicate support for System Suspend
+ ******************************************************************************/
+bool plat_supports_system_suspend(void)
+{
+ return true;
+}
diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c
index 7e18b5c421..06a328427f 100644
--- a/plat/nvidia/tegra/soc/t186/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t186/plat_setup.c
@@ -12,6 +12,7 @@
#include <bl31/interrupt_mgmt.h>
#include <common/bl_common.h>
#include <common/debug.h>
+#include <common/ep_info.h>
#include <common/interrupt_props.h>
#include <context.h>
#include <cortex_a57.h>
@@ -20,6 +21,7 @@
#include <drivers/arm/gicv2.h>
#include <drivers/console.h>
#include <lib/el3_runtime/context_mgmt.h>
+#include <lib/utils.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
@@ -28,6 +30,8 @@
#include <tegra_platform.h>
#include <tegra_private.h>
+extern void memcpy16(void *dest, const void *src, unsigned int length);
+
/*******************************************************************************
* Tegra186 CPU numbers in cluster #0
*******************************************************************************
@@ -286,3 +290,50 @@ int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
return ret;
}
+
+/*******************************************************************************
+ * Handler to relocate BL32 image to TZDRAM
+ ******************************************************************************/
+void plat_relocate_bl32_image(const image_info_t *bl32_img_info)
+{
+ const plat_params_from_bl2_t *plat_bl31_params = plat_get_bl31_plat_params();
+ const entry_point_info_t *bl32_ep_info = bl31_plat_get_next_image_ep_info(SECURE);
+ uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
+
+ if ((bl32_img_info != NULL) && (bl32_ep_info != NULL)) {
+
+ /* Relocate BL32 if it resides outside of the TZDRAM */
+ tzdram_start = plat_bl31_params->tzdram_base;
+ tzdram_end = plat_bl31_params->tzdram_base +
+ plat_bl31_params->tzdram_size;
+ bl32_start = bl32_img_info->image_base;
+ bl32_end = bl32_img_info->image_base + bl32_img_info->image_size;
+
+ assert(tzdram_end > tzdram_start);
+ assert(bl32_end > bl32_start);
+ assert(bl32_ep_info->pc > tzdram_start);
+ assert(bl32_ep_info->pc < tzdram_end);
+
+ /* relocate BL32 */
+ if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) {
+
+ INFO("Relocate BL32 to TZDRAM\n");
+
+ (void)memcpy16((void *)(uintptr_t)bl32_ep_info->pc,
+ (void *)(uintptr_t)bl32_start,
+ bl32_img_info->image_size);
+
+ /* clean up non-secure intermediate buffer */
+ zeromem((void *)(uintptr_t)bl32_start,
+ bl32_img_info->image_size);
+ }
+ }
+}
+
+/*******************************************************************************
+ * Handler to indicate support for System Suspend
+ ******************************************************************************/
+bool plat_supports_system_suspend(void)
+{
+ return true;
+}
diff --git a/plat/nvidia/tegra/soc/t186/platform_t186.mk b/plat/nvidia/tegra/soc/t186/platform_t186.mk
index fe158536c7..197e4c6bad 100644
--- a/plat/nvidia/tegra/soc/t186/platform_t186.mk
+++ b/plat/nvidia/tegra/soc/t186/platform_t186.mk
@@ -1,5 +1,6 @@
#
# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -17,6 +18,8 @@ PROGRAMMABLE_RESET_ADDRESS := 1
COLD_BOOT_SINGLE_CPU := 1
+RELOCATE_BL32_IMAGE := 1
+
# platform settings
TZDRAM_BASE := 0x30000000
$(eval $(call add_define,TZDRAM_BASE))
@@ -64,3 +67,6 @@ ERRATA_A57_826977 := 1
ERRATA_A57_828024 := 1
ERRATA_A57_829520 := 1
ERRATA_A57_833471 := 1
+
+# Enable higher performance Non-cacheable load forwarding
+A57_ENABLE_NONCACHEABLE_LOAD_FWD := 1
diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
index bb1dd6706f..2208b85e74 100644
--- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
@@ -145,13 +145,13 @@ const static uint32_t tegra194_streamid_override_regs[] = {
* Array to hold the security configs for stream IDs
******************************************************************************/
const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = {
- mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE),
@@ -160,115 +160,115 @@ const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = {
mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
- mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, DISABLE),
mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(PCIE0R1, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PCIE0R1, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, DISABLE),
+ mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, DISABLE)
};
/* To be called by common memctrl_v2.c */
diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c
index 912dcc6f96..3640ade0a2 100644
--- a/plat/nvidia/tegra/soc/t194/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t194/plat_setup.c
@@ -304,6 +304,9 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
return (plat_params_from_bl2_t *)(uintptr_t)val;
}
+/*******************************************************************************
+ * Handler for late platform setup
+ ******************************************************************************/
void plat_late_platform_setup(void)
{
#if ENABLE_STRICT_CHECKING_MODE
@@ -314,3 +317,11 @@ void plat_late_platform_setup(void)
mce_enable_strict_checking();
#endif
}
+
+/*******************************************************************************
+ * Handler to indicate support for System Suspend
+ ******************************************************************************/
+bool plat_supports_system_suspend(void)
+{
+ return true;
+}
diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
index 4ef9558eec..832b8d647f 100644
--- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
@@ -394,6 +394,15 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
*/
tegra_reset_all_dma_masters();
+ /*
+ * Mark PMC as accessible to the non-secure world
+ * to allow the COP to execute System Suspend
+ * sequence
+ */
+ val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
+ val &= ~PMC_SECURITY_EN_BIT;
+ mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
+
/* clean up IRAM of any cruft */
zeromem((void *)(uintptr_t)TEGRA_IRAM_BASE,
TEGRA_IRAM_A_SIZE);
@@ -480,12 +489,14 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
tegra_bpmp_resume();
}
- /* sc7entry-fw is part of TZDRAM area */
if (plat_params->sc7entry_fw_base != 0U) {
+ /* sc7entry-fw is part of TZDRAM area */
offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;
tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,
plat_params->tzdram_size + offset);
+ }
+ if (!tegra_chipid_is_t210_b01()) {
/* restrict PMC access to secure world */
val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
val |= PMC_SECURITY_EN_BIT;
@@ -533,10 +544,11 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
tegra_fc_lock_active_cluster();
/*
- * Resume PMC hardware block for Tegra210 platforms supporting sc7entry-fw
- */
- if (!tegra_chipid_is_t210_b01() && (plat_params->sc7entry_fw_base != 0U))
+ * Resume PMC hardware block for Tegra210 platforms
+ */
+ if (!tegra_chipid_is_t210_b01()) {
tegra_pmc_resume();
+ }
return PSCI_E_SUCCESS;
}
diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c
index da1f1b33eb..c32772de86 100644
--- a/plat/nvidia/tegra/soc/t210/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t210/plat_setup.c
@@ -236,6 +236,13 @@ void plat_late_platform_setup(void)
val |= PMC_SECURITY_EN_BIT;
mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
}
+
+ if (!tegra_chipid_is_t210_b01()) {
+ /* restrict PMC access to secure world */
+ val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
+ val |= PMC_SECURITY_EN_BIT;
+ mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
+ }
}
/*******************************************************************************
@@ -255,3 +262,21 @@ void plat_gic_setup(void)
*/
tegra_fc_enable_fiq_to_ccplex_routing();
}
+/*******************************************************************************
+ * Handler to indicate support for System Suspend
+ ******************************************************************************/
+bool plat_supports_system_suspend(void)
+{
+ const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
+
+ /*
+ * sc7entry-fw is only supported by Tegra210 SoCs.
+ */
+ if (!tegra_chipid_is_t210_b01() && (plat_params->sc7entry_fw_base != 0U)) {
+ return true;
+ } else if (tegra_chipid_is_t210_b01()) {
+ return true;
+ } else {
+ return false;
+ }
+}
diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk
index 4f2db53864..0d27bcdc55 100644
--- a/plat/nvidia/tegra/soc/t210/platform_t210.mk
+++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk
@@ -57,3 +57,6 @@ ERRATA_A53_855873 := 1
# Skip L1 $ flush when powering down Cortex-A57 CPUs
SKIP_A57_L1_FLUSH_PWR_DWN := 1
+
+# Enable higher performance Non-cacheable load forwarding
+A57_ENABLE_NONCACHEABLE_LOAD_FWD := 1